High Speed Memory Interfacing 800MHz DDR3 Memory Lab

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High Speed Memory Interfacing 800MHz DDR3 Memory Lab

Software Requirements Overview 1) The Quartus II software version 11.1 2) Modelsim software version 11.1 This lab focuses on compiling and simulating a pre-made DDR3 interface. The memory interface is configured as 8 bits wide running at 800MHz with a quarter rate controller. The design was created using the standard UniPHY MegaWizard. To save time today the design has been preassembled and the MegaWizard already run. The design has both timing and placement constraints which can be seen in the design directory. The Quartus II software tool synthesizes the DDR3 800MHz interface and produces the timing analysis results which can be viewed in the TimeQuest tool. Additionally the design has an RTL test bench which is used in the simulation section of the lab. Step 1 Open Quartus and DDR3 example design 1. Open Quartus II 2. Be sure that the target device is 5SGXEA7H3F35C2 3. Go to File => open project and then navigate to the memory folder within the 28nm labs folder (c:\altera_28nm_labs) 4. Select and restore ddr3_800_example.qar MegaWizard 5. Go to Tools =>MegaWizard Plug-In Manager => Edit existing custom megafunction variation 6. From the drop down menu select c:\altera_28nm_labs\memory\qr800 => open the qr800 folder and select the ddr3_800.v file and press next. This will open the MegaWizard. 7. Look at the Memory Timing tab and note the specs. When doing your own design, you may need to de-rate tds, tdh, tis and tih, depending on the load and board topology. 8. Look at the Board Settings tab for accurate timing analysis of the interface. 9. For the exercise, the memory controller does NOT need to be regenerated. (If it was regenerated, do not add it to the current project). You may close the MegaWizard after examining the current configuration. Close the MegaWizard window. 2

Compile the design High Speed Memory Interfacing 800MHz DDR3 Memory Lab 10. Compile the project by going to the Quartus II toolbar Processing => Start Compilation (or use the icon on the toolbar) 11. [Takes around 10 minutes] This is a good time to ask questions! 12. Ignore the 3 errors about EDA This is our ability to talk to external tools like Synopsis, Mentor, etc. We will enable this feature in a later version of Quartus II Step 2 Exercises 13. Open the compilation report by going to Processing => Compilation report 14. In the Table of Contents window find TimeQuest Timing Analyzer => Fast 850mV 0C Model => Report DDR 15. Take a look at the Before Calibration tab and note the negative slacks on the write/read setup/hold 16. Take a look at if0 write and if0 Read Capture and check out the after calibration margin. 17. For a summary of the interface timing summary, open the if0 folder. (if0 Write). 18. Let s look at the timing of the path in detail. Look at either window called Path #1: Setup slack is click on the extra fitter information tab. Scroll to the bottom and you can see the path this interface is using. This is very helpful if you re not meeting timing. You can dig into the fitter detail. Next, click on the Data Path tab. The location column spells out the path in detail. TimeQuest 19. Open TimeQuest by clicking on the larger Clock Icon on the Quartus II toolbar 20. Select Report Fmax => Note the DDR3 interface fmax 21. Under the Report Device Specific folder => What is the write leveling tdqss setup and hold margin in ps? DDR3 800MHz (1600 Mbps) Simulation 22. Generating the DDR3 models from Quartus II 23. Double click the Quartus II 11.1 (64-bit) icon to open it. 24. Close the welcome window and hit ok when the Cannot connect to Altera window appears. 3

25. Select File-> open project High Speed Memory Interfacing 800MHz DDR3 Memory Lab 26. Find the Memory folder on the c:\ drive 27. Find the design file by going to Memory\qr800\qr800\ddr3_800_example_design\simulation 28. Select the file "generate_sim_example_design.qpf" and hit open 29. If the tcl Console window isn t already open, then open it from the Quartus II Toolbar by going to view utility windows Tcl console. (You can check if it s open by looking for tcl console in one of the lower windows.) 30. From the Quartus II Toolbar select Tools -> Tcl Scripts... -> generate_sim_verilog_example_design.tcl 31. and click "Run". (Do not hit ok ) 32. In the Tcl console you should see the message Generating Verilog example design. It will take a few minutes for this message to appear in the console, so please be patient. Once you see this you can move on to the next step. (if you take the lab files to run on your own machine later, you may need to correct the paths on lines 285 and 302) ----------------For the VHDL users this is an FYI----------------- 33. To generate the VHDL example design, open the Quartus project "generate_sim_example_design.qpf" and select Tools -> Tcl Scripts... - > generate_sim_vhdl_example_design.tcl and click "Run". 34. Alternatively, you can run "quartus_sh -t generate_sim_vhdl_example_design.tcl" at a Windows or Linux command prompt. 35. The generated files will be found in the subdirectory "vhdl". -------------------------------------------------------------------------------- 4

Simulation with ModelSim 36. Open Modelsim (double click modelsim icon on the desktop) 37. Close welcome screen 38. Go to File Change directory 39. Navigate to : c:\altera_28nm_labs\memory\qr800\ddr3_800_example_design\si mulation\verilog\mentor 40. In the ModelSim transcript window type 41. do run.do (all lower case) 42. The simulation files will then be loaded 43. The files will take a few moments to load and the simulation will then begin. 44. When the simulation is complete you will see this message 5

45. Select No 46. You should now see the simulation results 47. Right-click in the waveform window and select Zoom-full, you can now see the complete DDR3 800MHz (1600 Mbps) initialization and data transfer. Exercises 48. When does initialization and calibration complete? 49. Was initialization and calibration successful or not? How do you know? Note that the simulation pass goes hi and the fail remains low. This indicated that the simulation was successful. 6

Summary Use Quartus II to generate a 800MHz DDR3 design Analyse the design using Quartus II and Timequest to see if it meets performance 1. Analyse the design using Modelsim to see if it meets performance END OF EXERCISE Notes on DDR3 Lab 7

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