www.ti.cm Applicatin Nte Memry Map f Visin SDK Applicatin Reprt Dec 2016 1. Intrductin... 2 2. Memry Sectins in VISION SDK Memry Map... 2 3. VSDK Memry Map Table... 3 4. Sftware and Hardware Cnstraints t Cnsider Fr Deciding Memry Map... 4 4.1 Hardware Cnstraints... 4 4.2 Sftware Cnstraints... 4 5. Memry Allcatin... 4 5.1 External Buffer Memry Allcatin... 5 5.2 Internal Buffer Memry Allcatin... 6 5.3 Static Memry sectins Allcatin... 7 6. Memry map f the applicatin... 7 6.1 Adding a new sectin t memry map... 8 6.2 Changing size f a sectin in the memry map... 9 6.3 Hw T - Add a new memry map... 9 6.4 Hw T Mdify Linux/Bis VSDK Memry Map... 9 6.4.1 Cache and MMU cnfiguratins... 10 6.4.2 Mdify default memry maps f VSDK... 11 7. Revisin Histry... 17 1 Memry Map Cnfiguratin f visin SDK
Applicatin Nte www.ti.cm 1. Intrductin The dcument discusses abut the Visin SDK (VSDK) memry map implementatin n TDA2xx, TDA2Ex and TDA3xx. TI Visin SDK is a multi-prcessr multi-channel sftware develpment platfrm, which enables the easy integratin f new visin applicatins using different hetergeneus CPUs f TI ADAS SCs. VISION SDK allws different usecases fr different platfrms and hence a generic memry map might nt be sufficient fr all users. This dcument gives insight n different sectins f the memry map that a user can change fr their usecases. It is expected that the user has gne thrugh the belw dcumentatins t understand the hardware and sftware architecture/partitining. TDAxx SC architecture (TRM) Visin SDK (Links & chain) Framewrk UserGuides VisinSDK_SW_Architecture_Details.pdf VisinSDK_SW_Architecture_Overview.pdf VSDK Develper guides VisinSDK_DevelpmentGuide.pdf VisinSDK_Linux_DevelpmentGuide.pdf 2. Memry Sectins in VISION SDK Memry Map VISION SDK has multiple memry map cnfiguratins supprted based n the usage scenaris and available ttal memry n varius platfrms. The ttal system memry is divided int varius sub-sectins/prcessrs. The brad classificatin f the sectins is listed belw: Shared regins: SRs are different memry partitins that are shared acrss prcessrs SR0: Shared Regin 0. This shared regin is used t allcate memry fr data structures needed fr inter prcessr cmmunicatin. This shared regin is nt cached n any f the prcessr cres. SR1_FRAME_BUFFER_MEM: This memry regin is used fr allcating data buffers fr capturing vide data, scaling, Alg prcessing & displaying vide frames. Accessible & cached frm all cres. SR2_MEM: Used nly with VSDK Linux reserving memry fr CMEM allcatins (cntiguus memry fr Linux) SYSTEM_IPC_SHM_MEM: Nn-Cached Memry sectin fr keeping IPC link data structures Lg Mem: REMOTE_LOG_MEM: Nn-Cached Memry sectin reserved and accessible frm all prcessr cres t dump the debug/prfile print messages. Each prcessr cre uses VPS_printf() t dump the status/debug messages n this memry regin. Remte Debug Client running n master cres (IPU1-0 fr Bis and A15 in case f Linux) reads this memry regin and prints the cntent n the (UART) cnsle. LINK_STATS_MEM: Nn Cached Memry sectin reserved and accessible frm all prcessr cres t dump the Link statistics TRACE_BUF: Remte prc lgs, nn-cached, used nly with VSDK Linux DDR Cde/data: CODE_MEM: Partitin fr cde sectin f each cre s executable binary DATA_MEM: Partitin fr data sectin f each cre s executable binary Internal memry: OCMC_RAM: Internal Memry sectin accessible frm all prcessr cres L2_SRAM: DSP L2 Internal Memry sectin, nly accessible frm DSP cre Linux mem: Memry partitins given t Linux kernel memry manager 2 Memry Map Cnfiguratin f visin SDK
www.ti.cm Applicatin Nte Others: HDVPSS_DESC_MEM: Memry sectin used by BSP/STW. It is used by these driver fr its internal descriptr data structures. 3. VSDK Memry Map Table Refer the.xs file under \visin_sdk\build\tdaxxx\ fr the cmplete memry map cnfiguratin, Fr example, \visin_sdk\build\tda2xx\mem_segment_definitin_512mb_bis.xs defines the memry map fr TDA2x with 512MB DDR. Als refer the generated map files under \visin_sdk\binaries\tdaxxx_evm_xxx_all\visin_sdk\bin\tdaxxx-evm\ Fr ample, visin_sdk_ipu1_0_release.xem4.map, Memry sectins are arranged as belw Name Origin Length Used Unused Attr ---------------------- -------- --------- -------- -------- ---- L2_ROM 00000000 00004000 000005ec 00003a14 RWIX L2_RAM 20000000 00010000 00000000 00010000 RWIX OCMC_RAM1 40300000 00080000 00080000 00000000 RWIX OCMC_RAM2 40400000 00100000 00000000 00100000 RWIX OCMC_RAM3 40500000 00100000 00000000 00100000 RWIX DSP1_L2_SRAM 40800000 00048000 00000000 00048000 RWIX DSP2_L2_SRAM 41000000 00048000 00000000 00048000 RWIX NDK_MEM 85800000 00200000 00000000 00200000 RWIX SR1_FRAME_BUFFER_MEM 85a00000 0fa00000 0fa00000 00000000 RWIX DSP1_CODE_MEM 99000000 00200000 00000000 00200000 RWIX DSP1_DATA_MEM 99200000 01800000 00000000 01800000 RWIX IPU1_1_CODE_MEM 9d000000 00200000 00000000 00200000 RWIX IPU1_1_DATA_MEM 9d200000 00200000 00000000 00200000 RWIX IPU1_1_BSS_MEM 9d400000 00200000 00000000 00200000 RWIX IPU1_0_CODE_MEM 9d600000 00600000 004fa45d 00105ba3 RWIX IPU1_0_DATA_MEM 9dc00000 00400000 00000000 00400000 RWIX IPU1_0_BSS_MEM 9e000000 00d00000 00bf5cdc 0010a324 RWIX DSP2_CODE_MEM 9f000000 00200000 00000000 00200000 RWIX DSP2_DATA_MEM 9f200000 00a00000 00000000 00a00000 RWIX SR0 a0100000 00100000 00100000 00000000 RWIX REMOTE_LOG_MEM a0200000 00040000 00027890 00018770 RWIX LINK_STATS_MEM a0240000 00080000 00020d9c 0005f264 RWIX SYSTEM_IPC_SHM_MEM a02c0000 00040000 00035a60 0000a5a0 RWIX HDVPSS_DESC_MEM a0300000 00100000 000b07c0 0004f840 RWIX TRACE_BUF a0400000 00060000 00008000 00058000 RWIX EXC_DATA a0460000 00010000 00000000 00010000 RWIX PM_DATA a0470000 00080000 00000000 00080000 RWIX EVE1_VECS_MEM a2000000 00080000 00000000 00080000 RWIX EVE1_CODE_MEM a2080000 00200000 00000000 00200000 RWIX EVE1_DATA_MEM a2280000 00d80000 00000000 00d80000 RWIX EVE2_VECS_MEM a3000000 00080000 00000000 00080000 RWIX 3 Memry Map Cnfiguratin f visin SDK
Applicatin Nte www.ti.cm EVE2_CODE_MEM EVE2_DATA_MEM EVE3_VECS_MEM EVE3_CODE_MEM EVE3_DATA_MEM EVE4_VECS_MEM EVE4_CODE_MEM EVE4_DATA_MEM a3080000 00200000 00000000 00200000 RWIX a3280000 00d80000 00000000 00d80000 RWIX a4000000 00080000 00000000 00080000 RWIX a4080000 00200000 00000000 00200000 RWIX a4280000 00d80000 00000000 00d80000 RWIX a5000000 00080000 00000000 00080000 RWIX a5080000 00200000 00000000 00200000 RWIX a5280000 00d80000 00000000 00d80000 RWIX Refer visin_sdk\include\link_api\systemlink_cmmn_if.h fr the available Memry Heaps, Here is a brief list; detailed descriptin is in systemlink_cmmn_if.h file SYSTEM_HEAPID_DDR_NON_CACHED_SR0: Heap ID f heap in DDR, This is nn-cached memry SYSTEM_HEAPID_DDR_CACHED_SR1: Heap ID f heap in DDR, This is cached memry SYSTEM_HEAPID_OCMC_SR2: Heap ID f heap in OCMC SYSTEM_HEAPID_RESERVED1: Heap ID f heap in DDR, This is cached memry SYSTEM_HEAPID_RESERVED2: Heap ID f heap in L2 Memry, Internal memry 4. Sftware and Hardware Cnstraints t Cnsider Fr Deciding Memry Map 4.1 Hardware Cnstraints AMMU in IPU1/2 handles large memry segments f size 512MB/32MB nly and there can be 4 such segments. Fr EVE we have nly 32 TLB entries t map the memry, ne TLB can map a max f 16MB 4.2 Sftware Cnstraints Fr VSDK Linux, the first 64MB frm 0x8000 0000 is reserved fr Linux Kernel Frame Buffer Shared Regin (SR1) is mapped n A15 Linux. But if user wants Linux side app/links t allcate memry/buffers frm any ther heap, then user need t mmap the physical address in the applicatin cde t map thse memry/buffers n A15. Imprtant things t pay attentin t, while prting the map file are: DDR, OCMC & DSP/EVE SRAM sizes Cre specific cde/data/vecs sizes Size f the shared frame buffer pl DDR is divided int 2 sectins: cached and nn-cached. The cached part is used mainly fr frame buffer (SR1) and cre specific cde/data sectins. The nn-cached part is used mainly fr Visin SDK lg buffers, IPC shared data structure (SR0) HDVPSS descriptrs etc. 5. Memry Allcatin This sectin describes the different methds by which memry is allcated in the Visin SDK framewrk. The Visin SDK framewrk als supprts static memry allcatin. 4 Memry Map Cnfiguratin f visin SDK
www.ti.cm Applicatin Nte Memry in Visin SDK framewrk is allcated fr the fllwing purpses Purpse Regin in memry used fr allcatin Type f allcatin (Dynamic, Static) External Buffer memry fr string algrithms results and/r SR1_FRAME_BUFFER_MEM Dynamic (heap based) and/r Static HW engine results Internal Buffer memry fr string algrithms results and/r HW engine results Ntify Shared regin ONLY used during Ntify setup (IPC_Start()), nt used later Temprary scratch memry in internal memry fr algrithms results OCMC_RAM SR0 DMEM in EVE L2SRAM in DSP Shared memry fr remte cre REMOTE_LOG_MEM Static print lgs Shared memry fr link statistics LINK_STATS_MEM Static Shared memry fr inter SYSTEM_IPC_SHM_MEM Static prcessr cmmunicatin VPDMA descriptr memry fr HDVPSS_DESC_MEM Static VIP, VPE HW engines CPU specific memry fr BIOS bjects like semaphres, tasks, interrupts, clcks CPU specific data sectin Static Dynamic (heap based) and/r Static Dynamic (heap based) The subsequent sectins prvide mre details n each type f memry allcatin In the belw descriptin, <sc> = tda2xx, tda2ex, tda3xx, tda2x-entry <ddr_size> = 128mb, 256mb, 512mb, 1024mb <s_type> = Bis, Linux 5.1 External Buffer Memry Allcatin Lcatin where memry map is specified Dynamic (nn-heap, linear allcatin) The memry regin used fr external buffer memry allcatin is specified via the belw file File: visin_sdk\build\<sc>\mem_segment_definitin_<ddr_size>_<s_type>.xs Variable SR1_FRAME_BUFFER_SIZE The heap frm which memry is allcated is defined in file FILE: visin_sdk\src\utils_cmmn\src\utils_mem_ipu1_0.c #pragma DATA_SECTION(gUtils_memHeapDDR, ".bss:heapmemddr") FILE: visin_sdk\src\utils_cmmn\include\utils_mem_cfg.h #define UTILS_MEM_HEAP_DDR_CACHED_SIZE This heap is placed in SR1_FRAME_BUFFER sectin via the IPU1-0 cfg file FILE: visin_sdk\src\main_app\<sc>\ipu1_0\ipu1_0.cfg 5 Memry Map Cnfiguratin f visin SDK
Applicatin Nte www.ti.cm Prgram.sectMap[".bss:heapMemDDR"] = "SR1_FRAME_BUFFER_MEM"; The heap is defined nly n IPU1-0 CPU; all ther CPUs sends message t IPU1-0 t allcate memry. This is dne internally inside the Utils_memAllc APIs. API t allcate and free memry Belw APIs are used t allcate and free memry FILE: visin_sdk\src\utils_cmmn\include\utils_mem.h API: Utils_memAllc() with heapid as SYSTEM_HEAPID_DDR_CACHED_SR1 Utils_memFree() with heapid as SYSTEM_HEAPID_DDR_CACHED_SR1 Utils_memGetHeapStats() with heapid as SYSTEM_HEAPID_DDR_CACHED_SR1 Other APIs frm this file are nt recmmended t be used by users and are used internally by the framewrk Using static memry allcatin When a system wants t use static memry allcatin and avid the heap, it shuld set the size f this heap segment as 0 by mdifying the #define in utils_mem_cfg.h file Define static memry bjects (arrays, data structures) in IPU1-0 use-case file. Make sure the bjects are placed in data sectin.bss:heapmemddr" via #pragma The links which supprt static memry allcatin allw passing f memry regin pinters frm use-case file via System_LinkMemAllcInf data structure When creating a link frm a use-case, user shuld nw pass memry pinter allcated statically frm use-case file. This prevents the link fr allcating memry internally. Thus dynamic memry allcatin is avided See capture link capturelink.h fr example See use-case visin_sdk\examples\tda2xx\src\usecases\vip_single_cam_view fr sample usage f passing user memry pinter t a link NOTE: In the use-case the memry allcatin is still dne using Utils_memAllc APIs. In a fully static memry system, this API wn t be used by the user. The links assert if the memry segment size passed t it is smaller than what is needed. In this case, it als reprts the size required by the link. When creating user specific AlgPlugins same mechanism shuld be used, i.e algrithm plugin shuld take memry pinter passed frm use-case file rather than allcating memry internally. See Capture link fr example 5.2 Internal Buffer Memry Allcatin Lcatin where memry is specified The memry regin used fr buffer memry allcatin is specified via the belw file File: visin_sdk\build\<sc>\mem_segment_definitin_<ddr_size>_<s_type>.xs Variable OCMC1_SIZE The heap frm which memry is allcated is defined in file FILE: visin_sdk\src\utils_cmmn\src\utils_mem_ipu1_0.c 6 Memry Map Cnfiguratin f visin SDK
www.ti.cm Applicatin Nte #pragma DATA_SECTION(gUtils_memHeapOCMC, ".bss:heapmemocmc") FILE: visin_sdk\src\utils_cmmn\include\utils_mem_cfg.h #define UTILS_MEM_HEAP_OCMC_SIZE This heap is placed in OCMC sectin via the IPU1-0 cfg file FILE: visin_sdk\src\main_app\<sc>\ipu1_0\ipu1_0.cfg Prgram.sectMap[".bss:heapMemOCMC"] = "OCMC_RAM"; The heap is defined nly n IPU1-0 CPU; all ther CPUs send a cmmand t IPU1-0 t allcate memry. This is dne internally inside the Utils_memAllc APIs. API t allcate and free memry Belw APIs are used t allcate and free memry FILE: visin_sdk\src\utils_cmmn\include\utils_mem.h API: Utils_memAllc() with heapid as SYSTEM_HEAPID_OCMC_SR2 Utils_memFree() with heapid as SYSTEM_HEAPID_OCMC_SR2 Utils_memGetHeapStats() with heapid as SYSTEM_HEAPID_OCMC_SR2 Other APIs frm this file are nt recmmended t be used by users and are used internally by the framewrk 5.3 Static Memry sectins Allcatin The memry regin used fr these sectins are specified via the belw file File: visin_sdk\build\<sc>\mem_segment_definitin_<ddr_size>_<s_type>.xs Variable REMOTE_LOG_SIZE fr Remte Lg memry Variable SYSTEM_IPC_SHM_SIZE fr inter-prcessr cmmunicatin Variable LINK_STATS_SIZE fr Link Statistics Variable HDVPSS_DESC_SIZE fr VPDMA descriptrs 6. Memry map f the applicatin Memry map f the entire usecase is gverned by fllwing artifacts. 1. DDR_MEM variable in Rules.make (lder versins) r \visin_sdk\cnfigs\tdaxxx_evm_<os>_all\cfg.mk (fr VSDK versin 2.11 and abve) List f VSDK files need t be reviewed & mdified 1. /visin_sdk/build/tdaxxx/mem_segment_definitin_<ddr_mem>_<os>.xs 2. /visin_sdk/src/utils_cmmn/include/utils_mem_cfg.h 3. /visin_sdk/src\main_app\tda2xx\ipu1_0 \ Ammu1.cfg r Ammu1_linux.cfg (if yu mdify the IPU1 memry map) 4. /visin_sdk/src\main_app\tda2xx\ipu2\ Ammu2.cfg r Ammu2_linux.cfg (if yu mdify the IPU2 memry map) 5. /visin_sdk/src/main_app/tda2xx/eve_cmmn/tlb_cnfig_eve_cmmn.c (if yu mdify any EVE1-4 memry map) 6. /visin_sdk/include/link_api/system_vring_cnfig.h (nly fr Linux/HLOS build) 7. /visin_sdk/hls/src/sa/include/sa_mem_map.h (nly fr Linux/HLOS build) 7 Memry Map Cnfiguratin f visin SDK
Applicatin Nte www.ti.cm 8. /visin_sdk/src/links_cmmn/system/system_rsc_table_ipu.h (nly fr Linux/HLOS build, if resurce table mdificatin required) 9. /visin_sdk/src/links_cmmn/system/system_rsc_table_dsp.h (nly fr Linux/HLOS build, if resurce table mdificatin required) List f Linux Kernel files need t be mdified 10. /ti_cmpnents/s_tls/kernel/map/arch/arm/bt/dts/dra7-evm-infadas.dts (Fr TDA2x) 11. /ti_cmpnents/s_tls/kernel/map/arch/arm/bt/dts/dra7-evm.dts (Fr TDA2x) 12. /ti_cmpnents/s_tls/kernel/map/arch/arm/bt/dts/dra72-evm-infadas.dts (Fr TDA2Ex) 13. /ti_cmpnents/s_tls/kernel/map/arch/arm/bt/dts/dra72-evm.dts (Fr TDA2Ex) #1 DDR_MEM is an envirnment variable that tells build system which.xs is t be picked up fr the final executable. #2 The.xs file verrides default implementatin fr the platfrm defined by xdc.runtime. This file can be mdified t increase/decrease size f a sectin r add/remve sectins frm the memry map. Fr Linux/HLOS, Linux enables L2MMU fr each cre, s all the addresses mentined in the.xs file are slave virtual addresses. #3 The.dts file is used t reserve memry frm Linux, this is a platfrm specific file. This ensures Linux and bis side dn t verwrite int each ther. Typically the bis side needs sme memry sectins and rest all can be given t Linux. Essentially this creates a few hles in Linux memry that is later mapped t user space at the applicatin startup time. 6.1 Adding a new sectin t memry map While adding a new sectin in the memry map f ipu/dsp/eve/a15, fllwing things needs t be taken care f: 1. Add a new sectin in apprpriate.xs file by defining NEW_SECTION_SIZE, NEW_SECTION_ADDR & NEW_SECTION_MEM (just fllw the cnventin used in.xs file) 2. Its advised t remve r reduce sme unwanted sectins t free-up the memry required fr the new sectin 3. Make sure the ttal memry shuld nt exceeds the ttal available physical memry 4. Make sure the new sectin desn t verlap with any ther sectins. 5. If yu add any new memry sectin and, the data/cde crrespnding t that can be placed int the sectin by adding Prgram.sectMap in the apprpriate \visin_sdk\src\main_app\tdaxxx\<cpu>\<cpu>.cfg file. 6. In case f Linux, it shuld lie within the hle f memry declared in.dts file in kernel using /memreserve 7. If needed, /memreserve can be used t increase the size f the hle accmmdate new sectin s memry requirement. 8. If this newly added sectin has t be mapped int L2MMU f ipu/dsp by Linux and hence it needs t be added in the resurce table i.e. in system_rsc_table_ipu.h r system_rsc_table_dsp.h accrdingly. 9. If this sectin is ging t be accessed frm Linux user space r kernel space, this mapping needs t be taken care by the applicatin r thrugh OSA_mem mdule in visin_sdk 8 Memry Map Cnfiguratin f visin SDK
www.ti.cm Applicatin Nte 10. If yu are changing base addresses and sizes fr IPU s, DSP s carve-ut sectins (cde/data) and if yu plan t change CMA address in linux kernel (.dts) please ensure yu als make this changes t visin_sdk\include\system_vring_cnfig.h. 11. Refer sectin 6.4: Hw T Mdify Linux/Bis VSDK Memry Map fr mre details 6.2 Changing size f a sectin in the memry map While changing the size f the sectin in the memry map frm ipu/dsp/eve/a15, fllwing things needs t be taken care f: 1. D changes in respective.xs file fr the sectin sizes 2. Its advised t reduce sme unwanted sectins t free-up the memry required fr new size (increase) 3. Make sure the ttal memry shuld nt exceeds the ttal available physical memry 4. Make sure the new sectin desn t verlap with any ther sectins. 5. In case f Linux, it shuld lie within the hle f memry declared in.dts file in kernel using /memreserve 6. If needed, /memreserve can be used t increase the size f the hle accmmdate new sectin s memry requirement. 7. As yu are mdifying existing sectin, n need t change resurce table mappings, the updated value will be picked up in resurce table in the build prcess. 8. If yu are changing base addresses and sizes fr IPU s, DSP s carve-ut sectins (cde/data) and if yu plan t change CMA address in linux kernel (.dts) please ensure yu als make this changes t visin_sdk\include\system_vring_cnfig.h. 9. Refer sectin 6.4: Hw T Mdify Linux/Bis VSDK Memry Map fr mre details 6.3 Hw T - Add a new memry map In general, if yu are planning t have yur wn memry map fr the applicatin, yu can fllw these steps 1. Evaluate memry requirements f the sectins e.g. (Is 256 MB SR1 sufficient r yu need mre r less?) 2. Add apprpriate.xs file under $INSTALL_DIR/visin_sdk/build/tdaxxx/, fr example mem_segment_definitin_512mb.xs 2. Mdify DDR_MEM_XXXX, fr example DDR_MEM_512M variable in Rules.make (lder versins) r \visin_sdk\cnfigs\tdaxxx_evm_<os>_all\cfg.mk (fr VSDK versin 2.11 and abve) 3. Mdify apprpriate platfrm ISI build files t pick the crrect memry map (.xs) file, fr example, refer belw files fr TDA3x, a. \visin_sdk\build\tda3xx\cnfig_arp32.bld b. \visin_sdk\build\tda3xx\cnfig_c66.bld c. \visin_sdk\build\tda3xx\cnfig_m4.bld d. Etc. 4. Nw fllw the sectin 6.4: Hw T Mdify Linux/Bis VSDK Memry Map fr mre details and hw t mdify all necessary VSDK and Linux kernel files 6.4 Hw T Mdify Linux/Bis VSDK Memry Map The memry map f cmplete VISION SDK is cntrlled in 9 Memry Map Cnfiguratin f visin SDK
Applicatin Nte www.ti.cm \visin_sdk\build\tdaxxx\cnfig_<isi>.bld The mem_segment_definitin (fr example - mem_segment_definitin_1024mb_linux.xs) file is included in this build cnfiguratin file, size f each sectins are recnfigured in.xs file. Fr example, DSP cde size and DSP data size sectin can be changed by mdifying the fllwing entries. DSP1_CODE_SIZE = 3*MB; DSP1_DATA_SIZE = 13*MB; The base addresses f each sectin are incremented based n the base address f previus sectin and the size f the previus sectin. Fr example, if sectins are created in the numerical rder, base address f Sectin 2 is calculated as belw: <Start Addr f Sect 2> = <Start Addr f Sec 1> + <Size f Sect 1> T mdify the memry map, user needs t cnsider the fllwing: Refer t the hardware limitatins and sftware limitatins in sectin 4: We assume a ne-t-ne mapping f AMMU virtual address t physical address. The ther sectins like Remte Debug, HDVPSS Shared Memry etc. are read directly frm the build cnfiguratin file Changes in the Linux memry size in build cnfiguratin file has t be reflected in the bt arguments f the Linux kernel using mem=<size>m entry. Cnsider the verall buffer requirement fr the specific usecase befre mdifying the Frame Buffer r Meta data buffer r BitsBuffer sectin sizes. The current default memry maps f VSDK (as per 2.12 releases) as belw TDA2xx Bis 512 MB TDA2xx Linux 1024 MB TDA2Ex Bis 512 MB TDA2Ex Linux 1024 MB TDA3xx Bis 512 MB TDA3xx Bis 128 MB 6.4.1 Cache and MMU cnfiguratins List f VSDK files sets the Cache and MMU cnfiguratins <1> DSP DSP L1 & L2 Cache cnfiguratin is in \visin_sdk\src\main_app\tdaxxx\cfg\dsp_cmmn.cfg, Belw the default cache size setting fr L1P, L1D and L2 as 32K var Cache = xdc.usemdule('ti.sysbis.family.c66.cache'); Cache.initSize.l1pSize = Cache.L1Size_32K; Cache.initSize.l1dSize = Cache.L1Size_32K; Cache.initSize.l2Size = Cache.L2Size_32K; Cache ON/OFF setting f DSP als in \visin_sdk\src\main_app\tdaxxx\cfg\dsp_cmmn.cfg /* Set cache sectins */ /* cnfigure MARs, by default cache is enabled fr the entire memry regin */ fr (var i = 0; i < Prgram.cpu.memryMap.length; i++) { memsegment = Prgram.cpu.memryMap[i]; Cache.setMarMeta(memSegment.base, memsegment.len, Cache.Mar_ENABLE); } 10 Memry Map Cnfiguratin f visin SDK
www.ti.cm Applicatin Nte /* set nn-cached sectins */ fr (var i = 0; i < Prgram.cpu.memryMap.length; i++) { memsegment = Prgram.cpu.memryMap[i]; if ((memsegment.name == "SR0") (memsegment.name == "REMOTE_LOG_MEM") (memsegment.name == "LINK_STATS_MEM") (memsegment.name == "SYSTEM_IPC_SHM_MEM") (memsegment.name == "OPENVX_SHM_MEM")) { Cache.setMarMeta(memSegment.base, memsegment.len, Cache.Mar_DISABLE); } } If yu plan t add any new nn-cached DSP sectin, then add the same sectin in abve cde snippet in DSP_cmmn.cfg. <2> IPU Refer belw files which set the AMMU f IPU t cnfigure MMU and Cache settings \visin_sdk\src\main_app\tdaxxx\ipu1_0\ammu1_bis.cfg r Ammu1_linux.cfg \visin_sdk\src\main_app\tdaxxx\ipu2\ammu2_bis.cfg r Ammu2_linux.cfg Map prgram cde/data & ther cached memry int ammu (cacheable) by AMMU.largePages[1] Map SR_0 & ther nn-cached data memry int ammu (nn-cacheable) by AMMU.largePages[2] Nte: Only fr TDA3x, IPU1 AMMU setting is dne in SBL. Refer \visin_sdk\src\main_app\tda3xx\ipu1_0\ammu1_bis.cfg, AMMU.cnfigureAmmu = false; If cnfigureammu is set t false, then AMMU setting is dne in SBL. <3> EVE Refer \visin_sdk\src\main_app\tda2xx\eve_cmmn\tlb_cnfig_eve_cmmn.c fr EVE memry mapping by prgramming the TLB registers, each TLB can map a max f 16MB cntiguus regin and 16MB aligned. cnst UInt32 tlbmapping[eve_tlb_num_entries*2u] ={.} <4> A15 (Bis) If A15 running Bis, then \visin_sdk\src\main_app\tda2xx\a15_0\ a15_0.cfg des the MMU & cache cnfiguratins, Mmu.setSecndLevelDescMeta(); 6.4.2 Mdify default memry maps f VSDK Please revisit & mdify the list f belw files (as required) List f VSDK files <1> /visin_sdk/build/tdaxxx/mem_segment_definitin_<ddr_size>_<os>.xs. A single file that cnfigures the entire memry map f all cres in the SC, and the majr file t be mdified if yu want t make changes in VSDK memry map. This file defines all 11 Memry Map Cnfiguratin f visin SDK
Applicatin Nte www.ti.cm the memry sectins fr IPU, DSP, EVE, A15 and ther heaps such as SR1, SR0 etc. Belw a sample sectin, DSP1_START_ADDR = 0x99000000; DSP1_CODE_SIZE = 2*MB; DSP1_DATA_SIZE = 24*MB; DSP1_CODE_ADDR = DSP1_START_ADDR; DSP1_DATA_ADDR = DSP1_CODE_ADDR + DSP1_CODE_SIZE; functin getmemsegmentdefinitin_external(cre) { memry[index++] = ["DSP1_CODE_MEM", { cmment : "DSP1_CODE_MEM", name : "DSP1_CODE_MEM", base : DSP1_CODE_ADDR, len : DSP1_CODE_SIZE }]; } If yu add any new memry sectin and, the data/cde crrespnding t that can be placed int the sectin by adding Prgram.sectMap[] in the apprpriate \visin_sdk\src\main_app\tdaxxx\<cpu>\<cpu>.cfg file. Fr example, \visin_sdk\src\main_app\tda2xx\dsp1\dsp1.cfg is the file fr DSP1 f TDA2x, and belw cde place bss:extmemnncache:ipcshm int the memry sectin SYSTEM_IPC_SHM_MEM Prgram.sectMap[".bss:extMemNnCache:ipcShm"] = "SYSTEM_IPC_SHM_MEM"; Prgram.sectMap[".bss:extMemNnCache:linkStats"] = "LINK_STATS_MEM"; Same apply fr all cres like IPU1-0, IPU1-1, IPU2, A15, DSP1-2 and EVE1-4 f TDA2x, TDA2Ex and TDA3x. The.xs file t lk at depends n SC, A15 OS and DDR memry cnfig selected; here is a list f default memry map f VSDK 2.12.0.0 SC A15 OS DDR cnfig.xs file M TDA2XX_BUILD Bis TDA2XX_512MB_DDR visin_sdk\build\tda2xx\mem_segment_definitin_512mb_bis.xs TDA2XX_BUILD Linux TDA2XX_1024MB_DDR visin_sdk\build\tda2xx\mem_segment_definitin_1024mb_linux.xs TDA3XX_BUILD d NA TDA3XX_128MB_DDR visin_sdk\build\tda3xx\mem_segment_definitin_128mb.xs TDA3XX_BUILD i NA TDA3XX_512MB_DDR visin_sdk\build\tda3xx\mem_segment_definitin_512mb.xs TDA2EX_BUILD f Bis TDA2EX_512MB_DDR visin_sdk\build\tda2ex\mem_segment_definitin_512mb_bis.xs TDA2EX_BUILD y Linux TDA2EX_1024MB_DDR visin_sdk\build\tda2ex\mem_segment_definitin_1024mb_linux.xs Mdify start address, size r even add/remve a memry sectin t change the memry map as per yur requirement. 12 Memry Map Cnfiguratin f visin SDK
www.ti.cm Applicatin Nte <2> \visin_sdk\src\utils_cmmn\include\utils_mem_cfg.h This file defines the size f majr memry heaps, and these sizes need t be in sync with abve.xs file. The memry allcatin utility/api refers this file fr the heap size. Any mdificatin f these heap size t be updated in bth utils_mem_cfg.h & mem_segment_definitin_<ddr_size>_<os>.xs file. #define UTILS_MEM_HEAP_L2_SIZE (224*1024) DSP internal memry (SRAM) #define UTILS_MEM_HEAP_L2_SIZE (24*1024) - EVE internal memry (SRAM) #define UTILS_MEM_HEAP_OCMC_SIZE (512*1024) Shared OCMC internal memry #define UTILS_MEM_HEAP_DDR_CACHED_SIZE (256*1024*1024) Shared cached DDR heap memry. <3> \visin_sdk\src\main_app\tda2xx\ipu1_0\ammu1_bis.cfg r Ammu1_linux.cfg (if yu mdify the IPU1 memry map) \visin_sdk\src\main_app\tda2xx\ipu2\ammu2_bis.cfg r Ammu2_linux.cfg (if yu mdify the IPU2 memry map) This file set IPU subsystem (cre 0 and cre 1) AMMU and Cache cnfiguratins. IPU can access nly the memry sectins mapped via AMMU. A sinle AMMU sets the memry map f bth cres (cre 0 & cre 1) f an IPU subsystem. functin init() { } Map prgram cde/data & ther cached memry int ammu (cacheable) by AMMU.largePages[1] Map SR_0 & ther nn-cached data memry int ammu (nn-cacheable) by AMMU.largePages[2] <4> /visin_sdk/src/main_app/tda2xx/eve_cmmn/tlb_cnfig_eve_cmmn.c (if yu mdify any EVE1-4 memry map) This file implements cmmn MMU cnfiguratin fr all EVE as per Visin SDK requirements There are nly 32 TLB entries in EVE, Each TBL entry can maps a max f 16MB, and need 16MB alignment, cnst UInt32 tlbmapping[eve_tlb_num_entries*2u] = { 0x84000000U, 0x84000000U, /* 08 - Fr SR1 */ 0x85000000U, 0x85000000U, /* 09 - Fr SR1 */ 0x86000000U, 0x86000000U, /* 10 - Fr SR1 */ 0x87000000U, 0x87000000U, /* 11 - Fr SR1 */ 13 Memry Map Cnfiguratin f visin SDK
Applicatin Nte www.ti.cm } evecmmnmmucnfig(); <5> /visin_sdk/include/link_api/system_vring_cnfig.h (used nly in A15 Linux Build) Vring virtual addresses (Fr Start address) f IPU & DSP are used by IPC, if it is changed in.xs file, same need t be updated in this system_vring_cnfig.h als. #ifdef BUILD_M4_0 #define IPU_PHYS_MEM_IPC_VRING #endif #ifdef BUILD_DSP_1 #define DSP_PHYS_MEM_IPC_VRING #endif #ifdef BUILD_DSP_2 #define DSP_PHYS_MEM_IPC_VRING #endif #ifdef BUILD_M4_2 #define IPU_PHYS_MEM_IPC_VRING #endif 0x9d000000 0x99000000 0x9f000000 0x95800000 <6> /visin_sdk/<hls>/src/sa/include/sa_mem_map.h (used nly in A15 Linux Build) This is an aut generated file frm [gen_system_mem_map.xs], please check and cnfirm the entries in sa_mem_map.h is matching with.xs file r the MAP file #define SR0_ADDR #define SR0_SIZE 0xa0100000 0x100000 #define SYSTEM_IPC_SHM_MEM_ADDR #define SYSTEM_IPC_SHM_MEM_SIZE 0xa02c0000 0x80000 #define REMOTE_LOG_MEM_ADDR #define REMOTE_LOG_MEM_SIZE 0xa0200000 0x40000 #define SR1_FRAME_BUFFER_MEM_ADDR 0x84203000 #define SR1_FRAME_BUFFER_MEM_SIZE 0xfa00000 <7> If a newly added sectin has t be mapped int L2MMU f ipu/dsp by Linux and hence it needs t be added in the resurce table i.e. in system_rsc_table_ipu.h r system_rsc_table_dsp.h accrdingly. /visin_sdk/src/links_cmmn/system/system_rsc_table_ipu.h (mdify if required, used nly in A15 Linux Build ) struct my_resurce_table { } struct my_resurce_table ti_ipc_remteprc_resurcetable = { } 14 Memry Map Cnfiguratin f visin SDK
www.ti.cm Applicatin Nte system_rsc_table_ipu.h define the resurce table entries fr all IPU cres. This will be incrprated int crrespnding base images, and used by the remteprc n the hstside t allcated/reserve resurces. /visin_sdk/src/links_cmmn/system/system_rsc_table_dsp.h (mdify if required, used nly in A15 Linux Build) struct my_resurce_table { } struct my_resurce_table ti_ipc_remteprc_resurcetable = { } system_rsc_table_dsp.h define the resurce table entries fr all DSP cres. This will be incrprated int crrespnding base images, and used by the remteprc n the hstside t allcated/reserve resurces. List f Linux Kernel files <1> /ti_cmpnents/s_tls/kernel/map/arch/arm/bt/dts/dra7-evm-infadas.dts (fr TDA2x) Mdify the start address f IPU1, IPU2, DSP1, DSP2 r CMEM, if any f this is changed in the memry map, /* Update the CMA regins fr Visin SDK binaries */ &ipu2_cma_pl { reg = <0x94000000 0x5000000>; &dsp1_cma_pl { reg = <0x99000000 0x4000000>; &ipu1_cma_pl { reg = <0x9d000000 0x2000000>; &dsp2_cma_pl { reg = <0x9f000000 0x1000000>; &reserved_mem { cmem_pl: cmem@a6000000 { cmpatible = "shared-dma-pl"; reg = <0xA8000000 0x4000000>; n-map; status = "kay"; <2> /ti_cmpnents/s_tls/kernel/map/arch/arm/bt/dts/dra7-evm.dts (fr TDA2x) This file reserves the memry fr SR1, SR0 and EVE data/cde memry sectins and the size. If any changes in the memry map fr any f these sectins, then update the belw cde, 15 Memry Map Cnfiguratin f visin SDK
Applicatin Nte www.ti.cm /memreserve/ 0x84000000 0x10000000; /memreserve/ 0xA2000000 0x4000000; /memreserve/ 0xA0000000 0x2000000; Mdify the start address f IPU1, IPU2, DSP1 r DSP2, if any f this is changed in the memry map, dsp1_cma_pl: dsp1_cma@99000000 { cmpatible = "shared-dma-pl"; reg = <0x99000000 0x4000000>; reusable; status = "kay"; <3> /ti_cmpnents/s_tls/kernel/map/arch/arm/bt/dts/dra72-evm-infadas.dts (fr TDA2Ex) Mdify the start address f IPU1, IPU2, DSP1 r CMEM, if any f this is changed in the memry map, /* Update the CMA regins fr Visin SDK binaries */ &ipu2_cma_pl { reg = <0x94000000 0x5000000>; &dsp1_cma_pl { reg = <0x99000000 0x4000000>; &ipu1_cma_pl { reg = <0x9d000000 0x2000000>; &reserved_mem { cmem_pl: cmem@a6000000 { cmpatible = "shared-dma-pl"; reg = <0xA8000000 0x2000000>; n-map; status = "kay"; <4> /ti_cmpnents/s_tls/kernel/map/arch/arm/bt/dts/dra72-evm.dts (fr TDA2Ex) This file reserves the memry fr SR1, SR0 memry sectins and the size. If any changes in the memry map fr any f these sectins, then update the belw cde, /memreserve/ 0x84000000 0x10000000; /memreserve/ 0xA0000000 0x2000000; 16 Memry Map Cnfiguratin f visin SDK
www.ti.cm Applicatin Nte Mdify the start address f IPU1, IPU2 r DSP1, if any f this is changed in the memry map, dsp1_cma_pl: dsp1_cma@99000000 { cmpatible = "shared-dma-pl"; reg = <0x99000000 0x4000000>; reusable; status = "kay"; Clean and Rebuild Kernel & VSDK. Nte1: If SR1 r IPU1-2 memry needs t be increased t very high value, then Mve DSP1-2 r EVE1-4 ut f 0xA000 0000 address space. This will avid the need f any IPU AMMU recnfiguratin. Nte2: T build SBL, Build apprpriate secndary bt lader as per yur memry cnfiguratin. Refer file \visin_sdk\build\makerules\build_sbl.mk fr all valid cnfiguratins. Fr examples, EMIFMODE = DUAL_EMIF_1GB_512MB (default) r DUAL_EMIF_2X512MB r SINGLE_EMIF_256MB Nte3: In case f A15 Linux, Yu als need t change DMM cnfiguratin in Ubt t set the DDR cnfiguratin, i.e., the EMIF and LISA map cnfiguratin as per custm bard r memry map. 7. Revisin Histry Versin # Date Authr Name Revisin Histry 0.1 26/12/2016 Shiju S First draft 17 Memry Map Cnfiguratin f visin SDK