ECE 425: Introduction to VLSI System Design Machine Problem 0 Due: Friday 11:59pm, Sep. 15th, 2017

Similar documents
EECE 285 VLSI Design. Cadence Tutorial EECE 285 VLSI. By: Kevin Dick Co-author: Jeff Kauppila Co-author: Dr. Arthur Witulski

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #4, Standard cell design flow (from verilog to layout, 8-bit accumulator)

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #1, Full Custom VLSI (inverter layout)

ELEC 301 Lab 2: Cadence Basic

VLSI Lab Tutorial 1. Cadence Virtuoso Schematic Composer Introduction

Revision Notes: July2004 Generate tutorial for single transistor analysis. Based on existing schematic entry tutorial developed for ECE410

ECE425: Introduction to VLSI System Design Machine Problem 3 Due: 11:59pm Friday, Dec. 15 th 2017

Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Andrew Mason and the AMSaC lab group.

Creating Verilog Tutorial Netlist Release Date: 01/13/2005(Version 2)

EE115C Digital Electronic Circuits. Tutorial 2: Hierarchical Schematic and Simulation

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #2, Schematic Capture, DC Analysis, Transient Analysis (Inverter, NAND2)

Virtuoso Layout Editor

CS755 CAD TOOL TUTORIAL

Verifying the Multiplexer Layout

Abstract Editor (Last updated: Oct. 23, 2008)

The original document link is

Laboratory 6. - Using Encounter for Automatic Place and Route. By Mulong Li, 2013

ECE471/571 Energy Efficient VLSI Design Project 2 Cadence Setup and Creation of an Inverter Due Date 11:30 am on Friday, February 2 nd, 2018

ECE 331: Electronics Principles I Fall 2014

Cadence Tutorial A: Schematic Entry and Functional Simulation Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group.

Introduction to Computer Engineering (E114)

EEC 116 Fall 2011 Lab #3: Digital Simulation Tutorial

EECS 627, Lab Assignment 3

ECE471/571 Energy Ecient VLSI Design

EE 330 Laboratory Experiment Number 11

Cadence Tutorial 2: Layout, DRC/LVS and Circuit Simulation with Extracted Parasitics

EE4111 Advanced Analog Electronics Design. Spring 2009 Experiment #4 April 6 ~ April 17

Synthesis and APR Tools Tutorial

Creating LEF File. Abstract Generation: Creating LEF Tutorial File Release Date: 01/13/2004. Export GDS:

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #3, Standard cell design flow (from schematic to layout, 8-bit accumulator)

ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS)

Place & Route: Using Silicon Ensemble

HOMEWORK 10 CMPEN 411 Due: 4/28/ :30pm

Tutorial II: Cadence Virtuoso ECE6133: Physical Design Automation of VLSI Systems Georgia Institute of Technology Prof.

CMOS VLSI Design Lab 3: Controller Design and Verification

Using Cadence Virtuoso, a UNIX based OrCAD PSpice like program, Remotely on a Windows Machine

Guide to the CSE 577 Lab and Cad tools

Cadence IC Design Manual

UNIVERSITY OF WATERLOO

Cadence Virtuoso Layout Connectivity Mark- Net Tutorial

VLSI Lab Tutorial 3. Virtuoso Layout Editing Introduction

ANALOG MICROELECTRONICS ( A)

CMOS VLSI Design Lab 3: Controller Design and Verification

Basic Analog Simulation in Cadence

Virtuoso Schematic Composer

ELEC451 Integrated Circuit Engineering Using Cadence's Virtuoso Layout Editing Tool

Actel Libero TM Integrated Design Environment v2.3 Structural Schematic Flow Design Tutorial

CS/EE 5720/6720 Analog IC Design Tutorial for Schematic Design and Analysis using Spectre

Cadence Schematic Tutorial. EEE5320/EEE4306 Fall 2015 University of Florida ECE

The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL

Cadence Tutorial: Schematic Entry and Circuit Simulation of a CMOS Inverter

UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180A DIGITAL SYSTEMS I Winter 2015

DOWNLOAD PDF CADENCE WAVEFORM CALCULATOR USER GUIDE

Laboratory 3. EE 342 (VLSI Circuit Design) - Using Spectre netlist and Calculator for simulation

ECSE-323 Digital System Design. Lab #1 Using the Altera Quartus II Software Fall 2008

Tutorial 2 Automatic Placement & Routing

HOMEWORK 9 CMPEN 411 Due: 4/12/ :30pm

Select the technology library: NCSU_TechLib_ami06, then press OK.

InDesign Part II. Create a Library by selecting File, New, Library. Save the library with a unique file name.

Cadence Virtuoso Schematic Design and Circuit Simulation Tutorial

CMOS VLSI Design Lab 4: Full Chip Assembly

CSE P567 - Winter 2010 Lab 1 Introduction to FGPA CAD Tools

EE115C Digital Electronic Circuits. Tutorial 4: Schematic-driven Layout (Virtuoso XL)

CADENCE SETUP. ECE4430-Analog IC Design

University of California, Davis Department of Electrical and Computer Engineering. EEC180B DIGITAL SYSTEMS Spring Quarter 2018

EEC 116 Fall 2011 Lab #1 Cadence Schematic Capture and Layout Tutorial

AGENT123. Full Q&A and Tutorials Table of Contents. Website IDX Agent Gallery Step-by-Step Tutorials

TUTORIAL II ECE 555 / 755 Updated on September 11 th 2006 CADENCE LAYOUT AND PARASITIC EXTRACTION

EE 330 Spring 2018 Laboratory 2: Basic Boolean Circuits

CMOS VLSI Design Lab 3: Controller Design and Verification

Amplifier Simulation Tutorial. Design Kit: Cadence 0.18μm CMOS PDK (gpdk180) (Cadence Version 6.1.5)

eproduct Designer A Simple Design and Simulation Tutorial

Another view of the standard cells called the abstract view needs to generated

EE 330 Fall 2017 Lab 1: Cadence Custom IC design tools - Setup, Schematic capture and simulation

EE 330 Spring 2018 Lab 1: Cadence Custom IC design tools Setup, Schematic capture and simulation

University of Florida EEL 3701 Dr. Eric M. Schwartz Department of Electrical & Computer Engineering Revision 0 12-Jun-16

Cadence Tutorial C: Simulating DC and Timing Characteristics 1

EE 330 Laboratory Experiment Number 11 Design and Simulation of Digital Circuits using Hardware Description Languages

This is a brief tutorial about building a Symbol for a Schematic in Cadence IC design tool environment for hierarchical design of schematics.

RC Extraction. of an Inverter Circuit

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #3, Standard cell design flow (from schematic to layout, 8-bit accumulator)

EXPERIMENT 1 INTRODUCTION TO MEMS Pro v5.1: DESIGNING a PIEZO- RESISTIVE PRESSURE SENSOR

EE434 ASIC & Digital Systems. From Layout to SPICE Simulation (Virtuoso, Calibre, HSpice) Spring 2017 Dae Hyun Kim

Quick Start Guide - Contents. Opening Word Locating Big Lottery Fund Templates The Word 2013 Screen... 3

The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL

FACULTY OF ENGINEERING MULTIMEDIA UNIVERSITY LAB SHEET DIGITAL INTEGRATED CIRCUIT

Introduction to Schematic Entry using Xilinx ISE and Digital Logic Simulation using ModelSim MXE

CADENCE TUTORIAL. San Diego State University, Department of Electrical and Computer Engineering. Amith Dharwadkar and Ashkan Ashrafi

ADOBE DREAMWEAVER CS4 BASICS

CSC116: Introduction to Computing - Java

Introduction to CCV and Cadence Virtuoso for Electronic Circuit Simulation

Lab 0 Introduction to the MSP430F5529 Launchpad-based Lab Board and Code Composer Studio

CPE/EE 427, CPE 527, VLSI Design I: VHDL design simulation, synthesis, and ASIC flow, Laboratory #8,

USING TASKS IN OUTLOOK

The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL

Introduction to laboratory exercises in Digital IC Design.

University of California, Davis Department of Electrical and Computer Engineering. Lab 1: Implementing Combinational Logic in the MAX10 FPGA

Cadence Capture and PSpice Tutorial

Lab Assignment #1. University of Pittsburgh Department of Electrical and Computer Engineering

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science. EECS 150 Spring 2000

Transcription:

ECE 425: Introduction to VLSI System Design Machine Problem 0 Due: Friday 11:59pm, Sep. 15th, 2017 You will spend most of your lab time using the Virtuoso design tools from Cadence Design Systems. Virtuoso is a set of tools for full-custom silicon chip design, giving complete control over all design aspects to you, the designer. It has long been the industry leader in its class. This tutorial will introduce you to entering designs into Virtuoso, before you begin designing anything original. Our designs will consist of layouts, schematics, and Verilog code. A layout is a complete physical description of a chip, the three-dimensional pattern which may be fabricated on a wafer of silicon. A schematic diagram represents the components formed by the layout in a two-dimensional format. Although a one-dimensional text file is sufficient to simply list the chip s components (such a file is called a netlist), schematic diagrams enable you to draft a design in two dimensions before starting the laborious layout process. This advantage makes schematics the standard for custom circuit design. In this MP, you will be following two tutorial documents, where you will learn how to create schematics and layouts using Virtuoso. By the end of this tutorial, you will have created your own accumulator schematic, inverter layout and 2-input mux layout. You will need to submit the PDFs for the ones you create following the tutorials, not the master layouts given to you for reference. You may help each other and ask for help. Please use Piazza so that all help is shared as much as possible. We will use Linux exclusively in this class. Linux is more popular than Windows in engineering, and its more advanced features are very helpful in digital circuit design, so it s a good idea to learn it well. Please direct Linux questions to the technician in the EWS lab rather than the TA s. If you already know Linux well enough, you may also choose to log in from home. Cadence Design Framework II Virtuoso stores designs in a database system managed by the Cadence Design Framework. This means that you cannot access your data in UNIX files without exporting them first. Although it is tempting to manage your projects and files using Linux, Cadence will work better if you do things its way: 1. Always launch Cadence directly from your work directory. 2. Do not edit directories (libraries and cells) managed by Cadence. 3. There is one exception: Cadence creates temporary files to track who is editing what part of the database. After a crash, the files will be locked as if someone else is editing them. To unlock all your files, run this from your work directory: find. -name \*cdslck -exec rm {} \; Setup Please keep all coursework in your work directory, /home/your_netid/ece425.work. Always enter your 1

ece425.work directory before starting any work. To begin the tutorial, initialize your work directory with the following commands: cd ~ mkdir ece425.work cd ece425.work mkdir ece425mp0 cd ece425mp0 mkdir comptut cd comptut module load cadence/aug2016 cp -r /software/cadence- Aug2016/IC617/tools/dfII/samples/tutorials/composer/*. (Attention: There is a dot. at the end of the command!) (The cp command is in one single line) cp ~ece425/.cdsinit. cp ~ece425/.cdsenv. cp ~ece425/.cdsplotinit. cp /software/ncsu-cdk-1.6.0.beta/cdssetup/simrc. The Cadence Documentation Viewer Invoke the Cadence reference library with the command cdnshelp &. You will find the needed information by typing the keywords or clicking along the document tree. The documents related to MP0 are in the following locations: Composer Tutorial: ~ece425/comptut.pdf Cell Design Tutorial: ~ece425/celltut.pdf Please copy the two pdf files to your own folder and follow the instructions from tutorial files to do MP0. cd ~/ece425.work cp ~ece425/comptut.pdf. cp ~ece425/celltut.pdf. 2

Part 1: Schematic Design Entry (Composer Software) Composer Tutorial 1. Open comptut.pdf file. 2. Follow the instructions and complete Chapters 1 to 5 inclusive (starting on page 13 of the PDF file or under the title Starting the Schematic Composer Software in the HTML) of the composer tutorial with the following notes: Note: The comptut.pdf is written for the older version of Virtuoso, so some details will be slightly different from the new version we are using in this class. We have added notes in the PDF file (highlighted in yellow) with some of updated instructions with different menu names. We have updated all changes on first and/or second occurrences but may have not placed the updates on all repeating places so please refer to the prior note if you don t find the listed menu options. Neglect the command of icfb in the pdf. All we are using is the command virtuoso On Windows and Linux, you will be able to view the notes we added in tutorial PDF files by default, but on Mac OSX, you may need to enable options to view the contents: Mac OSX: open file on Preview. Select View->Highlights and Notes on menu bar and notes will show up on left side of the window. If you encounter the following pop up window while opening any schematic, select Always. -OR- Figure. Sample screenshots of pop-up window regarding license warning. Chapter 1: 1. Start with Starting the Cadence Software 2. Be sure to go into the directory of ~/ece425.work/ece425mp0/comptut/ before launching Cadence software 2. Execute module load cadence/aug2016 and type virtuoso & from the directory of ~/ece425.work/ece425mp0/comptut/ to launch the Cadence. 3. Library Path Editor window will pop up as the software launches. If not, select Tools->Library Path Editor from CDS.log window. 4. Manually add the 8 libraries according to paragraph 2, section Setting the Paths to the Tutorial Libraries in Chapter 1. Replace the your_install_dir with /software/cadence-aug2016/ic617 3

when adding the path of the 8 libraries. You can simply neglect /your_home_dir/comptut since TTL_tutor, master, tutorial, and user_asic are under current directory. After adding the 8 libraries, the Library Path Editor should be like this (the ordering of the library doesn t matter): Chapter 2: Start with Opening the Schematic Window. Figure. Library Path Editor screenshot Chapter 4: Ignore Creating a Sheet Border and Title section. 4

Print to File: 1. The Accumulator schematic in PDF format. To print the schematic, use File => Print... in the schematic window. You must print to a file (Check Send Plot Only To File under Plot Options). Make sure to turn off the Header and Mail Log options, and change the page size to be letter instead of A4. Sample configuration windows are shown as follows. The software will print to an EPS format file (e.g. accum.eps ). You could use the following command to turn it into a PDF file: ps2pdf accum.eps There will be a new pdf file named accum.pdf generated. We will talk about how to merge all the pdf files into single pdf report at the end of this document. Note: Please do NOT use screenshot. Points will be deducted for screenshot with black background with unreadable zoom setting! Figure. Plot options setting screenshot 5

Part 2: Layout Design and Verification (Virtuoso Layout Editor and Diva Software) Cell Design Tutorial 1. Execute these commands: cd ~/ece425.work/ece425mp0 cp -r ~ece425/cell_design*. cd cell_design module load cadence/aug2016 cp ~ece425/.cdsplotinit. cp /software/ncsu-cdk-1.6.0.beta/cdssetup/simrc. virtuoso & 2. Open celltut.pdf file. 3. Follow the instructions from Chapter 1, Opening Designs, through Chapter 4. Note: (1) The celltut.pdf is written for the older version of Virtuoso, so some details will be slightly different from the new version we are using in this class. We have added notes in the PDF file (highlighted in yellow) with some of updated instructions with different menu names. We have updated all changes on first and/or second occurrences but may have not placed the updates on all repeating places so please refer to the prior note if you don t find the listed menu options. Neglect the command of icfb or layoutplus in the pdf. All we are using is the command virtuoso (2) To switch layers in the current tool (page 83, Changing to metal2 ), you have two ways to do that: a. manually layout a wire and add via by yourself. The option of "Change to layer" is essentially the same with inserting a via. It just automatically insert the via for you. For example, when you need to change from metal 1 to metal 2, double click the end coordinate the path, choose "Create--Via--M2_M1", and put the via at the end of the path. Then, change the active layer to metal 2 and continue with the path. b. create shape -> geometric wire, when drawing the wire, right click to bring up the contextual menu, and choose via up/down to add a via and switch layers. 6

Print to File: 1. The Inverter layout (clearly label all pins) in PDF format. 2. The Multiplexer layout (clearly label all pins) in PDF format. Refer to the printing instruction in Composer Tutorial. Although you do not have to finish the Cell Design Tutorial to get the printouts specified above, you should go through the whole tutorial to familiarize yourself with the Virtuoso Layout Editor, since you will need to spend most of your time on laying out your cells for the next two MPs. Merge All PDF Files into a Single Report Please refer to the following sample command to merge all the PDF files to a single file, and only turn in the merged PDF file. The command below will merge three different files: in_1.pdf, in_2.pdf, in_n.pdf file into single out.pdf in the order specified. Make sure to merge the designs in order we have listed in the document (e.g. MP0: 1. Accumulator schematic, 2. Inverter layout, 3. Multiplexer layout). : pdfunite in_1.pdf in_2.pdf in_n.pdf out.pdf What to Submit: Single PDF file (mp0_netid.pdf) containing following items in order 1. Accumulator schematic 2. Inverter layout 3. Multiplexer layout 7