CARLETON UNIVERSITY Department of Electronics ELEC 267 Switching Circuits Jan 3, 28 Overview Laboratory 2. A 3-Bit Binary Sign-Extended Adder/Subtracter A binary adder sums two binary numbers for example X = and Y= => Sum = The adder, you will build, will find the sum or difference of two 3-bit two s-complement binary numbers represented here by, X = x 2 x x and Y= y 2 y y, and show the result on four output lines. Since some adder applications only do not allow the output sum to expand into an extra bit, it also signals an overflow when the sum is too large or small to be correctly represented with 3 bits. FIGURE A summary and block diagram of the lab circuit. The details are explained later. Two s Complement Numbers 3-bit numbers 3 2 - -2-3 -4 4-bit numbers 7 6 5 4 3 2 - -2-3 -4-5 -6-7 -8 SUB(H) ADD(L) 3 DATA BITS x 2 x x LEAST SWITCH 3 DATA BITS y 2 y y 3-BIT, TWO S COMPLEMENT /subtracter SIGNIFICANT BITS 3-bit sum 22 is too 3-bit s 3 s s big for a 3-bit Overflow 2 s complement numbers Examples 4-bit sum Y X S 3-bit () (-) y 2 y y x 2 x x s 3 s s (2) (2) (3) (-4) (-) (-4) (3) (3) (-3) (-2) (-) - (-4) - ( ) - (-4) - ( ) - ( ) - Negative numbers Overflow happens when 3 bits will not correctly hold the sum, always have a leading. with 3 bit numbers, 4 bits will always hold the correct sum. To change 3-bit 2 s complement numbers into 4-bit 2 s complement: For positive numbers insert a leading. Thus (3) becomes For negative numbers insert a leading. Thus (-3) becomes J.Knight, Jan 3, 8 ELEC 267 Switching Circuits Lab2-
Carleton University Background Binary Numbers In decimal numbers, the digits are given a weight according to there position, thus: 325 is 3 2 5 or 3 2 2 5 In binary numbers, the bits are given a weight according to there position, thus: is 8 4 2 or 2 3 2 2 2 2 3 = 8 4 In decimal Negative numbers could be done in many ways, but the one most used in computer arithmetic is called two s complement Two s complement numbers are weighted like binary numbers except the first bit is given a negative weight.. is ( 8) 4 2 or ( 2 3 ) 2 2 2 2-3 = - 8 4 In decimal Two s Complement Numbers These are a convenient method of representing negative numbers. They look just like positive binary integers. They are two s compliment only in the way you interpret them. The same hardware can add both positive and negative numbers. Addition is done exactly the same way as for positive binary numbers. A few gates will convert an adder into a subtracter. Negative numbers all start with, i.e. the most significant bit is. There is one more negative number than positive number. (There is -4, but no 4 for 3-bit numbers) Sign Extension (Adding leading Bits to Two s Complement Numbers) Placing leading zeros in front of a positive binary number causes no change. However doing this to a negative two s complement number changes the leading bit from to, making the number positive.. is the same as in a positive binary system 6 = 6 decimal values But is not the same as in a two s complement system.. -2 6 decimal values To change a N bit two s complement number into a N bit one: - If the leading bit is, add another leading - If the leading bit is, add another leading 3 2 - -2-3 -4 FIGURE 2: 3-bit binary numbers 3 2 7 6 5 4 FIGURE 3: Some two s complement numbers 3-bit numbers Negative numbers have a leading. Example: changing a 3-bit negative number (-3 decimal) into a 4, 5, 6 and 7-bit number... = = = = 3-bit 4-bit 5-bit 6-bit 7-bit 4-bit numbers 7 6 5 4 3 2 - -2-3 -4-5 -6-7 -8 Lab2-2 ELEC 267 Switching Circuits J.Knight, Jan 3, 28
. Example: of why adding a leading transforms a 3-bit negative number into a 4-bit one... is ( 4) 2 with another leading one is ( 8) 4 2-3 = - 4 decimal values -3 = - 8 4 Addition Of Binary Numbers, Including Two s Complement Numbers To add two binary numbers, add them bit-by-bit transfering the carries left to the next column. In positive integer binary adds, the off-end carry is part of the number. Thus adding two three-bit numbers may give a four-bit number, as shown in the box on the left of Fig. 4. (36=9) With two s complement numbers the final off-end carry is always ignored so the result of adding two 3-bit numbers is always a 3-bit number. This lab will only do two s complement adds. FIGURE 4 Two s complement binary addition example. Positive integer binary addition (3) (6) (9) The addition is the same for positive or two s complement numbers, except: For positive numbers include the off-end carry as part of the sum. For two s complement addition ignore the off-end carry, and read the result as two s complement. - If the remaining 3 bits of the number starts with a it is a positive two s complement number. - If the remaining 3 bits of the number starts with a it is a negative two s complement number. - Unless the answer overflows. Overflow in Two s Complement Addition FIGURE 5: Overflow: When adding 3-bit numbers, 3-bits may not be enough to hold the sum. For 3-bit two s complement numbers, the sum must be between -4 and 3 or addition will overflow. Sign Extension Will Cure Overflow Here the off-end carry is part of the answer (3) (2) (5) is too large for 3-bit two s complement. We say it overflows. (- 3) Ignore the off-end carry. (3) (- 2) With 2 s complement numbers, ignore the off-end carry. (- 3) (- 2) (- 5) overflows 3-bit two s complement Carry The leading bit tells the sign of the number. To use sign extension, concatenate a new sign (leading) bit of the same value as the previous sign bit, thus: is sign extended to and is sign extended to. () (3) ignore the off-end carry.. One can sign extend as far as desired, thus as an 8 bit 2 s complement number is. J.Knight,Jan 3, 8 ELEC 267 Switching Circuits Lab2-3
Carleton University FIGURE 6 Curing Overflow with sign extension (with sign extension) (3) (2) (5) Ignore the off-end carry. if any (5) If the numbers are sign extended by one bit before adding, the results can never overflow. However the numbers becomes one bit longer, and take more storage. 2 Checking an Addition for Overflow Add the numbers as 3-bit numbers Then do sign extension and add them as 4-bit numbers. If the 3 and 4-bit answers have the same sign, there was no overflow and the 3-bit answer was correct. If they have different signs, there was an overflow, and one must use the 4-bit answer and/or send the user an overflow warning. FIGURE 7 Checking for overflow (3) (2) (5) 3-bit number overflows because the leading is part of the number and cannot be the sign. Sign extension 5 fits into a 4-bit 2 s complement number (- 3) (- 2) (- 5) FIGURE 8 Checking for overflow using the last two bits of the sign extended add. With sign extension 2. Some filter circuits add a hundred or more numbers. If each addition requires a one bit increase, one might start with an 8-bit number and end with a 8-bit number! Lab2-4 ELEC 267 Switching Circuits J.Knight, Jan 3, 28 (with sign extension) Ignore the off-end carry. (- 5) With sign extension Sign extension 5 fits into a 4-bit 2 s complement number Sign extension (3) (2) (- 3) (5) (5) 4-bit two s compliment Ignore. has a 4th bit to give These are the correct sign Ignore. 3-bit sign different. 4-bit sign Signs are different. There is overflow without sign extension With sign extension Sign extension (- 3) (- 3) (- 2) (- 2) (- 5) (- 3) (- 5) (- 5) 3-bit two s compliment 4-bit two s compliment number overflows because Ignore. has a 4th bit to give Ignore. These are the leading bit is not the 3-bit sign the correct sign different correct sign. 4-bit sign Signs are different. There is overflow without sign extension (-3) (-) (- 4) 3-bit number overflows (- 4) Ignore. (-3) (-) (-4) (-4) 4-bit two s compliment has a 4th bit to give the correct sign Ignore. Signs are the same. No overflow. Sign extension not needed Sign extension These are the same No overflow. 4-bit sign
Sign extension is not always the answer. Computers store 6 bit integers, and most adds do not overflow. Computers do not store sums as 7 bits. They can store them using 32 bits, but only if necessary. Often one would like to send out a warning signal that the 6 bit addition overflowed and tell the computer to store this sum with 32 bits. To Tell If a Sum Overflowed 3 Bits (Or N Bits in General) Add the numbers with sign extension. Then compare the leftmost two sum bits: If they are equal all is OK. Remember to ignore If they are not equal send out an overflow warning. off-end carry Examples FIGURE 9 Examples of two s complement addition, with and without sign extension and overflow checking. 3-bit addition 3-bit addition 3-bit sum With sign extension 3-bit sum With sign extension (3) (-3) (-4) (-2) (- ) (- 5) Correct No overflow of 3--bit sum. Wrong Overflow of 3-bit sum. 3-bit sum Correct 4-bit sum 3-bit sum Correct 4-bit sum 3-bit addition 3-bit sum (-2) (-2) (- 4) Correct 3-bit sum With sign extension No Overflow. Correct 4-bit sum 4-bit addition 4-bit sum (-3) (-2) (- 5) Correct 4-bit sum With sign extension No Overflow. Correct 5-bit sum 2. Calculation of the Compliment. To Take The Two s Complement Of A Binary Number. Invert each bit. 2. add 3. ignore any carry. Example: Take the 2 s complement of ( in binary). Take, invert bits add one ( is - in 2 s complement) Find the 3-bit two s complement representation of 3, -2, -, -4. using the method above. (You will be asked to do this in the prelab for 5-bit numbers.) Explain what is special about the 3-bit two s complement of -4? 3 Hint: When you add, try sign extending before you add 3-bit numbers 3 2 - -2-3 -4 Negative numbers always have a leading. 4-bit numbers 7 6 5 4 3 2 - -2-3 -4-5 -6-7 -8 Two s Complement Numbers 3. Hint: When you add, try sign extending before you add. Then check for overflow. J.Knight,Jan 3, 8 ELEC 267 Switching Circuits Lab2-5
Carleton University 2.. The Adder Circuit The Half Adder, an Adder for Two Single-Bit Numbers Until we get into detailed logic, after Step 3.4, will mean plus, not OR. This circuit can add,,, and. It gives a single-bit sum output s i and a single-bit carry output c i The Full-Adder, an Adder for Three Single-Bit Numbers The half-adder is not enough for adding binary numbers. One must be able to add three input bits. The third bit, c i is for a carry input. An Iterative Adder Circuit for Multibit Numbers FIGURE y i x i HALF One can make a multibit adder by combining full adders in an iterative circuit, also called bit-sliced circuits. These are circuits which can be made from identical sections coupled together. FIGURE 2 A 3-bit adder made from three full-adders, an example of an iterative or bit-sliced circuit... c i c i FIGURE y i s i s i x i c i y 2 x 2 y x y x c Not part of sum with 2 s complement numbers c 3 c 2 s c s C = for addition The carry output of one full-adder is sent to the next full-adder. In the above picture, c 3 is ignored in two s complement addition. c is always zero since there is no carry input Adding Multibit Two s Complement Numbers The advantage of two s complement numbers is, that negative numbers are added exactly the same way positive numbers. Thus the positive integer adder circuit in Fig. 2 could be used for adding two s complement integers. However, unlike 3-bit positive integers, adding 3-bit two s complement integers cannot give a 4-bit number. The carry out c 3, is never part of the sum. Remember In two s compliment the off-end carry is never part of the sum! A Two s Complement subtracter To calculate Y - X, one adds Y to the 2 s complement of X. Let X = x n x n-...x x To get the 2 s compliment, inverts each of the bits of X, to get x n x n-...x x and add. In summary, Y - X = Y x n x n-...x x A convenient way to add the, is to use c input. FIGURE 3 A 2 s complement subtracter. x 2 x x For a 3-bit number like X = x 2 x x, inverting each bit gives= x 2 x x y 2 x 2 y x y x c c 3 c 2 c s s Lab2-6 ELEC 267 Switching Circuits J.Knight, Jan 3, 28
A Combination Adder-Subtractor One can make a circuit that both adds and subtracts by: () Having the inverters switch in and out of the circuit by external subtract/add control. (2) Making the initial carry in, c = for addition and c = for subtraction. FIGURE 4 Making an adder into a combination add-subtract unit. Sub(H)/Add(L) x 2 SUB(H) ADD(L) Control Switch The switch inverts x i when and does not invert when. When it is, it also injects a into c. c 3 A Controlled Inverter. To build a combination adder/subtracter, one needs a way to invert or not invert on command FIGURE 5 A controlled inverter circuit.. y 2 z 2 c 2 y s x x z y z c s c Sub(H)/Add(L) X i Z i X i Sub(H)/Add(L) gate Z i = X i IF Sub(H)/Add(L) = X i IF Sub(H)/Add(L) = The signal name Sub(H)/Add(L) means subtract when the signal is high () and add when it is low (). The gate in the box, inverts x i when the control signal Sub(H)/Add(L) is, and passes x i with no change when Sub(H)/Add(L) is. This is a fairly common logic gate. Can you give this gate s name? The Sign Extended Adder The sign extended adder repeats the addition of the most significant bits with a different input carry. Does one need a complete full adder for this last circuit. Does the last full adder need a carry out? FIGURE 6 A sign-extended adder. SUB(H) ADD(L) SWITCH Sub(H)/Add(L) x 2 x x y 2 z 2 y z y z? c 3 c 2 c c s 3 s s J.Knight,Jan 3, 8 ELEC 267 Switching Circuits Lab2-7
Carleton University FIGURE 7 A sign-extended adder with an overflow check to tell if only 3 bits are needed. Sub(H)/Add(L) x 2 x x SUB(H) Check if 3-bits is enough to hold result ADD(L) NOT EQUAL SWITCH? c 3 y 2 z 2 c 2 y z y z c c 3-Bit_ s 3 s s From Fig. 8 (p. 4) one knows that if s 3 = there is no overflow in the 3-bit sum. if s 3 overflowed 3-bits. Thus one can add an overflow check by using a NOT EQUAL gate. What kind of a gate can check for inequality? FIGURE 8 An inequality detection circuit. Ovf s 3 s 3 s 3 gate Ovf Lab2-8 ELEC 267 Switching Circuits J.Knight, Jan 3, 28
Prelab (This must be prepared prior to the scheduled lab session. You must show calculations, since some unscrupulous individuals sometimes sabotage their education by copying raw answers. It will be checked near the start of the lab. It will also be an appendix for your final report.) 3. Convert the binary number to decimal in a system having only positive numbers. Do the same for a system of 2 s complement number? 3. Make a table of 5-bit two s-complement numbers showing them opposite their decimal values. You may put in a row of dots... to save writing, but show the top 3 numbers, the bottom 3 numbers, and at least 2,,, - and -2. 3.2 Show how to calculate 4-bit two s complement of numbers by inverting and adding. Use 7, - and -8 as examples. Decide if there is a 4-bit two s complement of -4. 3.3 Do the following (a through d) arithmetic problems as a 3-bit binary sign-extended adder/subtracter would do them. Show how the carries propagate and how the overflow for 3-bits is calculated as is illustrated in Fig. 9 for the 3 bit subtraction of X - Y = (-3) - (2). (a) (2) (2), (b) (-) (-), (c) (-2) (-), (d) (-3) - (-3), (e) (-3) - (3). FIGURE 9 Doing a 2 s complement sign-extended subtract. - Sign Extension (- 3) (2) 3.4 Complete the truth table for a generic full adder. The three inputs are x i, y i, and c i. The two outputs are sum and carry, that is s i and c i Subtract here means invert all bits here (-5) Then the subtraction can be done as addition Provided an extra is added to the least significant bit. Partial Truth Table for a Generic Full Adder Carry Initial carry in, as part of 2 s complement calculation Not Equal Means Overflow y i x i c i c i s i Expression for c i Expression for s i y i x i c i y i x i c i y i x i c i y i x i c i - - - - - - - - - - - - - - - - - - -- FIGURE 2 c i y i s i x i c i y i x i c i y i x i c i 3.5 Obtain the equations for the generic full adder from the truth table. 4 4. One can learn many things, that may be useful here, from the lecture notes Basic Logic Gates and Formulas athttp://www.doe.carleton.ca/%7ejknight/97.267/267_7w/indexnotes7.html (there may be a later release) J.Knight,Jan 3, 8 ELEC 267 Switching Circuits Lab2-9
Carleton University 3.6 Simplify the equations. Hint : (This may or may not help you) (a b)c ab = (ab ab)c ab Expand xor = abc abc abc abc ab xcx = x (Simplification) = ac bc ab xb xb = x, use twice 3.7 Take the simplified equations you just derived for the full-adder subcircuit and draw a schematic from them. 3.8 What logic gate can function as a controlled inverter? What gate can test two bits for equality? 3.9 Design a generic invert control unit that inverts the x i input when subtract is selected. 3. Design the circuit that detects overflow. 3. Draw a block diagram for the complete 3-bit adder/subtracter. Use blocks, or gates if the block is only one gate, for the standard subcircuits you designed in subsections 3.6, 3.9 and 3.. The figure below gives an idea of what is wanted,. However several necessary things are left out. FIGURE 2 Partial block diagram of the adder/subtracter. SubIf_ x 2 x x input y 2 y y 3-BIT OVERFLOW DETECT c 3 2 c 2 c c s s LEAST SIGNIFC BIT 3.2 You should have at least three types of blocks: full-adders, invert-control, and overflow detect. Draw a schematic of each type of block, with the gates drawn the way they will appear in the lab. This lab will be done with a computer simulation, so you will have as many gates of each type as you need. 3.3 Can one of the additions be done by a simpler circuit than a full adder? If so, use it. 2.2 In the Laboratory The lower-level schematic This circuit will be implemented by drawing circuits on the computer screen the Top-Level Schematic, the Adder Symbol and the Full Adder Symbol are already drawn. You will draw the lower level schematic for the Adder somewhat like the schematic on the right in Fig. 22. You will also draw the Full Adder. The simulation After the schematic is correctly entered, you will need to simulate the circuit. The simulations will come out as wave forms which are hard to read without detailed study. In labaratory reports, you should anotate a representative sample of the 28 cases. See Fig. 23 Lab2- ELEC 267 Switching Circuits J.Knight, Jan 3, 28
FIGURE 22 The hierarchy of schematics and symbols used in the lab.. Top-Level Schematic The wires(nets) C,X,Y,X... are seen by the simulator. C Use C for SUB(H)/ADD(L) X X C X X X S X S S2 X S3 X3 Y X Y Y2 Schematic of circuit using the adder and nothing else Net (wire) names on this schematic are the same as on the symbol. They don t have to be. X X Y Y Y2 C S S S2 S3 Adder symbol used in top-level schematic Leads in the schematic are connected to leads of the same name on the symbol, as shown for C and S. C X Y X Y Y2 ADD C S S S2 S3 Lower-level schematic of what is inside the the adder symbol. (Note this circuit is not a real adder) Value of X in decimal X -4-2 -3-2 3-4-3-2 - 2 3-4 -3-2 - 2 3-4 -3-2 - FIGURE 23 How to annotate simulation waveforms so the TA can understand them. X Value of X in decimal Y Y Value of Y in decimal Y2 S S - 2 3 Annotate you waveforms at various interesting spots. Here some values that give a for 2 s complement and 8 for positive numbers are noted. Also some that give an overflow are highlighted. The notation show what the numbers are in decimal. That way someone reading your report can check your results more easily. Write the notes on by hand. It is hard to print them, and they stand out more. Sample annotations here are in blue. S2 Value of S in decimal -3-2 - 234 5-2-3456- -2 S3 For pos integers (7) = 8 for 2 s comp - = -=-, 3=4, There is no 4 in 3-bit 2 s comp. hence overflow J.Knight,Jan 3, 8 ELEC 267 Switching Circuits Lab2-
Carleton University Lab2-2 ELEC 267 Switching Circuits J.Knight, Jan 3, 28