ECMF02-2HSMX6. ESD protected common mode filter for USB3.0 interface. Description. Applications. Features. Benefits

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ESD protected common mode filter for USB3.0 interface Datasheet - production data Save components count Make the application robust against ESD strikes from external environment Description µqfn-6l 1.7 x 1.5 mm Figure 1. Pin out, top view The is a highly integrated common mode filter designed to suppress EMI/RFI common mode noise on high speed differential serial buses like the USB3.0 transceiver. Applications D+ connector D- connector 1 2 6 5 D+ IC D- IC Consumer and computer electronics featuring USB3.0 such as: Personal computer 3 4 To be left floating Notebook Tablet Set-top boxes Features PC graphic cards Telecom application High common mode attenuation: -10 db @ 300 MHz -20 db @ 2.4 and 5 GHz -15 db from 500 MHz to 6 GHz Compliant with USB3.0 eye diagram Small and thin package 1.5 x 1.7 x 0.5 mm RoHS compliant. High reduction of parasitic elements through integration. ESD protection compliant with IEC 61000-4-2 level 4 standards (8 kv contact) Benefits Suppress the common mode noise but keep signal integrity Low PCB space consumption. December 2017 DocID025079 Rev 3 1/17 This is information on a product in full production. www.st.com

Functional description 1 Functional description The is an ESD protected common mode filter especially designed for USB3.0 Tx/Rx differential pair, for host and device. The USB3.0 is actually made of 3 differential pairs. The first differential pair supports the high speed USB mode (also called USB2.0 mode). The 2 other differential pairs are used to support the super speed USB mode in full duplex. Bit rate on super speed USB can reach 5 Gbps. The is able to filter the common mode noise from 300 MHz to 6 GHz, helping to make the application compliant with the electromagnetic interference emission standard such as CISPR22 or FCC part 15, or EN55022 and avoiding antenna desense on mobile phones, WiFi/Bluetooth, GPS,/GNSS frequencies. At the same time, the keeps the high speed signal integrity and provides an efficient ESD protection. More application information available in following AN: Application Note AN4356: "Antenna desense on handheld equipment" Application Note AN4511: "Common Mode filters" Application Note AN4540: "MHL link filtering and protection" Figure 2. Functional diagram D+ connector 1 6 D+ IC D- connector 2 5 D- IC 3 4 To be left floating A typical application diagram is shown in Figure 3. ST offers a global approach to USB3.0 interface by providing a comprehensive range of dedicated products. 2/17 DocID025079 Rev 3

D+ D+ D+ D- D- D+ D- D- Functional description Host Figure 3. Typical application diagram USB 3.0 cable Hub/device USB 2.0 High Speed Driver V BUS D+ D- V BUS V BUS D- D- D- D- D+ D+ D+ D+ I D I D V BUS D+ D- USB 2.0 High Speed Driver ECMF02-4CMX8 ECMF02-4CMX8 USB 3.0 Super Speed Driver + + D- 6 D- 1 D+ 5 D+ 2 I4 D 3 D- 6 D- 1 D+ 5 D+ 2 I4 D 3 1 2 3 1 2 3 6 5 4 6 5 4 I D I D SSTX+ + SSRX+ SSTX+ SSTX- SSRX+ SSRX- SSTX- USB 3.0 SSRX- Super Speed Driver + CONNECTOR CONNECTOR DocID025079 Rev 3 3/17 17

Electrical characteristics 2 Electrical characteristics Table 1. Absolute maximum ratings (limiting values) Symbol Parameter Test conditions Value. Unit ESD discharge (pins 1 and 2) Contact discharge ±8 kv V PP IEC 61000-4-2 level 4 Air discharge ±15 kv I DC Maximum DC current 100 ma T OP Operating temperature range -55 to +125 C T J Maximum junction temperature 125 C T stg Storage temperature range -55 to +150 C Figure 4. Electrical characteristics (definitions) Symbol Parameter V BR = Breakdown voltage I RM = Leakage current @ VRM V RM = Stand-off voltage V CL = Clamping voltage at I PP I PP = Peak pulse current I F = Forward current V F = Forward voltage V CL V BR V RM I F I I R I V F RM V I PP Table 2. Electrical characteristics (T amb = 25 C) Symbol Parameter Test conditions Min. Typ. Max. Unit V BR Breakdown voltage I R = 1 ma 6 V I RM Reverse leakage V RM = 3 V 100 na R DC DC serial resistance 7 9 Ω 4/17 DocID025079 Rev 3

Electrical characteristics Figure 5 shows that USB3.0 devices and cables can interfere with radio frequency devices operating between 700 MHz and 5 GHz. Figure 5. USB3.0 frequency radiation measured with current loop db -70-75 Skew -80-85 -90-95 Frequency (GHz) -100 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 6 0 SDD21 (db) Figure 6. Differential attenuation versus frequency F 0 @-3 db = 3.2 GHz -1-2 -3-4 -5 F (Hz) 10M 30M 100M 300M 1G 3G DocID025079 Rev 3 5/17 17

Electrical characteristics Figure 7. Common mode attenuation versus frequency 0 SCC21 (db) -5 USB3.0 S21CC template -10-15 -20-25 -30-35 -40 10M 30M 100M 300M 1G 3G F (Hz) Note: STMicroelectronics has defined the USB3.0 SCC21 template to prevent antenna desense between 700 MHz and 5 GHz. Figure 8. Return loss versus frequency (Z 0 COM = 50 Ω - SDD11) 0 SDD11 (db) -5-10 -15-20 -25-30 -35 F (Hz) 40-10M 30M 100M 300M 1G 3G 6/17 DocID025079 Rev 3

Electrical characteristics Figure 9. Return loss versus frequency (Z 0 COM = 50 Ω - SDD22) 0 SDD22 (db) -5-10 -15-20 -25-30 -35 F (Hz) -40 10M 30M 100M 300M 1G 3G Figure 10. Differential (Z DD21 ) and common mode (Z CC21 ) impedance versus frequency ZDD21 ZCC21 (Ω) 1E4 1E3 1E2 1E1 1E7 1E8 1E9 6E9 F (Hz) DocID025079 Rev 3 7/17 17

Electrical characteristics Figure 11. Typical ESD response to IEC 61000-4-2 +8kV contact 10 V/div 1 56.4 V 1 23 4 V PP: ESD peak voltage V CL :clamping voltage @ 30 ns V CL :clamping voltage @ 60 ns V :clamping voltage @ 100 ns CL 2 26.8 V 3 19.0 V 4 12.5 V 20 ns/div Figure 12. Typical ESD response to IEC 61000-4-2-8kV contact 10 V/div 2-16.0 V 3-9.9 V 4-6.4 V 1 23 4 V PP: ESD peak voltage V CL :clamping voltage @ 30 ns V CL :clamping voltage @ 60 ns V :clamping voltage @ 100 ns CL 1-60.2 V 20 ns/div 8/17 DocID025079 Rev 3

Electrical characteristics Figure 13. USB2.0 (480 Mbps) eye diagram without device Figure 14. USB2.0 (480 Mbps) eye diagram with device Figure 15. USB3.0 (5 Gbps) eye diagram without device Figure 16. USB3.0 (5 Gbps) eye diagram with device Figure 17. USB3.1 (10 Gbps) eye diagram without device Figure 18. USB3.1 (10 Gbps) eye diagram with device DocID025079 Rev 3 9/17 17

Electrical characteristics Figure 19. MHL (4.5 Gbps) eye diagram without device Figure 20. MHL (4.5 Gbps) eye diagram with device Figure 21. MHL (6 Gbps) eye diagram without device Figure 22. MHL (6 Gbps) eye diagram with device Figure 23. Display Port HBR2 (5.4 Gbps) eye diagram without device Figure 24. Display Port HBR2 (5.4 Gbps) eye diagram with device 10/17 DocID025079 Rev 3

Package information 3 Package information Epoxy meets UL94, V0 Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 25. µqfn-6l dimension definitions Top view D Index area E Side view A A1 Bottom view e b PIN # 1 ID 1 3 L1 L2 6 4 Ref. Table 3. µqfn-6l dimension values Millimeters Dimensions Inches Min. Typ. Max. Min. Typ. Max. A 0.45 0.50 0.55 0.018 0.020 0.022 A1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 D 1.55 1.60 1.65 0.061 0.063 0.065 E 1.30 1.35 1.40 0.051 0.053 0.055 e 0.45 0.50 0.55 0.018 0.020 0.022 L1 0.35 0.45 0.55 0.014 0.018 0.022 L2 0.65 0.75 0.85 0.026 0.030 0.034 DocID025079 Rev 3 11/17 17

Package information Figure 26. Footprint, dimensions in mm (inches) Figure 27. Marking 0.25 (0.0098) 0.50 (0.0197) 0.65 (0.0256) 0.30 (0.0118) Dot, xx = marking z = manufacturing location yww = datecode (y = year ww = week) x y x w z w 0.95 (0.0374) Figure 28. Tape and reel specifications Dot identifying Pin A1 location 0.22 2.0 4.0 Ø 1.55 1.85 3.5 1.75 8.0 xxx yww xxx yww xxx yww 0.75 1.63 4.0 All dimensions are typical values in mm User direction of unreeling 12/17 DocID025079 Rev 3

Recommendation on PCB assembly 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 29. Stencil opening dimensions L T W b) General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ---- 1.5 T L W Aspect Area = --------------------------- 2TL + W 0.66 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for leads: Opening to footprint ratio is 90%. 4.2 Solder paste 1. Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004. 2. No clean solder paste recommended. 3. Offers a high tack force to resist component displacement during PCB movement. 4. Use solder paste with fine particles: powder particle size 20-45 µm. DocID025079 Rev 3 13/17 17

Recommendation on PCB assembly Figure 30. Recommended stencil window position 0.25 (0.0098) 0.50 (0.0197) 0.95 (0.0374) 0.34 (0.0134) 0.30 (0.0118) 0.90 (0.0354) 0.62 (0.0244) 0.65 (0.0256) Stencil window 0.24 (0.0095) 0.50 (0.0197) mm (inches) Footprint 4.3 Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 4.4 PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. 14/17 DocID025079 Rev 3

Recommendation on PCB assembly 4.5 Reflow profile Figure 31. ST ECOPACK recommended soldering reflow profile for PCB mounting 250 Temperature ( C) 2-3 C/s 240-245 C -2 C/s 200 60 sec (90 max) -3 C/s 150-6 C/s 100 50 0.9 C/s Time (s) 0 30 60 90 120 150 180 210 240 270 300 Note: Minimize air convection currents in the reflow oven to avoid component movement. 4.6 PCB layout recommendation Figure 32. PCB footprint recommendation Zdiff according to the application Via to plane DocID025079 Rev 3 15/17 17

Ordering information 5 Ordering information Figure 33. Ordering information scheme ECMF 02-2 HS MX6 Function ESD common mode filter Number of lines 02 = 2 lines Number of ESD protected lines 2 = 2 ESD protected lines Version HS = High speed lines Package Mx6 = µqfn-6l Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode KR µqfn-6l 3.4 mg 3000 Tape and reel 6 Revision history Table 5. Document revision history Date Revision Changes 13-Nov-2013 1 Initial release. 25-Aug-2014 2 13-Dec-2017 3 Updated Table 1. Inserted Figure 10: Differential (ZDD21) and common mode (ZCC21) impedance versus frequency. 16/17 DocID025079 Rev 3

IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 2017 STMicroelectronics All rights reserved DocID025079 Rev 3 17/17 17