8051 Architecture 1
Microcontrollers can be considered as self-contained systems with a processor, memory and I/O ports. In most cases, all that is missing is the software to define the operation of the embedded system. Usually available in several forms: Devices for prototyping Built-in or piggy-back EPROM for storing the software. One Time Programmable (OTP) devices. No window on the package. Therefore, the internal EPROM cannot be erased after being programmed. High Volume Production devices. Use ROM internally to hold the software. Cheaper in large volume. 2
The Architectural Needs of a Microcontroller Lets consider what architectural features would be needed in a microcontroller. What are the expected applications? Sensing the environment. Input. Producing a response. Output. The response may be delayed. Timer/Counter. Prioritized response. Interrupts. Software to control the process. Non-volatile Memory. Temporary data. RAM. 3
Three criteria in Choosing a Microcontroller 1. meeting the computing needs of the task efficiently and cost effectively speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption easy to upgrade cost per unit 2. availability of software development tools assemblers, debuggers, C compilers, emulator, simulator, technical support 3. wide availability and reliable sources of the microcontrollers. 4
The MCS-51 Family of Microcontrollers Originally introduced by Intel in 1981. Currently, the most widely used microcontroller. 8-bit processor. 2 distinct separately addressable memory areas. Maximum of 64K on-chip ROM. Usually 0 to 4K. Maximum of 64K external data memory. Maximum of 64K external code memory. Basic version (8051) contains: 4K Bytes of on-chip ROM instruction memory. 128 Bytes of on-chip RAM for temporary data storage and the stack. 2 Timers, One Serial Port, and Four 8-bit Parallel I/O ports. Speeds starting from12 MHz. 5
Features of the 8051 Microcontroller Feature Quantity ROM 4K Bytes RAM 128 Bytes Timer 2 I/O Ports 4 Serial Port 1 Interrupt Sources 6 The 8051 is the original member of the Intel MCS-51 family of Microcontrollers. There are several varieties that differ slightly in the available features. 6
Feature 8051 8052 8751 8752 8031 8032 EPROM On-Chip ROM 4K 8K 4k 8k 0K 0K RAM (Bytes) 128 256 128 256 128 256 Timers 2 3 2 3 2 3 I/O Ports 4 4 4 4 2 2 Serial Port 1 1 1 1 1 1 Interrupt Sources 6 8 6 8 6 8 The 8031 requires external instruction memory. It can be as large as 64K Bytes. You lose 2 ports for interfacing to the external memory. You can replace these by interfacing the chip to an I/O port controller like the 8255. 7
Manufacturers of MCS-51 Clones There is a large number of companies that manufacture microcontrollers in the 8051 family. Atmel Corporation. Flash instead of EPROM. Low Voltage. Minimal version with less memory and fewer I/O ports in a smaller package. CMOS implementation. Speeds that range from 12 to 20 MHz. 8
Manufacturers of MCS-51 Clones Dallas Semiconductor Uses NV-RAM. Programmable in-system. As large as 32K of instruction memory. Some versions have an on-chip real-time clock. Philips Corporation. Large selection of 8051 based microcontrollers. Include features like A/D and D/A on chip. Xilinx and Altera 8051 FPGA cores. 9
Programmer s View Memory Organization Register Set Instruction Set Hardware Designer s View Pin-out Timing characteristics Current / Voltage requirements 10
The 8051 Internals External interrupts Interrupt Control On-chip ROM for program code On-chip RAM Timer/Counter Timer 1 Timer 0 Counter Inputs CPU OSC Bus Control 4 I/O Ports Serial Port P0 P1 P2 P3 Address/Data TxD RxD 11
The 8051 has separate address spaces for program storage and data storage. Depending on the type of instruction, the same address can refer to two logically and physically different memory locations. FFFF FFFF 1000 0FFF 0000 External Internal Program Memory 7F 00 Special Function Registers Internal Data Memory FF 80 0000 External Data Memory 12
After reset, the MCS-51 starts fetching instructions from 0000H. This can be either on-chip or external depending on the value of the EA input pin. If EA is low, then the program memory is external. If EA is high, then addresses from 0000 to 0FFF will refer to on-chip memory and addresses 1000 up to FFFF refer to external memory. Note that the 8031 must have its EA connected low as all of its memory is external. 13
Port 0 acts as a multiplexed address/data bus. Sending the low byte of the program counter (PCL) as an address. Port 2 sends the program counter high byte (PCH) directly to the external memory. The signal ALE operates as in the 8085 to allow an external latch to store the PCL byte while the multiplexed bus is made ready to receive the code byte from the external memory. Port 0 then switches function and becomes the data bus receiving the byte from memory. 14
The 8051 has 256 bytes of RAM on-chip. The lower 128 bytes are intended for internal data storage. The upper 128 bytes are the Special Function Registers (SFR). The lower 128 bytes are not to be used as standard RAM. They house the 8051 s registers, its default stack area, and other features. Special Function Registers Internal Data Storage FFH 80H 7FH 00H 15
Data Storage Contd. The lowest 32 bytes of the on-chip RAM form 4 banks of 8 registers each. Only one of these banks can be active at any time. Bank is chosen by setting 2 bits in PSW Default bank (at power up) is bank 0 (locations 00 07). The 8 registers in any active bank are referred to as R0 through R7 Given that each register has a specific address, it can be accessed directly using that address even if its bank is not the active one. 1F H 1E H 1D H 1C H 1B H 1A H 19 H 18 H 17 H 16 H 15 H 14 H 13 H 12 H 11 H 10 H 0F H 0E H 0D H 0C H 0B H 0A H 09 H 08 H 07 H 06 H 05 H 04 H 03 H 02 H 01 H 00 H R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 R7 R6 R5 R4 R3 R2 R1 R0 Bank 03 Bank 02 Bank 01 Bank 00 16
2F 7F 7E 7D 7C 7B 7A 79 78 The next 16 bytes locations 20H to 2FH form a block that can be addressed as either bytes or individual bits. The bytes have addresses 20H to 2FH. The bits have addresses 00H to 7FH. Specific instructions are used for accessing the bits. 2E 77 76 75 74 73 72 71 70 2D 6F 6E 6D 6C 6B 6A 69 68 2C 67 66 65 64 63 62 61 60 2B 5F 5E 5D 5C 5B 5A 59 58 2A 57 56 55 54 53 52 51 50 29 4F 4E 4D 4C 4B 4A 49 48 28 47 46 45 44 43 42 41 40 27 3F 3E 3D 3C 3B 3A 39 38 26 37 36 35 34 33 32 31 30 25 2F 2E 2D 2C 2B 2A 29 28 24 27 26 25 24 23 22 21 20 23 1F 1E 1D 1C 1B 1A 19 18 22 17 16 15 14 13 12 11 10 21 0F 0E 0D 0C 0B 0A 09 08 20 07 06 05 04 03 02 01 00 Locations 30H to 7FH are general purpose RAM. 17
Data Storage the Lower 128 Bytes 30 7F General Purpose Ram 2F 7F 7E 7D 7C 7B 7A 79 78 2E 77 76 75 74 73 72 71 70 2D 6F 6E 6D 6C 6B 6A 69 68 2C 67 66 65 64 63 62 61 60 2B 5F 5E 5D 5C 5B 5A 59 58 2A 57 56 55 54 53 52 51 50 29 4F 4E 4D 4C 4B 4A 49 48 28 47 46 45 44 43 42 41 40 27 3F 3E 3D 3C 3B 3A 39 38 26 37 36 35 34 33 32 31 30 Bit addressable memory locations 25 2F 2E 2D 2C 2B 2A 29 28 24 27 26 25 24 23 22 21 20 23 1F 1E 1D 1C 1B 1A 19 18 22 17 16 15 14 13 12 11 10 21 0F 0E 0D 0C 0B 0A 09 08 20 07 06 05 04 03 02 01 00 18 1F Register Bank 3 10 17 Register Bank 2 08 0F Register Bank 1 00 07 Register Bank 0 18
The SFR Special Function Registers The upper 128 bytes of the on-chip RAM are used to house special function registers. In reality, only about 25 of these bytes are actually used. The others are reserved for future versions of the 8051. These are registers associated with important functions in the operation of the MCS-51. Some of these registers are bit-addressable as well as byteaddressable. The address of bit 0 of the register will be the same as the address of the register. 19
F8 FF F0 B F7 E8 EF E0 ACC E7 D8 DF D0 PSW D7 C8 (T2CON) (RCAP2L) (RCAP2H) (TL2) (TH2) CF C0 C7 B8 IP BF B0 P3 B7 A8 IE AF A0 P2 A7 98 SCON SBUF 9F 90 P1 97 88 TCON TMOD TL0 TL1 TH0 TH1 8F 80 P0 SP DPL DPH PCON 87 Bit/Byte addressable registers Byte only addressable registers 20
ACC and B registers 8 bit each DPTR : [DPH:DPL] 16 bit combined PC : Program Counter 16 bits Stack pointer SP 8 bit PSW : Program Status Word Port Latches Serial Data Buffer Timer Registers Control Registers 21
Commonly used for move and arithmetic instructions. Can be referred to in several ways: Implicitly in opcodes. Referred to as ACC (or A) for instructions that allow specifying a register. By its SFR address 0E0H. Operates in a similar manner to the 8085 accumulator. Bit addressable. ACC.2 means bit 2 of the ACC register. 22
Commonly used as a temporary register, much like a 9 th R register. Used by two opcodes mul AB, div AB B register holds the second operand and will hold part of the result Upper 8 bits of the multiplication result Remainder in case of division. Can also be accessed through its SFR address of 0F0H. Bit addressable. 23
2 8-bit registers that can be combined into a 16-bit DPTR Data Pointer. Used by commands that access external memory Also used for storing 16bit values mov DPTR, #data16 ; setup DPTR with 16bit ext. address movx A, @DPTR ; copy mem[dptr] to A Can be accessed as 2 separate 8-bit registers if needed. DPTR is useful for string operations and look up table (LUT) operations. 24
SP is the stack pointer. SP points to the last used location of the stack. Push operation will first increment SP and then copy data. Pop operation will first copy data and then decrement SP. In 8051, stack grows upwards (from low memory to high memory) and can be in the internal RAM only. On power-up, SP points to 07H. Register banks 2,3,4 (08H to 1FH) form the default stack area. Stack can be relocated by setting SP to the upper memory area in 30H to 7FH. mov SP, #32H 25
Program Status Word is a bit addressable 8-bit register that has all the flags. (MSB) (LSB) CY AC F0 RS1 RS2 OV - P Symbol Position Function CY PSW.7 Carry Flag AC PSW.6 Auxiliary Carry Flag. For BCD Operations F0 PSW.5 Flag 0. Available to the user for general purposes. RS1 PSW.4 Register bank select bits. Set by software to RS2 PSW.3 determine which register bank is being used. OV PSW.2 Overflow Flag - PSW.1 Not used P PSW.0 Parity Flag. Even Parity. 26
The P0, P1, P2, and P3 Registers Port Latches. Specify the value to be output on the specific output port or the value read from the specific input port. Bit addressable. First bit has the same address as the register. Example: P1 has address 90H in the SFR, so P1.7 or 97H refer to the same bit. 27
Serial Port Data Buffer. 2 registers at the same location One is read-only used for reading serial input data. Serial Data Receive Buffer. The other is write-only used for storing serial output data. Serial Data Transmit Buffer. 28
The high and low bytes of the 16-bit counting register for timer/counter T0. There is also a TH1 / TL1 pair for the T1 timer. In the 8052, one more pair exists (TH2) / (TL2) for the T2 timer. (RCAP2H) and (RCAP2L) exist only in the 8052 and they are copies of the TH2 and TL2 registers. 29
IP Interrupt Priority. IE Interrupt Enable. TMOD Timer Mode. TCON Timer Control. T2CON Timer 2 Control (8052) SCON Serial Port Control. PCON Power Control (80C51). 30
31
Pin Description of the 8051 PDIP/Cerdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (T0)P3.4 (T1)P3.5 XTAL2 XTAL1 GND (INT0)P3.2 (INT1)P3.3 (RD)P3.7 (WR)P3.6 Vcc P0.0(AD0 ) P0.1(AD1) P0.2(AD2 ) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14 ) P2.5(A13 ) P2.4(A12 ) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8) 8051 (8031) 32
Pins of 8051(1/4) Vcc(pin 40): Vcc provides supply voltage to the chip. The voltage source is +5V. GND(pin 20):ground XTAL1 and XTAL2(pins 19,18): These 2 pins provide external clock. Way 1:using a quartz crystal oscillator Way 2:using a TTL oscillator 33
Pins of 8051(2/4) RST(pin 9):reset It is an input pin and is active high(normally low). The high pulse must be high at least 2 machine cycles. It is a power-on reset. Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost. Reset values of some 8051 registers Way 1:Power-on reset circuit Way 2:Power-on reset with debounce 34
Pins of 8051(3/4) /EA(pin 31):external access There is no on-chip ROM in 8031 and 8032. The /EA pin is connected to GND to indicate the code is stored externally. /PSEN & ALE are used for external ROM. For 8051, /EA pin is connected to Vcc. / means active low. /PSEN(pin 29):Program Store ENable This is an output pin and is connected to the /OE pin of the ROM. 35
Pins of 8051(4/4) ALE(pin 30):Address Latch Enable It is an output pin and is active high. 8051 port 0 provides both address and data. The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. I/O port pins The four ports P0, P1, P2, and P3. Each port uses 8 pins. All I/O pins are bi-directional. 36
XTAL Connection to 8051 Using a quartz crystal oscillator We can observe the frequency on the XTAL2 pin. C2 30pF XTAL2 C1 30pF XTAL1 GND 37
XTAL Connection to an External Clock Source Using a TTL oscillator XTAL2 is unconnected. N C EXTERNAL OSCILLATOR SIGNAL XTAL2 XTAL1 GND 38
Example : Find the machine cycle for (a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz. Solution: (a) 11.0592 MHz / 12 = 921.6 khz; machine cycle = 1 / 921.6 khz = 1.085 s (b) 16 MHz / 12 = 1.333 MHz; machine cycle = 1 / 1.333 MHz = 0.75 s 39
RESET Value of Some 8051 Registers: Register PC ACC B PSW SP DPTR Reset Value 0000 0000 0000 0000 0007 0000 RAM are all zero. 40
Power-On RESET Circuit Vcc + 10 uf 8.2 K 30 pf 30 pf 11.0592 MHz 31 19 18 9 EA/VPP X1 X2 RST 41
Power-On RESET with Debounce Vcc 10 uf 30 pf 31 EA/VPP X1 9 X2 RST 8.2 K 42
Pins of I/O Port The 8051 has four I/O ports Port 0 (pins 32-39):P0(P0.0~P0.7) Port 1(pins 1-8) :P1(P1.0~P1.7) Port 2(pins 21-28):P2(P2.0~P2.7) Port 3(pins 10-17):P3(P3.0~P3.7) Each port has 8 pins. Named P0.X (X=0,1,...,7), P1.X, P2.X, P3.X Ex:P0.0 is the bit 0(LSB)of P0 Ex:P0.7 is the bit 7(MSB)of P0 These 8 bits form a byte. Each port can be used as input or output (bi-direction). 43
Registers A B R0 R1 DPTR DPH DPL R2 R3 R4 R5 R6 R7 PC PC Some 8051 16-bit Register Some 8-bitt Registers of the 8051 44
Some Simple Instructions MOV dest,source ; dest = source MOV A,#72H ;A=72H MOV A, # r ;A= r OR 72H MOV R4,#62H ;R4=62H MOV B,0F9H ;B=the content of F9 th byte of RAM Just COPY MOV MOV MOV DPTR,#7634H DPL,#34H DPH,#76H MOV P1,A ;mov A to port 1 Note 1: MOV A,#72H MOV A,72H After instruction MOV A,72H the content of 72 th byte of RAM will replace in Accumulator. 8086 8051 MOV AL,72H MOV A,#72H MOV AL, r MOV A,# r MOV BX,72H MOV AL,[BX] MOV A,72H Note 2: MOV A,R3 MOV A,3 45
ADD A, Source ;A=A+SOURCE ADD A,#6 ;A=A+6 ADD A,R6 ;A=A+R6 ADD A,6 ;A=A+[6] or A=A+R6 ADD A,0F3H ;A=A+[0F3H] 46
SETB bit ; bit=1 CLR bit ; bit=0 SETB C ; CY=1 SETB P0.0 ;bit 0 from port 0 =1 SETB P3.7 ;bit 7 from port 3 =1 SETB ACC.2 ;bit 2 from ACCUMULATOR =1 Note: CLR instruction is as same as SETB i.e: CLR C ;CY=0 But following instruction is only for CLR: CLR A ;A=0 47
SUBB A,source ;A=A-source-CY SETBC SUBB A,R5 ;CY=1 ;A=A-R5-1 ADDC A,source ;A=A+source+CY SETBC ;CY=1 ADDC A,R5 ;A=A+R5+1 48
DEC byte ;byte=byte-1 INC byte ;byte=byte+1 INC R7 DEC A DEC 40H ; [40]=[40]-1 CPL A ;1 s complement Example: MOV A,#55H ;A=01010101 B L01: CPL A MOV P1,A ACALL DELAY SJMP L01 NOP & RET & RETI All are like 8086 instructions. 49
ANL - ORL - XRL EXAMPLE: MOV ANL R5,#89H R5,#08H RR RL RRC RLC A EXAMPLE: RR A 50
Structure of Assembly language and Running an 8051 program ORG MOV MOV MOV ADD ADD HERE: SJMP HERE END 0H R5,#25H R7,#34H A,#0 A,R5 A,#12H Myfile.lst EDITOR PROGRAM ASSEMBLER PROGRAM Myfile.obj LINKER PROGRAM OH PROGRAM Myfile.asm Myfile.abs Other obj file 51 Myfile.hex
Memory mapping in 8051 ROM memory map in 8051 family 4k 8k 32k 0000H 0000H 0000H 0FFFH 8751 AT89C51 1FFFH 8752 AT89C52 7FFFH DS5000-32 from Atmel Corporation from Dallas Semiconductor 52
RAM memory space allocation in the 8051 7FH Scratch pad RAM 30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Register Bank 3 Register Bank 2 (Stack) Register Bank 1 Register Bank 0 53
8051 Flag bits and the PSW register PSW Register CY AC F0 RS1 RS0 OV -- P CY PSW.7 Carry flag AC PSW.6 Auxiliary carry flag -- PSW.5 Available to the user for general purpose RS1 PSW.4 Register Bank selector bit 1 RS0 PSW.3 Register Bank selector bit 0 OV PSW.2 Overflow flag -- PSW.1 User define bit P PSW.0 Parity flag Set/Reset odd/even parity RS1 RS0 Register Bank Address 0 0 0 00H-07H 0 1 1 08H-0FH 1 0 2 10H-17H 1 1 3 18H-1FH 54
Instructions that Affect Flag Bits: Note: X can be 0 or 1 55
I/O Port Programming Port 1(pins 1-8) Port 1 is denoted by P1. P1.0 ~ P1.7 We use P1 as examples to show the operations on ports. P1 as an output port (i.e., write CPU data to the external pin) P1 as an input port (i.e., read pin data into CPU bus) 56
A Pin of Port 1 Read latch TB2 Vcc Load(L1) Internal CPU bus D P1.X Q P1.X pin Write to latch Clk Q M1 TB1 Read pin 8051 IC 57
Hardware Structure of I/O Pin Each pin of I/O ports Internal CPU bus:communicate with CPU D latch store the value of this pin D latch is controlled by Write to latch Write to latch=1:write data into the D latch 2 Tri-state buffer: TB1: controlled by Read pin Read pin=1:really read the data present at the pin TB2: controlled by Read latch Read latch=1:read value from internal latch A transistor M1 gate Gate=0: open Gate=1: close 58
Tri-state Buffer Output Input Tri-state control (active high) High impedance (open-circuit) L L H H Low H H 59
Writing 1 to Output Pin P1.X Read latch 1. write a 1 to the pin Internal CPU bus Write to latch TB2 D Q P1.X Clk Q 1 Vcc Load(L1) 2. output pin is Vcc P1.X pin 0 M1 output 1 Read pin TB1 8051 IC 60
Writing 0 to Output Pin P1.X Read latch 1. write a 0 to the pin Internal CPU bus Write to latch TB2 D Q P1.X Clk Q 0 Vcc Load(L1) 2. output pin is ground P1.X pin 1 M1 output 0 Read pin TB1 8051 IC 61
Port 1 as Output(Write to a Port) Send data to Port 1: MOV A,#55H BACK: MOV P1,A ACALL DELAY CPL A SJMP BACK Let P1 toggle. You can write to P1 directly. 62
Reading Input v.s. Port Latch When reading ports, there are two possibilities: Read the status of the input pin. (from external pin value) MOV A, PX JNB P2.1, TARGET ; jump if P2.1 is not set JB P2.1, TARGET ; jump if P2.1 is set Read the internal latch of the output port. ANL P1, A ; P1 P1 AND A ORL P1, A ; P1 P1 OR A INC P1 ; increase P1 63
Reading High at Input Pin Read latch 1. write a 1 to the pin MOV P1,#0FFH TB2 Vcc Load(L1) 2. MOV A,P1 external pin=high Internal CPU bus D Q P1.X 1 1 P1.X pin Write to latch Clk Q 0 M1 TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1 8051 IC 64
Reading Low at Input Pin Read latch 1. write a 1 to the pin MOV P1,#0FFH TB2 Vcc 2. MOV A,P1 Load(L1) external pin=low Internal CPU bus D Q P1.X 1 0 P1.X pin Write to latch Clk Q 0 M1 TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1 8051 IC 65
Port 1 as Input(Read from Port) In order to make P1 an input, the port must be programmed by writing 1 to all the bit. MOV A,#0FFH ;A=11111111B MOV P1,A ;make P1 an input port BACK: MOV A,P1 ;get data from P1 MOV P2,A ;send data to P2 SJMP BACK To be an input port, P0, P1, P2 and P3 have similar methods. 66
Instructions For Reading an Input Port Following are instructions for reading external pins of ports: Mnemonics Examples Description MOV A,PX MOV A,P2 Bring into A the data at P2 pins JNB PX.Y,.. JNB P2.1,TARGET Jump if pin P2.1 is low JB PX.Y,.. JB P1.3,TARGET Jump if pin P1.3 is high MOV C,PX.Y MOV C,P2.4 Copy status of pin P2.4 to CY 67
Reading Latch OR the Port 1: MOV P1,#55H ;P1=01010101 ORL P1,#0F0H ;P1=11110101 1. The read latch activates TB2 and bring the data from the Q latch into CPU. Read P1.0=0 2. CPU performs an operation. This data is ORed with bit 1 of register A. Get 1. 3. The latch is modified. D latch of P1.0 has value 1. 4. The result is written to the external pin. External pin (pin 1: P1.0) has value 1. 68
Reading the Latch 1. Read pin=0 Read latch=1 Write to latch=0 (Assume P1.X=0 initially) Read latch 2. CPU compute P1.X OR 1 0 Internal CPU bus Write to latch 3. write result to latch Read pin=0 Read latch=0 Write to latch=1 1 TB2 D Q P1.X Clk Q 0 1 0 Vcc Load(L1) M1 1 4. P1.X=1 P1.X pin TB1 Read pin 69 8051 IC
Read-modify-write Feature Read-modify-write Instructions This features combines 3 actions in a single instruction: 1. CPU reads the latch of the port 2. CPU perform the operation 3. Modifying the latch 4. Writing to the pin Note that 8 pins of P1 work independently. 70
Port 1 as Input(Read from latch) Exclusive-or the Port 1: MOV P1,#55H ;P1=01010101 AGAIN: XOR P1,#0FFH ;complement ACALL DELAY SJMP AGAIN Note that the XOR of 55H and FFH gives AAH. XOR of AAH and FFH gives 55H. The instruction read the data in the latch (not from the pin). The instruction result will put into the latch and the pin. 71
Other Pins P1, P2, and P3 have internal pull-up resisters. P1, P2, and P3 are not open drain. P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051. P0 is open drain. Compare the figures of P1.X and P0.X. However, for a programmer, it is the same to program P0, P1, P2 and P3. All the ports upon RESET are configured as output. 72
A Pin of Port 0 Read latch TB2 Internal CPU bus D P1.X Q P0.X pin Write to latch Clk Q M1 TB1 Read pin 8051 IC 73
Port 0(pins 32-39) P0 is an open drain. Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips. When P0 is used for simple data I/O we must connect it to external pull-up resistors. Each pin of P0 must be connected externally to a 10K ohm pull-up resistor. With external pull-up resistors connected upon reset, port 0 is configured as an output port. 74
Port 0 with Pull-Up Resistors Vcc 10 K DS5000 8751 8951 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 Port 0 75
Dual Role of Port 0 When connecting an 8051/8031 to an external memory, the 8051 uses ports to send addresses and read instructions. 8031 is capable of accessing 64K bytes of external memory. 16-bit address:p0 provides both address A0-A7, P2 provides address A8-A15. Also, P0 provides data lines D0-D7. When P0 is used for address/data multiplexing, it is connected to the 74LS373 to latch the address. There is no need for external pull-up resistors. 76
ALE Pin The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch. When ALE=0, P0 provides data D0-D7. When ALE=1, P0 provides address A0-A7. The reason is to allow P0 to multiplex address and data. 77
Port 2(pins 21-28) Port 2 does not need any pull-up resistors since it already has pull-up resistors internally. In an 8031-based system, P2 are used to provide address A8- A15. 78
Port 3(pins 10-17) Port 3 does not need any pull-up resistors since it already has pull-up resistors internally. Although port 3 is configured as an output port upon reset, this is not the way it is most commonly used. Port 3 has the additional function of providing signals. Serial communications signal:rxd, TxD External interrupt:/int0, /INT1 Timer/counter:T0, T1 External memory accesses in 8031-based system:/wr, /RD 79
Port 3 Alternate Functions P3 Bit Function Pin P3.0 RxD 10 P3.1 TxD 11 P3.2 INT0 12 P3.3 INT1 13 P3.4 T0 14 P3.5 T1 15 P3.6 WR 16 P3.7 RD 17 80
A simple project using AT89C51 81