Ch 1. Introduction to Embedded Systems Part B Embedded ARM Applications Byung Kook Kim Dept of EECS Korea Advanced Institute of Science and Technology
Overview Trends in embedded system design Integrate all the major system functions apart from some memory components into a single chip Benefits in terms of component costs, reliability, and power-efficiency Advance in semiconductor process technology: millions of transistors built cheaply The era of complex systems on a single chip Several examples of ARM-based system on chips Embedded Systems, KAIST 2
1.7 The VLSI Ruby II Advanced Communication Processor Ruby II advanced communication processor chip VLSI Technology, Inc Organization -> clock clock control ARM core 512 x 32 SRAM external interrupts (3) interrupt controller counter/ timers parallel i/f 1,2,3,4 control I/O mode select PCMCIA host interface UART1 ho st FIFOs (16 x 8) external bus control address (22) data (8/16/32) serial UART2 high-speed serial i/f serial FIFOs (16 x 8) serial controller parallel interface 0 I 2 C,... 8 data bits & control Embedded Systems, KAIST 3
The VLSI Ruby II Advanced Communication Processor (II) Ruby II organization Based on an ARM core 2 Kbytes of fast (zero wait state) on-chip SRAM Critical routines can be loaded to get the best performance and minimum power consumption Peripheral modules PCMCIA interface Four byte-wide parallel interfaces Two UARTs Byte-wide FIFO buffers Synchronous communications controller Serial controller: I 2 C for battery-backed RAM, real-time clock, E 2 PROM, and audio codec External bus interface 8-, 16-, and 32-bit data buses and flexible wait state generation Counter/timer block Three 8-bit counters connected to a 24-bit prescaler Interrupt controller Programmable control of all on- and off-chip interrupt sources Embedded Systems, KAIST 4
The VLSI Ruby II Advanced Communication Processor (III) Ruby II power-management modes 1. On-line all circuits are clocked at full speed 2. Command the ARM core runs with 1 to 64 wait states but all other circuitry runs at full speed. An interrupt switches the system into on-line mode immediately. 3. Sleep all circuitry is stopped apart from the timers and oscillators. Particular interrupts return the system to on-line mode. 4. Stopped all circuits (including the oscillators) are stopped. Particular interrupts return the system to on-line mode. Packaging 144- and 176-pin thin quad flat packs Up to 32 MHz at 5 V. At 20 MHz, 30 ma in on-line mode, 7.9 ma in command mode, 1.5 ma in sleep mode, and 150 ua in stop mode. Embedded Systems, KAIST 5
1.8 The VLSI ISDN Subscriber Processor (VIP) VIP Programmable engine for ISDN (Integrated Services Digital Network, a digital telephony standard) subscriber communications Developed by Hagenuk GmbH Licensed to VLSI Technology for sale as ASSP (Application Specific Standard Part) Incorporates most of the circuitry required to implement a fullfeature ISDN terminal, supporting voice, data, and video services ISDN S0-interface, a numeric keypad, a number display, a microphone and an earphone Applications ISDN terminal equipment: PABX telephones, H.320 videophones, integrated PC communications ISDN to DECT (Digital European Cordless Telephone) controllers ISDN to PCMCIA communication cards. Embedded Systems, KAIST 6
The VLSI ISDN Subscriber Processor (II) Typical VIP system configuration volume V24 interface Driver S0-ISDN interface ISDN Subscriber Processor hook switch hands-free power ROM RAM K E Y P A D Embedded Systems, KAIST 7
The VLSI ISDN Subscriber Processor (III) VIP organization (Inside) external interrupts (3) clock clock control ARM6 core 768 x 32 SRAM interrupt controller timer & watchdog ports parallel interface control handset/ hands-free G.711 codec external bus control address (23) data (8/16/32) S0-interface battery, volume B and D channels ADCs (2) DRAM controller mux address ras, cas serial DSP serial i/f address decoder chip selects Embedded Systems, KAIST 8
The VLSI ISDN Subscriber Processor (IV) Memory interface Supports 8-, 16-, and 32-bit off-chip static RAMs and ROMs and 16- and 32-bit dynamic RAMs Divided into 4 ranges, each with programmable number of wait states 3 Kbyte on-chip RAM S0-interface Connection to an S0-interface bus via isolating transformers and surge protection PLL for data and clock recovery, framing, and low-level protocols 192 Kbit/s raw data includes two 64 Kbit/s B channels (8-bit 8 KHz speech samples) and one 16 Kbit/s D channel (control purposes) Codec G.711 codec On-chip analog front end: Direct connection to a telephone handset and a hands-free microphone and speaker Input and output independent programmable gains Amplification stages have power-down modes to save power. Embedded Systems, KAIST 9
The VLSI ISDN Subscriber Processor (V) ADCs Based on timing how long it takes to discharge a capacitor to the input voltage level Very simple way to measure slowly varying voltages Comparator and counter Measure the voltage from a volume control potentiometer or to check the battery voltage in a portable application Keypad interface Parallel output ports to strobe the columns of the keypad Parallel input ports with internal pull-down resistors to sense the rows Key press will generate an interrupt: ARM can activate individual columns and sense rows. Clocks and timers 38.864 MHz and 460.8 KHz during power-down Watchdog at every 1.28 sec 2.5 ms timer interrupts for DRAM refresh and multitasking. Embedded Systems, KAIST 10
1.9 The OneC VWS22100 GSM Chip OneC VW22100 Developed by VLSI Technology, Inc System-on-chip design for GSM mobile telephone handset All the functions required in a handset with addition of external program and data memory and a suitable radio module Example: Samsung SGH2400, a dual-band (GSM 900/1800) handset with hands-free voiceactivated dialing -> Embedded Systems, KAIST 11
The OneC VWS22100 GSM Chip (II) Typical GSM handset architecture speaker SIM card eeprom IrDA mic ringer VWS22100 radio module ROM RAM K E Y P A D LCD Embedded Systems, KAIST 12
The OneC VWS22100 (6) GSM Chip (III) JTAG test/debug ARM7TDMI core interrupt controller boot ROM UART1 (6) VWS22100 organization ARM7TDMI core General purpose controller GSM protocol layers DSP core Baseband signal processing (13) (20) audio i/f radio i/f program ROM Oak DSP core program RAM memory controller PCM i/f DSP radio port hardware coprocs DSP bus DSP subsystem ARM bus UART2/ IrDA high-speed serial i/f (2) SIM i/f RTC external bus control ADC (4) (5) (4) 32 KHz cntrl (6) addr (20) data (16) (7) data ROM data RAM power manager keypad scanner (10) interrupt controller config./ status GPIO PWM (11) Embedded Systems, KAIST 13
The OneC VWS22100 GSM Chip (IV) DSP subsystem Based on the 16-bit Oak DSP core Real-time signal processing functions Voice coding Equalization Channel coding Echo cancellation Noise suppression Voice recognition Data compression ARM7TDMI subsystem Responsible for the system control functions The user interface software The GSM protocol stack Power management Driving the peripheral interface Running some data applications Embedded Systems, KAIST 14
The OneC VWS22100 GSM Chip (V) On-chip debug Single JTAG interface ARM7TDMI EmbeddedICE module Debug technology on the Oak DSP core Other test and debug facilities Power management Global and selective power-down modes The ability to slow down the system clock in idle mode The analog circuits also can operate at reduced power The on-chip pulse-width modulation outputs control battery charging The on-chip ADCs provide for the monitoring of the temperature and battery voltage to give optimum operation. Embedded Systems, KAIST 15
1.10 The Ericsson-VLSI Bluetooth Baseband Controller Bluetooth De-facto standard for wireless data communication for the 2.4 GHz band Consortium of Ericsson, IBM, Intel, Nokia, and Toshiba Support short-range communication (to 10 m range) using radio communication with 1 Mbit/s Robust communication in a noisy and uncoordinated environment Frequency hopping scheme and forward error correction For laptop, cellular telephone, printer, PDA, desktop, fax, keyboards, and so on Provide bridge to existing networks Bluetooth piconet Bluetooth units dynamically form ad hoc piconets, which are groups of 2 to 8 units that operate the same frequency-hopping scheme One of the units will operate as master: Defines the clock and hopping sequence. Embedded Systems, KAIST 16
The Ericcson-VLSI Bluetooth Baseband Controller (II) Bluetooth system A typical Bluetooth system flash memory flash memory address data Bluetooth Baseband Controller radio module control host interface (RS232/USB) Embedded Systems, KAIST 17
The Ericcson-VLSI Bluetooth Baseband Controller (III) Bluetooth controller organization clock JTAG signals (5) clock control ARM7TDMI core 4 Kbyte I-cache internal ROM 16K x 32 SRAM control interrupt controller counter/ timers ex ternal bus control address (20) data (8/16) UART1,2,3 I/O mode select I 2 C i/f FIFOs EBC block radio interface USB i/f Embedded Systems, KAIST 18
The Ericcson-VLSI Bluetooth Baseband Controller (IV) Ericsson Bluetooth core Power-optimized hardware block Handles all the Link Controller functionality within the Bluetooth specification Interface logic to a Bluetooth radio communication Performs all the packet-handling functions for point-to-point, multislot, and point-to-multipoint communications Combination of circuit and packet switching Power management 1. On-line: all blocks are clocked at their normal speed. The ARM7TDMI core clock 13 to 40 MHz. 40 ma max. 2. Command: The ARM7TDMI clock is slowed down by the insertion of wait states 3. Sleep: The ARM7TDMI click is stopped. 0.3 ma. 4. Stopped: The clock oscillator is turned off. Embedded Systems, KAIST 19
The Ericcson-VLSI Bluetooth Baseband Controller (V) Bluetooth silicon Photograph of a Bluetooth die -> Bluetooth characteristics Process 0.35 um Transistors 4,300,000 MIPS 12 Metal layers 3 Die area 20 mm 2 Power 75 mw Vdd 2.5 V Clock 0-13 MHz MIPS/W 160 Embedded Systems, KAIST 20
1.11 The ARM7500 and ARM7500FE Features Highly integrated single-chip computer Combines the major components of the Acorn Risc PC Principal macrocells The ARM CPU core The FPA10 floating-point coprocessor (ARM7500FE) The video and sound macrocell The memory and I/O controller Embedded Systems, KAIST 21
The ARM7500 and ARM7500FE (II) The ARM CPU core Contains most of the functionality of the ARM710 ARM7TDMI without Thumb and embedded debug support Reduced cache 4 Kbytes (from 8 Kbytes) 4-way set-associative mixed instruction and data cache Memory management unit Based on a 2-level page table 64-entry translation look-aside buffer A write buffer The FPA10 floating-point unit Up to 6 MFLOPS at 40 MHz Embedded Systems, KAIST 22
The ARM7500 and ARM7500FE (III) The video and sound macrocell Video controller Generate displays using a pixel clock of up to 120 MHz 256-entry color palette with on-chip 8-bit DACs for RGB Additional control bits for external mixing and fading Support a separate hardware cursor Can drive a high-resolution color monitor or single- or double-panel grey-scale or color LCD Sound controller 8 independent channels of 8-bit analog stereo sound Played through an on-chip exponential DAC 16-bit sound samples through a serial digital channel and an external CD-quality DAC DMA controller for video/audio data channels Embedded Systems, KAIST 23
The ARM7500 and ARM7500FE (IV) The memory and I/O controller Memory controller Direct connection of up to four banks of DRAM and two banks of ROM Programmed to be 16 or 32 bits wide Double access for 32-bit quantities in 16-bit banks DRAM controller Page mode accesses for sequential cycles in bursts of up to 256 transfers Supports a range of DRAM refresh modes ROM controller Supports burst mode 3 DMA controller Handle data streams for video, cursor, and audio channels I/O controller Manages 16-bit off-chip I/O bus Number of on-chip interfaces: 4 comparators, 2 serial ports, counter/timers, 8 general-purpose open-drain I/O lines, and programmable interrupt controller. Embedded Systems, KAIST 24
The ARM7500 and ARM7500FE (V) Typical ARM7500 system diagram cas[3:0] ras[3:0] DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM ARM7500 D[31:0] ROM ROM LA[ 28: 0] interrupts video RA [11:0] analogue sound analogue inputs keyboard & mouse module selects I/O module I/O module Embedded Systems, KAIST 25 BD[15:0]
The ARM7500 and ARM7500FE (VI) Applications Low-cost versions of the Acorn Risc PC Online Media interactive video set-top box Restricting the video data stream to normal DRAM High-resolution displays 1280 x 1024 and above the number of colors become restricted due to the bandwidth limitations of standard DRAM Ideally suited LCD at VGA (640 x 480) TV quality display Hand-held test equipment Multimedia applications. Embedded Systems, KAIST 26
The ARM7500 and ARM7500FE (VII) ARM7500 silicon -> 5% ARM core area ARM7500 characteristics Process 0.6 um Transistors 550,000 MIPS 30 Metal layers 2 Die area 70 mm 2 Power 690 mw Vdd 5 V Clock 0-33 MHz MIPS/W 43 Embedded Systems, KAIST 27
1.12 The ARM7100 Features Highly integrated microcontroller Suited to a range of mobile applications Smart mobile phones and palm-top computers Psion Series 5MX -> Embedded Systems, KAIST 28
The ARM7100 (II) The Psion Series 5 hardware organization Principal user input devices Keyboard: parallel I/O Stylus pointing device: transparent digitizing tablet overlaid on the LCD display Infrared via ADC Communication RS232C serial interface IrDA compliant infrared interface for wireless connection to printers, modems, and host PCs Audio codec: microphone and speaker infrared RS232 audio ARM7100 Embedded Systems, KAIST 29 DRAM PC cards IrDA Tx/Rx codec ROM Flash PSU ADC digitizing tablet 640 x 240 LCD keyboard
The ARM7100 (III) ARM7100 organization ARM710a CPU ARM MMU 8 Kbyte 4-way associative quadword line cache 4-address 8-data word write buffer AMBA bus Peripherals LCD controller Serial & parallel I/O ports Interrupt controller 32-bit external bus interface DRAM controller ARM710a MMU 3.6864 MHz clock PLL 32.786 KHz RTC osc. ARM7 core power mgt. UART codec i/f sync serial 8 Kbyte cache counter/ timers FIFOs AMBA LCD controller ex ternal bus control DRAM controller expansion interrupt controller control address (28) data (32) DRA(13) RAS, CAS (8) WE, OE(2) parallel I/O PSU control Embedded Systems, KAIST 30
The ARM7100 (IV) Power management Intended for use in battery-powered equipment High performance in response to user input Operate at very low power consumption levels Levels Full operation mode: 14 MIPS, 24 ma at 3 V Idle mode: CPU stopped but other systems running. 33 mw Standby mode: 32 KHz running. 33 uw Other features to enhance power-efficiency Support for self-refresh DRAM. Embedded Systems, KAIST 31
The ARM7100 (V) ARM7100 silicon -> ARM7100 principal characteristics Process 0.6 um Transistor N/A MIPS 30 Metal layers 2 Die area N/A Power 14 mw Vdd 3.3 V Clock 18.432 MHz MIPS/W 212 Embedded Systems, KAIST 32
1.13 The SA-1100 Features High-performance integrated system-on-chip Based on a modified version of SA-110 StrongARM CPU core Intended for use in mobile phone handsets, modems, and other handheld applications High performance with minimal power consumption. Embedded Systems, KAIST 33
The SA-1100 (II) SA-1100 organization instruction MMU instruction cache SA-1 core data cache mini-cache data MMU CPU core write buffer read buffer system bus data (32) LCD (5) LCD control DMA control bridge memory & PCMCIA address (26) control 3.6864 MHz 32.786 KHz clock PLL RTC osc. interrupt control RTC serial 0 serial 1 USB (2) SDLC (2) I/O pins (28) battery (3) reset (2) generalpurpose I/O power manager OS timer reset control peripheral bus serial 2 serial 3 serial 4 IrDA (2) UART (2) Codec (4) Embedded Systems, KAIST 34
The SA-1100 (III) CPU core SA-1 processor core Exception vector relocation mechanism (for Windows CE) 16 Kbyte instruction cache using a 32-way associative CAM-RAM structure with 8-word lines MMU with ProcessID mechanism (for Windows CE) 8 Kbyte 32-way associative data cache in parallel with a 512 byte 2-way set-associative cache Allow large data structures to be cached without causing major pollution of the main data cache Addition of read buffer Pre-load data before the processor requests Addition of hardware breakpoint and watchpoint registers. Embedded Systems, KAIST 35
The SA-1100 (IV) Memory controller Up to 4 banks of 32-bit off-chip DRAM Conventional or extended data out (EDO) variety ROM, flash, and SRAM are also supported PCMCIA interface Two card slots are supported with some external glue logic System control On-chip A reset controller A power management controller that handles low-battery warnings and switches the system between its various operating modes An operating system timer block that supports general timing and watchdog functions An interrupt controller A real-time clock that runs from a 32 KHz crystal source 28 general-purpose I/O pins. Embedded Systems, KAIST 36
The SA-1100 (V) Peripherals LCD controlelr Serial ports: USB, SDLC, IrDA, codec, and standard UART 6-channel DMA Bus structure Two buses connected through a bridge The system bus: connects all the bus masters and the off-chip memory The peripheral bus: connects all the slave peripheral devices Similar to AMBA ASB-APB split Minimizes the bus width Reduces the complexity and cost Applications Off-chip memory: DRAM and ROM/flash Necessary interface electronics for the various peripheral interfaces, display, and so on Very simple at the PCB level, yet very powerful processing capability and sophisticated system architecture. Embedded Systems, KAIST 37
The SA-1100 (VI) SA-1100 silicon -> Characteristics Process 0.35 um Transistors 2,500,000 MIPS 220/250 Metal layers 3 Die area 75 mm 2 Power 330/550 mw Vdd 1.5/2V Clock 180/220 MHz MIPS/W 665/450 Embedded Systems, KAIST 38
1.14 Mio 168 Pocket PC with Integrated GPS Runs on Windows Mobile 2003 for Pocket PC Utilizes an Intel XScale processor A 16-bit TFT LCD display with LED backlighting offers up to 65,536 colors Bundled with a complete navigation software package Routing: Easy-to-follow turnby-turn visual and voice prompts guide you to your destination Plan trips and optimize routes with multi-point routing feature Automatic route recalculation suggests an alternate route if you take a wrong turn. Embedded Systems, KAIST 39
Function CPU Operating System I/O Display Memory Audio Input Method Expansion Slot Microphone Intel Xscale 300 MHz Specification Windiws Mobile software for Pocket PCs 3.5 color Transflective LCD, LED Backlighting, 240 x 320, 65K colors 32MB Flash ROM. 64MB SDRAM Voice Recording(Mono). MP3 Playback support. Media Player Stylus pen/software kdyboard/handwriting Recognition SD/MMC. SD IO Builit-in type x 1(Mono) Speaker Builit-in Monaural type speaker x 1 Headphone 2.5mm Mini jack x 1 USB Infrared battery Dimension Weight Power Supply USB 1.1 Client for ActiveSync IrDA (SIR). Consumer IR (4 meters) Embedded Lithium lon Battery 1350mAh Active:12 hours(fully charged main battery, w/o GPS) Suspend:21 days(fully charged main battery) 112.8 mm (H) x 69.6 mm (W) x 16.3~24.15mm (D) 147g Input 100~240VAC; Output 5VDC, 1A DC Embedded Systems, KAIST 40