Name: Email Username: Lab Date and Time: CSC 101: Lab #5 Boolean Logic Practice Due Date: 5:00pm, day after lab session Lab Report: Answer the questions within this document as you encounter them. Also, upload a Word document by the lab submission deadline with screenshots of all five circuits you design using the Assignments, Lab5 link Purpose: The purpose of this lab is to provide you with hands-on experience in manipulating and designing simple Boolean logic circuits using a logic simulator. You will be asked to test, understand from looking at, and build from scratch different Boolean logic circuits. Verifying an OR Circuit Step 1 Use the logic.ly interface (found here: http://logic.ly/demo/) to build and verify a simple OR circuit, using two input Switches, an OR gate, and a LightBulb output. Refer back to the Prelab for the process of how to drag gates onto the design area and how to connect the gates. Step 2 By clicking on and off the input switches, test all four possible input values for the OR gate, as outlined in the table below, and verify that the outputs you see match the expected outputs. Question 1 [4 pts]: Fill in the Actual column with the result you see. If your results don t match those expected, ask a TA or instructor to help fix your circuit. Input A Input B Expected Actual from OR 0 0 0 0 1 1 1 0 1 1 1 1 Step 3 Take a screenshot of your designed circuit (using the PrtSc key, above F10). Open a blank Word document, and paste your screenshot into that Word document. Save your document, but leave it open, as we will place other screenshots in it later in the lab. Determining the Function of a Circuit Step 4 Implement this Boolean logic circuit in logic.ly, and then answer the questions below:
Question 2 [4 pts]: Test all possible combinations of inputs on your circuit and complete the table below. Input A Input B 0 0 0 1 1 0 1 1 Question 3 [4 pts]: Go back to the pre-lab. Which of the basic circuits introduced in the pre-lab is this circuit equivalent to (equivalence meaning the outputs are the same)? Step 5 Take a screenshot of your designed circuit (using the PrtSc key, above F10). Paste your screenshot into your already open Word document and save the document. Building and Verifying a NAND Circuit Step 6 Manually design in the logic.ly interface a NAND circuit (we brought this circuit up originally in the pre-lab) using the following setup: two input Switches, an AND gate, a NOT gate, and a LightBulb output. The AND gate s output should be negated (sent through the NOT gate), with the NOT gate s output being sent to the LightBulb. Step 7 Now note that there is actually already a built-in NAND gate in the logic.ly interface. The builtin NAND looks like an AND gate, but has a small difference. It has a small circle, indicating negation, between the gate and the output connector. This is highlighted with an arrow in the image below. Now drag one of these NAND gates onto your design space along with another LightBulb output and connect it appropriately to your input Switches as shown in the diagram below. Your designed NAND (to be completed, hooked up to switches and output) The built in NAND also hooked up to your inputs. Step 8 Now that you have both circuits setup in logic.ly, the manually designed NAND and the built-in NAND, try all different possible inputs (there are 4, listed in the table below) and record the outputs for each circuit in the table on the next page.
Question 4: [8 pts] Fill in the two output columns with the results you see from trying all possible inputs. Input A Input B from YOUR NAND from Builtin NAND 0 0 0 1 1 0 1 1 Step 9 Take a screenshot of your designed circuit and paste and save your screenshot into your already open Word document. Building a 3-bit OR circuit: All of the basic logic gates supported in logic.ly (the gates you can design with) allow 2 inputs, and all of the circuits we have developed so far have only made use of two inputs. However, there are plenty of situations where we may want to have more than two inputs to a circuit. As an example, we may want to test whether any of a group of three bits (inputs) has the value 1. A 3-bit OR circuit should implement the following logic table: Input A Input B Input C 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 In order to simplify this particular desired task [A OR B OR C], we can think of it as a two part problem. The question of (A OR B OR C) can be broken down into ( (A OR B) OR C). Let s give the output of (A OR B) the name X. Then the output of the (A OR B OR C) can be defined as (X OR C). Now we can think of the table as follows: Input A Input B Input C (A OR B) (call it X) (X OR C) (from red entries) 0 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 Step 10 Now that you have an idea of how a 3-input OR circuit should work, using the logic.ly interface design and test a 3-input OR circuit using three input Switches, two OR gates, and a single LightBulb outut which correctly implements the 3-input OR table above.
Step 11 Take a screenshot of your designed circuit (using the PrtSc key, above F10) and paste and save your screenshot into your already open Word document. Question 5: [16 pts] Now we want to investigate a 3-input XOR circuit (different from the OR circuit above). We can think of a 3-input XOR circuit as having the value 1 if and only if exactly one of the inputs has the value 1 and all the others have a value of 0. We are wondering whether or not we can decompose a 3-input XOR into two two-input XORs (you already shoed we could do this for OR). This is a thought question. Using your understanding of the XOR gate, complete the two empty columns you do not need to design anything in logic.ly Input A Input B Input C (A XOR B) (Z XOR C) Desired (Call it Z) 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 Question 6 [6 pts]: State YES or NO for the following question: can the the 3-input XOR be decomposed into ((A XOR B) XOR C), similar to how we decomposed the 3-input OR? Also, explain: Why or why not? Building a Subtracter In class, you saw how to build a half-adder for bits. An image of a half-adder is shown below, with the Sum output at the top and the Carry output at the bottom. (No need to implement this just keep reading!)
A half adder has the following truth table: Input A Input B Sum Carry 0 1 1 0 1 0 1 0 1 1 0 1 Looking at the Sum column and comparing it to the truth tables on page 3 of the pre-lab, we see the Sum column is equivalent to the XOR gate output, hence why the XOR gate provides the value for the Sum in the picture above. Similarly, the Carry column matches the AND gate outputs, thus the use of AND to provide the value for the Carry. We would like to design a half-subtracter (computing A minus B in bits), which requires the following logic table to be implemented. Input A Input B Difference BorrowRequired 0 1 1 1 1 0 1 0 1 1 0 0 Read and answer the questions below regarding construction of this half-subtracter. Question 7: [6 pts] Reviewing the logic tables on page 3 of the pre-lab, which logic gate would work for computing the Difference output and why? Question 8: [8 pts] Using the NOT and AND gates, devise and draw below (on paper, not in logic.ly) a 2 gate series (an inter-connection of the two gates) that will correctly generate the BorrowRequired output from your A and B inputs. Also, justify your choice in words. Question 9: [4 pts] Build your designed circuit in the Logic Gate Simulator and test it. Did it work as you expected? If not, what were the errors?
Step 12 Take a screenshot of your designed circuit (using the PrtSc key, above F10) and paste your screenshot into your already open Word document. You can now save and close the Word document, as you are done with the lab. Submit your answers to these questions by the deadline of 5:00pm the day after your lab session. Upload the Microsoft Word file with screenshots of all circuits you designed to Sakai using the Assignments, Lab 5 link as well and by the same time. The answers to the questions in this lab document are worth 60 points (points listed by questions), and the screenshots are worth 20 points (4 points each), for a total of 80 for the lab document.