ECEN 468 Advanced Logic Design Lecture 28: Synthesis of Language Constructs
Synthesis of Nets v An explicitly declared net may be eliminated in synthesis v Primary input and output (ports) are always retained in synthesis v Synthesis tool will implement trireg, tri0 and tri1 nets as physical wires module and3( y, a, b, c ); input a, b, c; output y; wire y1; assign y1 = a & b; assign y = y1 & c; endmodule a b c y 2
Synthesis of Register Variables v A hardware register will be generated for a register variable when o It is referenced before value is assigned in a behavior o Assigned value in an edge-sensitive behavior and is referenced by an assignment outside the behavior o Assigned value in one clock cycle and referenced in another clock cycle v Multi-phased latches may not be supported in synthesis 3
Synthesis of Integers v Initially implemented as a 32-bit register v Always specify size when declare a constant o For example, parameter a = 3 d7 will consume 3 bits while default is 32 bits 4
Unsupported Data Types v real v time v realtime v string 5
Synthesis of Memories v No direct support v Usually implemented as array of registers v Not efficient as external memory v Minimize the usage of such memory 6
Synthesis of x and z v A description that uses explicit x or z values for data selection cannot be synthesized v The only allowed usage of x is in casex and casez statements v The only allowed use for z is in constructs that imply 3-states device v If a UDP assigns a value of x to a wire or reg, it will be treated as don t care 7
Synthesis of Assignment v Support by synthesis is vendor-specific v Continuous assignment can be mapped directly to combinational logic v Procedural assignment, LHS must be register variable v Procedural continuous assignment o Supported by some tools v PCA to register cannot be overwritten by any procedural assignment 8
Expression Substitution in Procedural Assignment module multiple_assign ( out1, out2, a, b, c, d, sel, clk ); output [4:0] out1, out2; input [3:0] a, b, c, d; input sel, clk; reg [4:0] out1, out2; always @ ( posedge clk ) begin out1 = a + b; out2 = out1 + c; if ( sel == 1 b0 ) out1 = out2 + d; end endmodule module multiple_assign ( out1, out2, a, b, c, d, sel, clk ); output [4:0] out1, out2; input [3:0] a, b, c, d; input sel, clk; reg [4:0] out1, out2; always @ ( posedge clk ) begin out2 = a + b + c; if ( sel == 1 b0 ) out1 = a + b + c + d; else out1 = a + b; end endmodule 9
Synthesis of fork join Blocks v Synthesis tools may o Either fail o Or require that it does not contain event and delay controls that are equal to or longer than a clock cycle equivalent to a set of nonblocking assignments 10
Synthesis of the disable Statement v External disables imply sequential logic v Internal disables -> reset or interrupt signals 11
Synthesis of Tasks and Functions v Synthesis tools expand tasks and functions v If multiple calls made to a task, duplicated control logic may result v No mechanism to synchronize multiple calls to the same task v A task may not contain inout ports v Any specify endspecify block is ignored by synthesis 12
Example: Sequence Detector v Single bit serial input o Synchronized to falling edge of clock v Single bit output o Assert if two or more successive 0 or 1 at input o Active on rising edge of clock Clock Input Output 13
State Transition Diagram State0 Start state 0/1 State1 0/0 1/0 1/0 State2 1/1 Input 0 0/0 Input 1 14
Example: Problematic module seq_det_wrong ( clk, rst, in, out ); input clk, rst, in; output out; reg [1:0] state; reg out; parameter state_0 = 2 b00; parameter state_1 = 2 b01; parameter state_2 = 2 b10; always @ ( posedge clk or posedge rst ) if ( rst == 1 ) state <= state_0; else case ( state ) state_0: if ( in == 0 ) state <= state_1; else state <= state_2; state_1: if ( in == 0 ) state <= state_1; else state <= state_2; state_2: if ( in == 0 ) state <= state_1; else state <= state_2; default: state <= state_0; endcase always @ ( state ) case ( state ) state_0: out <= 0; state_1: if ( in == 0 ) out <= 1; else out <= 0; state_2: if ( in == 0 ) out <= 0; else out <= 1; default: out <= 0; endcase endmodule 15
Example: Correct Version module seq_det_correct( clock, reset, in, out ); input clock, reset, in; output out; reg [1:0] state; reg out; parameter state_0 = 2 b00; parameter state_1 = 2 b01; parameter state_2 = 2 b10; always @ ( posedge clock or posedge reset ) if ( reset == 1 ) begin state <= state_0; out <= 0; end else case ( state ) state_0: if ( in == 0 ) begin state <= state_1; out <= 0; end else begin state <= state_2; out <= 0; end state_1: if ( in == 0 ) begin state <= state_1; out <= 1; end else begin state <= state_2; out <= 0; end state_2: if ( in == 0 ) begin state <= state_1; out <= 0; end else begin state <= state_2; out <= 1; end default: begin stage <= state_0; out <= 0; end endcase endmodule 16