Design of Arithmetic Units ECE152B AU 1

Design of Arithmetic Units ECE152B AU 1

Design of Arithmetic Units We will discuss the design of Adders/Substractors Multipliers/Dividers li id and analyze algorithms & methods to perform the desired d operations within an acceptable time. Addition A basic cell is the full adder (FA) ECE152B AU 2

A i B i C in C out=a i B i +B i C in+a i C in A B C in FA Cot F F i=a i B i C in C out F I AI-H BI-H COUT-H AI-H BI-H CIN-H FI-H CIN-H AI-H ECE152B AU 3

A word adder composed of full adders: A 7 B 7 A 6 B 6 A 5 B 5 A 4 B 4 A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 A B C in A B C in A B C in A B C in A B C in A B C in A B C in A B C in FA FA FA FA FA FA FA FA Cot F Cot F Cot F Cot F Cot F Cot F Cot F Cot F C out F 7 F 6 F 5 F 4 F 3 F 2 F 1 F 0 ECE152B AU 4

This kind of addition process is called a ripple carry adder, since the carry at each stage is propagated to the next stage. For an N-bit addition: (G: one gate delay) T ADDRCA =N T FA = N (2 G) Ripple carry adders are an example of a minimal gate solution, but the time required for the result may not be acceptable. Look-ahead carry adder (LACA): more hardware while faster ECE152B AU 5

Now look at the logic equation of Cout: C out = AB+AC in +BC in = AB+C in (A+B) If AB is asserted, there will be a carry regardless of the value of the carry input: this term (AB) is called the carry generate (CG) function. If (A+B) is asserted, any carry supplied to this stage is passed on to the next: this term (A+B) is called the carry propagate (CP) function. ECE152B AU 6

Data In Carry in A B Cin CG LACA CP F Carry Generate Carry Propagate Sum out The time required to create the carry generate and carry propagate is a single gate delay. The carry generate and carry propagate lines are not function of the carry input. A four-bit LACA: ECE152B AU 7

CG0 CP0 Cin Look-Ahead Carry Generator C3 CG3 CP3 C2 CG2 CP2 C1 CG1 CP1 CG0 CP0 A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 A B Cin CG LACA CP F A B Cin CG LACA CP F A B Cin CG LACA CP F A B Cin CG LACA CP F F 3 F 2 F 1 F 0 ECE152B AU 8

All of the CG & CP lines will be stable one gate delay after the inputs are stable. The Look-Ahead Carry Generator (LACG) has the responsibility of creating the carry for each stage: C 1 will be asserted if CG 0 is asserted or if CP 0 is asserted & Cin is asserted. i.e. C 1 = CG 0 +CP 0 C in C 2 =CG 1 +CP 1 C 1 =CG 1 +CP 1 (CG 0 +CP 0 C in ) =CG 1 +CP 1 CG 0 +CP 1 CP 0 C in ECE152B AU 9

As the carries become more significant the amount of logic needed to generate the carry becomes larger. However, all carries will be generated in 2 gate delays (in LACG). The addition performed by the above 4-bit LACA requires only 5 gate delay: 1 to generate CG & CP for each LACA. 2 to generate all carries. 2 to propagate the effect of the carries to the outputs ECE152B AU 10

For a 4-bit Ripple Carry Adder, the delay is 4 2=8 gate delay. A LACG the provided the carries for a large adder (e.g. 64 bits) would be prohibitively expensive in terms of # of gates. Solution: cascade the LACGs in exactly the same fashion as the LACAs The LACG also generates a CG & CP that can be utilized by a second stage of LACG. ECE152B AU 11

( Computer Design, by G.Langdon, JR, P145) ECE152B AU 12

181s, 4-bit ALUs, generate the CG & CP signals required. 182s are 4-bit LACGs that t handle the CG&CP signals from 4 modules. The time required for such an addition: T LACA = 2 + 4 (log b (N) -1) Where N: # of bits to be added d b: # of bits handled by an ALU or a LACG. If no LACG is needed d (N <= b), T LACA =2. ECE152B AU 13

The LACGs are added in a tree type of structure, where the fanout of each node of the tree is b. Each level of LACGs requires a 4-gate delay: 2 gate delay for generating g CG&CP for the next level of LACGs & 2 gate delay for computing the carries after Cin is ready. ECE152B AU 14

Addition for a 2 s complement system Consider 75 10 +58 10 01001011 -- 75 in base 2 00111010 -- 58 in base 2 10000101 -- In 2 s complement this is -123 An 8-bit two s complement number system can only represent values from -128 to +127.The most significant bit is a sign bit. The above addition causes an overflow ECE152B AU 15

Design a circuit that will detect the occurrence of an overflow for a two scomplement system. The overflow occurs when i) Two position numbers are added & a negative number results; or ii) Two negative numbers are added & a positive number results. SIGN_A SIGN_B ALU_SIGN SIGN_A SIGN_B ALU_SIGN OVER_FLOW ECE152B AU 16

The arithmetic bits included in the status register are set & cleared as directed by the control logic. Not all of the instructions will be allowed to modify the status bits, and some status bits will be modified by more instructions than other bits. ECE152B AU 17

Set_over_bit_L Over_flow_H Strobe_over_H Sys_clk_L clear_over_bit_l Sys_reset_L D S clear Over_flow_bit ECE152B AU 18

Multiplication Iterative multiplication methods Assume 2 5-bit numbers A: A 4 A 3 A 2 A 1 A 0 B: B 4 B 3 B 2 B 1 B 0 P=A B = A B 4 B 3 B 2 B 1 B 0 = A B 4 + 3 + 2 + 1 4 2 A B 3 2 A B 2 2 A B 1 2 + A B 0 2 0 In practice, we can write it as follows: ECE152B AU 19

A4 A3 A2 A1 A0 B4 B3 B2 B1 B0 PP0 A4 B0 A3 B0 A2 B0 A1 B0 A0 B0 PP1 A4 B1 A3 B1 A2 B1 A1 B1 A0 B1 PP PP2 A4 B2 A3 B2 A2 B2 A1 B2 A0 B2 PP3 A4 B3 A3 B3 A2 B3 A1 B3 A0 B3 PP4 A4 B4 A3 B4 A2 B4 A1 B4 A0 B4 PR sum of all rows PP 0 to PP 4 are called partial product arrays. The most straight-forward method for doing the multiply is the traditional shift and add method. ECE152B AU 20

0 MIER_CLK MIER_LD 8 Multiplier Multiplier 01101001 Multiplicand 0 1 0 1 1 0 1 0 PP 0 00000000 PP 1 01101001 PP 2 00000000 8 PP 3 01101001 PP 1 0 1 1 0 1 0 0 1 PP 5 00000000 PP 6 01101001 PP 7 00000000 8 Product 0 0 1 0 0 1 0 0 1 1 1 0 1 0 1 0 shift register Multiplicand PP 4 0 1 1 0 1 0 0 1 prod_clk 1 8 8-bit adder Cout D 0 D 7 D 1 7 7 8-bit register 8-bit register prod_clr D 0 D 7 D 1 7 8 ECE152B AU 21

An 8 8 8 Multiplier: li ECE152B AU 22

An 8-bit adder (2 4-bit 283s) is used to add a partial product array to the accumulating sum stored in a 16-bit register (2 273s). The partial product is created by ANDing the multiplicand with a multiplier bit obtain from a shift register. The shifting of the result is done by hard wiring the accumulating sum to line up with the appropriate p bit positions in the partial product. the timing diagram of the control signals: ECE152B AU 23

MIER_LD-L MIER_CLK-H PROD_CLR-L PROD_CLK-H Clear Product Reg, Load Multiplier Add partial Products to Product Register, Shift Multiplier register to next bit The time required for the multiplication: T MULT = T SETUP +N T ITER ECE152B AU 24

T SETUP : the time required to clear the product register & load the multiplier. T ITER : the time required to created the partial product, to add the partial product to the running sum, and to load the resulting value into the product register. T ITER = T AND +T SUM +T REG ECE152B AU 25