Synaptic Labs' HyperBus Memory Controller (HBMC) Tutorial T001: A Qsys based Nios II Reference design with HelloWorld test running in HyperRAM device using S/Labs' HBMC IP This tutorial describes a simple reference design for S/Labs HBMC IP targeted specifically to Intel Cyclone 10LP evaluation board or devboards GmbH HyperMAX 10M25 and 10M50 boards. Most HBMC customers using any of these boards board will want to start with this tutorial. This tutorial describes key aspects of how to configure a.qsys reference project and then walks through the process of generating and compiling that.qsys project. This tutorial then describes how to compile the example Nios II source code, integrate the firmware into the FPGA bitstream and then run the reference design on the development board. page 1
Table of Contents Set-Up Requirements:...4 1. Create Quartus Prime Hardware Design Project...6 1.1: Install S/Labs' HBMC Qsys Component into the project IP Folder...8 2. Create Qsys/Nios II processor design...9 3. Creating the reference Qsys project...10 3.1 Adding Components to the reference project...10 3.2 Adding S'Labs Hyperbus Controller IP...11 3.3 Adding Nios II Embedded processor...13 3.4 Adding Avalon-MM Pipeline Bridge...14 3.5 Adding Jtag Uart...15 3.6 Adding PIO Led connection...16 3.7 Wiring the core components...17 3.8 Configuring the Nios II processor...21 4. Generating the Qsys Design...22 5. Completing the Quartus project...23 5.1 Adding Files to the Quartus Project...23 5.2 Settings the pin locations and pin constraints...25 6. Preparing the firmware...28 6.1 Open the NIOS II Software Built Tools for Eclipse...28 6.2 Create a simple application and BSP...29 6.3 Configure the Board Support Package (BSP)...31 6.4 Generate the BSP and clean the project...35 6.6 Build the Nios II Application...35 7. Program the FPGA Bitstream into the FPGA device...36 8. Run the HelloWorld application from within Nios II SBT...37 page 2
Set-Up Requirements: Step 1: Obtain core materials 1. Download and install Quartus Prime Standard/Lite 17.0 on your PC, please ensure that your PC meets the required minimum specification. 2. For Intel's C10LP Evaluation board : Create a folder/directory for your work. We suggest: C:\C10_lab\ Download reference design HelloWorld_Project_C10LP_final from: http://media.synaptic-labs.com/pub/2017-designs/synapticlabs-hbmc-tutorial-001 /HelloWorld_Project_C10LP_final.zip Extract to: C:\C10_lab\ This zip file contains a full working example of the Quartus project as described in this tutorial. These files and folder may act as reference when building this project. 3. For devboards HyperMAX board : Create a folder/directory for your work. We suggest: C:\HyperMAX_lab Download reference design HelloWorld_Project_HM10M25_final from: http://media.synaptic-labs.com/pub/2017-designs/synapticlabs-hbmc-tutorial-001 /HelloWorld_Project_HM10M25_final.zip Extract to: C:\HyperMAX_lab\ page 3
Step 2: License Setup 1. Next you need to apply for Synaptic Labs' HyperBus Memory Controller license. You can skip this step if you already installed the license at some earlier stage. Free enrollment can be obtained from: http://opencore_license_001.synaptic-labs.com/ 2. Synaptic Labs offers two Installation Guides that: a. Begin by preparing you to enroll to receive a Basic Edition (OpenCore) license b. Guide you on how to install the license file you will receive after enrolment c. Guide you on how to install the Qsys components that you will receive after enrollment 3. Please download and read one of those Installation Guides: a. Developers familiar with installing third party IP into Quartus will probably prefer the streamlined: HBMC IP Installation Guide for Experience Developers. b. All other developers should download the: HBMC IP Installation Guide with Detailed Step-by-Step Instructions. page 4
1. Create Quartus Prime Hardware Design Project Synaptic Labs' HyperBus Memory Controller (HBMC) Reference design projects includes the following files and directories: Now you are going to create a Quartus Prime project with a setting for the Cyclone 10 LP device on the board. If not already open, start the Quartus Prime software by double-clicking on the icon on the desktop From the top menu select, File -> New Project Wizard and select Next page 5
Enter the path to the folder you created and a project name. We suggest a path of C:\C10Lab\ and project name of HelloWorld_C10LP HelloWorld_Project_C10LP HelloWorld_Project_C10LP Select Next If prompted, allow the tool to create a new folder Select Empty project. Select Next. Add files Select Next. Device -> Select: Family: Cyclone 10 LP Device: 10CL025YU256I7G You can use the filters to make this easier Package: UFPGA Pin Count: 256 Speed grade: 7 Or use the name filter Select Finish The Quartus Prime project is now ready to build an IP system and compile the project. The HyperMAX 10M25 board employs the 10M25DAF256C7G device. The HyperMAX 10M50 board employs the 10M50DAF256I7G device. The Intel C10LP Evaluation board employs the 10CL025YU256I7G device page 6
1.1: Install S/Labs' HBMC Qsys Component into the project IP Folder 1. In this tutorial we assume that S/Labs HyperBus Memory Controller (HBMC) will be located in the Project directory. a. Other Qsys component installation methods are described in the above mentioned installation Guides. 2. Download the latest version of Synaptic Labs' HBMC IP from: http://media.synaptic-labs.com/pub/softip/latest_sll_ca_hbmc_001_be_cots.zip 3. For Intel's C10LP Evaluation board : Create a new folder inside the project directory. Name this folder ip Extract to the project/ip directory : C:\C10_lab\HelloWorld_Project_C10LP\ip 4. For devboards HyperMAX board : Create a new folder inside the project directory. Name this folder ip Extract to the project/ip directory : C:\C10_lab\HelloWorld_Project_HM10M25\ip page 7
2. Create Qsys/Nios II processor design Now you will build a basic system using the Qsys tool. The system will contain: Nios II /f CPU Synaptic Labs' HyperBUS memory controller IP JTAG UART peripheral PIO (connected to LED) You will need a license for the Hyperbus memory controller to build the system, if you haven t installed the license please refer to the setup section at the beginning of this tutorial. In essence, you will be building a system that looks like this: Nios II SLL HBMC IP Jtag Uart Avalon-MM Bridge PIO This system will have a processor and a minimal number of standard embedded peripherals that enable it to run and communicate/interact with the outside world. Throughout this lab as we add components, it can make things easier to read and check connectivity if you re-order the components. The screenshots provided may be organized to make the connections more obvious, but do not have to be ordered that way. Once the hardware is built you will create a simple software project from a template and run it on the board. page 8
3. Creating the reference Qsys project In the menu bar of Quartus Prime, select Tools Qsys Save the Qsys project. Select File Save as Type hypernios.qsys as the file name Click Save 3.1 Adding Components to the reference project The reference Qsys project in this tutorial employs a NiosII/f processor, Synaptic Labs' HyperBus Memory Controller (HBMC) IP, and various peripherals such as Altera s JTAG UART as illustrated below. All these Qsys components are connected together. page 9
3.2 Adding S'Labs Hyperbus Controller IP Locate and select Synaptic Labs' Hyperbus controller component in the IP Library. This can be found at Library Synaptic Labs Memory Hyperbus S/Labs HyperBus Memory Controller The configuration wizard will open. page 10
In the "Master Configuration" tab The open-core edition of SLL HBMC IP only supports HyperRAM. The full edition of SLL HBMC IP supports any combination of HyperFlash and HyperRAM. Both editions offer preconfigured memory options for supported COTS FPGA development boards. The full edition of SLL HBMC IP also includes the option to manually configure the HyperBus devices. To configure the project to just use HyperRAM on the Intel C10LP/HyperMAX board: The FPGA board type field is set to either: Devboards - HyperMAX 10M25 (HyperRAM) or Devboards - HyperMAX 10M50 (HyperRAM) or Intel Cyclone 10LP Evaluation Kit (HyperRAM) To configure the project to use both HyperFlash and HyperRAM on the HyperMAX board: The FPGA board type field is set to either: Devboards - HyperMAX 10M25 (HyperFlash and HyperRAM) or Devboards - HyperMAX 10M50 (HyperFlash and HyperRAM) Currently, Intel's Cyclone 10LP evaluation board does not contain a HyperFlash device. S/Labs recommends using the HyperRAM only configuration if this is your first time through the tutorial. Leave everything as default and click Finish to add the IP to the system contents. reported error messages. Ignore any page 11
3.3 Adding Nios II Embedded processor Locate and select the Nios II processor in the IP Library, this can be done by entering Nios in the search bar and double clicking on the Nios II processor. The configuration wizard will open. Select the Nios II/f core and click on FINISH Once completed there will be some red Error messages in the Qsys messages tab, these are caused by the Nios II IP requiring settings for system memory; we will set these correctly after wiring the design page 12
3.4 Adding Avalon-MM Pipeline Bridge Locate and select the Avalon-MM Pipeline Bridge in the IP Library, this can be done by entering Bridge in the search bar and double clicking on the Avalon-MM Pipeline Bridge. This step is important so that we will be able to connect any peripherals to the Nios II processor over this bridge, while keeping the interconnect resources to a minimum. Tick [x] Use automatically determine address width. Leave everything else as default. Click on FINISH page 13
3.5 Adding Jtag Uart Locate and select the JTAG_Uart in the IP Library, this can be done by entering Uart in the search bar and double clicking on the JTAG_Uart. Select a Buffer depth of 1024 bytes as shown above. Leave everything else as default. Click on FINISH page 14
3.6 Adding PIO Led connection Locate and select the PIO (Parallel IO) in the IP Library, this can be done by entering Pio in the search bar and double clicking on the PIO (Parallel IO) component. For now you just want to drive the 4 LEDs on the board, so set for 4 bit width and select Output direction. Leave everything else as default. Click on FINISH page 15
3.7 Wiring the core components Input Clock source connections The Clock Source component is required in every Qsys system and can provide the clock and reset signal. The clock from this IP block will be the 50MHz clock coming into the Cyclone 10 device from the oscillator on the board; you will connect this into the clock input of S/Labs Hyperbus Controller (in_clk ) component. connect up the clk signal of the clock source to the clock input of S/Labs Hyperbus Controller (in_clk ). connect up the clk_reset of the clock source to the reset input of S/Labs Hyperbus Controller (i_ext_rstn ). Avalon Clock/Reset source connections S/Labs HBMC component contains an internal PLL. This will generate an output clock (o_av_out_clk) and and output reset (o_av_out_rstn) to drive all components in the Qsys system. The frequency on this clock can be configured in S/Labs HBMC IP directly. Connect S/Labs Hyperbus Controller o_av_out_clk Clock output to the clk (clock) inputs on the Nios II processor, Avalon pipeline bridge, JTAG UART and PIO components. Connect S/Labs Hyperbus Controller o_av_out_clk Clock output to the i_iavs0_clk (clock) input on S/Labs Hyperbus Controller. The o_av_out_clk signal connection is shown in red in the figure below. Connect S/Labs Hyperbus Controller o_av_out_rstn Reset output to the reset (reset) inputs on the Nios II processor, Avalon pipeline bridge, JTAG UART and PIO components. Connect S/Labs Hyperbus Controller o_av_out_rstn Reset output to the i_iavs0_rstn (Reset) input on S/Labs Hyperbus Controller. The o_av_out_rstn signal connection is shown in blue in the figure below. Nios II debug reset source connections When the debugger resets the Nios II processor, it is good if the rest of the system resets as well. So you should also connect the Nios II debug_reset_request (reset Output) to the rest inputs of the other components. The Nios II debug_reset_request signal connecttion is shown in green in the figure below. Do not connect the Nios II debug reset to S/Labs Hyperbus Controller (i_ext_rstn) reset input. page 16
NIOS II Avalon Instruction, Data master connections Connect the Nios II Avalon Instruction Master to S/Labs HBMC Avalon-MM Slave (iavs0) and Nios II debug_mem_slave. Connect the Nios II Avalon Data Master to S/Labs HBMC Avalon-MM Slave (iavs0), Nios II debug_mem_slave and Avalon pipeline bridge slave (s0). Avalon-MM bridge master connections Connect the Avalon-MM pipeline bridge Master to the avalon_jtag_slave (Avalon Memory Mapped Slave) port on the JTAG UART. Connect the Avalon-MM pipeline bridge Master to the s1 (Avalon Memory Mapped Slave) port on the PIO component. Nios II interrupt connections Finally, you need to connect the irq (interrupt sender) of the JTAG UART to the Nios II processor so that the UART can interrupt the Nios II processor when required. Your system should now look like this: page 17
All of the connections made so far are internal to the system. This is done by double clicking on the Conduit connections in the export column. This makes the signals visible externally at the top level of the generated Qsys system. Once visible they can then be connected to external pins or other system modules You need to connect the conduit signals of S/Labs HBMC component and connect them to the external pins of the Cyclone 10 device. Double clicking on the Conduit connections in the export column. You need to connect the outputs of the PIO component and connect them to the external pins of the Cyclone 10 device. Double clicking on the Conduit connections in the export column. page 18
Assigning base addresses Now you need to correctly set all the base addresses of each component in the memory map. In this example, we are setting the HyperRAM memory base address to 0x0. In the Base column, double click on S/Labs HBMC Avalon MM Slave. Set the respective field to 0. Click on the lock icon to lock this memory region and prevent it from being changed when automatically assigning base addresses. Lock icon Next, we need to set all the base addresses of each component in the memory map Fortunately, Qsys provides a mechanism for automatically assigning all the component base addresses and correctly building the Nios II memory map. Go to the Qsys menu and select System Assign Base Addresses. You can do the same for assigning the IRQ interrupt numbers. Go to the Qys menu and select System Assign Interrupt Numbers. page 19
3.8 Configuring the Nios II processor In this example, the Nios II/f Reset and Exception vectors are mapped to the HyperRAM as illustrated below. This means that the Nios II/f processor will look for the boot code and exception handling / interrupt code in the HyperRAM memory. As illustrated below, the instruction and data caches of the Nios II/f core have both been set to 4Kbytes in size to accelerate software performance. The instruction and data caches have both been configured with their burstcount signal enabled so that both caches issue burst memory transfer requests. This is done because: (a) the HyperBus protocol employs burst memory transfer requests with closed page mode of operation; and (b) SLL s HBMC employs an Avalon interface with burst mode of operation. page 20
4. Generating the Qsys Design Once the Qsys project has been correctly configured, press the [ Generate HDL ] button on the bottom right hand side of the Qsys window. In the Synthesis section, set the Create HDL design files for synthesis field to Verilog. In the Simulation section, set the Create simulation model field to None. Then click on the [ Generate ] button. You may see a Save System window. Click the [ Close ] button to close the save window. This should take a minute or so to complete. There maybe a few warnings but we can ignore these for now. Generating the.qsys project updates the.sopc file which will be used by the Nios II Software Build Tools (SBT) environment. Click the [ Close ] button to close the generate window. You may want to close the Qsys window. page 21
5. Completing the Quartus project You should get an information window stating that you need to add the.qip/.sip files (just generated by Qsys) to your project. (With newer versions of Quartus Prime you have to manually add the.qip file Qsys has just generated into the files list). This ensures that Quartus Prime builds the design correctly, and if later on you update and re-generate the Qsys system then Quartus Prime will automatically recognize this and rebuild as required. Select OK to close the dialog box. On the top level menu select 5.1 Adding Files to the Quartus Project Project-> Add/Remove Files in Project Click on the Browse button and select the hypernios.qip file (C:\C10Lab\HelloWorld_Poject_C10LP\hypernios\synthesis). Double click on the file or select Open to add the file to the list. Close the settings dialog window by clicking on OK You have now used Qsys to create an IP module that contains a Nios II processor and small peripheral set. Now you need to add this IP module into the Quartus Prime top-level file just as you would have to with any other module or block of RTL. This is normally created manually, you can copy the top-level entity/architecture from the generated QSys top-level file. Hint: If you want to create your own top level file Qsys has already created much of what you need; browse to HelloWorld_Poject_C10LP\hypernios\synthesis and open hypernios.vhd or hypernios.v. In this file, you will see the entity declaration for the Qsys IP module which you can then cut/paste into the top level file. page 22
To save time we have created a simple top-level project file; this files creates the top-level, instantiates the QSys IP component and maps this instantiation to top level signals. Copy the file NIOS_HyperRAM.vhd from the HelloWorld_Project_C10LP_final reference design folder. (C:\C10Lab\ HelloWorld_Project_C10LP_final \) into the Quartus Prime project folder C:\C10Lab\HelloWorld_Project_C10LP\). In Quartus Prime, on the top level menu select Project-> Add/Remove Files in Project Click on the Browse button and select the NIOS_HyperRAM.vhd file. Double click on the file or select Open to add the file to the list. The file should now appear in the Project Navigator->Files window. Double click on it or use File->Open to view the file in the editor. Review the contents of the file. Everything is now in place, but Quartus Prime needs to know what to build. Go to the Project Navigator and select Files from the drop-down list. Right click on the file NIOS_HyperRAM.vhd and select Set as Top-Level Entity page 23
5.2 Settings the pin locations and pin constraints For this lab, your top-level design has four types of signals defined: Clock (input) Reset (input) 4 LEDs (outputs) HyperRAM deive signals To get this design really working on the board you need to define how these signals should be connected to the FPGA pins From the schematics of the Cyclone10 LP evaluation board you can see that: The c10_clk50m is a 50MHz reference clock on the board (recall you set this when you configured the PLL within QSys). From the schematic this pin is E1. The c10_resetn signal is connected to pin J15 of the FPGA. the 4 LEDs on the board are connected to 4 pins on the FPGA: o user_led3 connects to pin J13 o user_led2 connects to pin J14 o user_led1 connects to pin K15 o user_led0 connects to pin L14 the HyperRAM signals are conneced to the following pins on the FPGA Pin Name on Board hbus_dq[0] hbus_dq[1] hbus_dq[2] hbus_dq[3] hbus_dq[4] hbus_dq[5] hbus_dq[6] hbus_dq[7] hbus_cs2n hbus_rstn hbus_rwds hbus_clk0p hbus_clk0n Pin location on FPGA T12 T13 T11 R10 T10 R11 R12 R13 P9 N9 T14 P14 R14 Pin IO Standard 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V page 24
You can make these connections in Quartus Prime in a number of different ways, but one of the easiest is via a graphical tool called the Pin Planner. From the Quartus menu, select Assignments Pin Planner you should then see the following window: In the middle of the screen you can see a physical view of the FPGA pins on the U256 package. At the bottom of the screen you can see the pins that Quartus Prime has identified in our design from the top level design file, namely Clk, Reset, LEDs, Hyperbus Signals etc (you may also see 4 pins for the JTAG interface but you can ignore these). You can see that Quartus Prime may already assigned these pins (Fitter location), you now need to edit each of these signals and assign them correctly in the Location column. page 25
Once you have assigned the pins close the pin planner and re-build the project. Go to the Quartus menu and select Processing -> Start Compilation, OR go to the button toolbar and click on the start compilation button Once the build is complete you will have a sof file in the output folder: C:\C10Lab\HelloWorld_Poject_C10LP\output_files\c10Lab_time_limited.sof This file will be used to configure the FPGA on the development board for the next exercise. page 26
6. Preparing the firmware 6.1 Open the NIOS II Software Built Tools for Eclipse In Quartus Prime, go to the menu bar and select Tools NIOS II Software Built Tools for Eclipse. Click the [Browse ] button. A new file selector window will open. In this tutorial we are going to select the software folder located inside the project folder as the workspace. Create a software folder incide the Quartus project. Then click the [ OK ] button. Be sure to leave the [ ] Use this as the default field unticked. Click the [ OK ] button. page 27
6.2 Create a simple application and BSP The software folder in the reference project is empty. This is because problems can be experienced when moving the Eclipse Workshop folder between Windows and Linux Systems. We need to create a Nios II application, and Nios II board support package for that Nios II application: In the Eclipse window, go the menu bar and select: File New NIOS II Application and BSP from Template A new window will pop up: (most of the fields below will initially be empty) hypernios.sopcinfo page 28
In the Target hardware information, click on the [ ] button A file browser window will open. Locate and select the hypernios.sopcinfo file generated by Qsys and stored in the project directory. Click [Open]. It may take around 30 seconds for the Eclipse application to parse the.sopcinfo file. Select a Project name. In this example, we are using HelloWorld as the project name. Ensure that: [x] Use default location is ticked. We now need to select a template from the Project Template list. In this example, select the Hello World template. Press the [ Finish ] button to complete the current step. The Nios II SBT will now generate: a HelloWorld application folder that contains the hello_world.c file. a HelloWorld_bsp folder that contains the Nios II Board Support Package (BSP) hardware abstraction layer (HAL). page 29
6.3 Configure the Board Support Package (BSP) The Nios II BSP must be configured before we can compile the source code. In the Project Explorer tab, right click on: HelloWorld_bsp Nios II -> BSP Editor... page 30
In the Main Tab of the BSP editor, in the panel on the left hand side, select: Settings Common Leave the sys_clk_timer field to none This is used to generate a recurring system clock interrupt for the hardware abstraction layer. Leave the timestamp_timer field to none This field is used to enable the hardware abstraction layer to perform fine precision timing. The Newlib ANSI C standard library can be configured as small or normal Generally, when mapping code and data to on-chip memory: Tick the [x] Enable small C library field to reduce the size of the executable code generated by the hardware abstraction layer (HAL). Ticking this option also reduces the functionality and performance of the HAL. Please note that the inbuilt memset() and memcpy() routines will be very slow. Generally, when mapping code and data to HyperRAM and/or HyperFlash: Untick the [ ] Enable small C library field to increase the functionality and performance of the executable code generated by the hardware abstraction layer (HAL). The inbuilt memset() and memcpy() routines will achieve good performance. However, the executable code will be considerably larger. We recommend the UnTick the [ ] Enable small C library for this specific tutorial. page 31
In the Main Tab of the BSP editor, in the panel on the left hand side, select: Settings Advanced hal.linker For the purpose of this tutorial, the following configuration will generally work: Tick [x] allow_code_at_reset Tick [x] enable_alt_load Tick [x] enable_alt_load_copy_rodata Tick [x] enable_alt_load_copy_rwdata Tick [x] enable_alt_load_copy_exception UnTick [ ] enable_exception_stack However, this specific configuration may not be the best configuration for your project s needs. Please refer to Altera s documentation for detailed information on how to setup the hal.linker fields: Generic Nios II Booting Methods User Guide, UG-20001, 2016.05.24 https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/niosii_generic_booting_methods.p df page 32
Select the Linker Script Tab of the BSP editor. For this tutorial example, we are going to: Map the reset vector (.reset) to the HyperRAM ( sll_hyperbus_controller_top_0. This is generated by Qsys and depends on the location of the Nios II reset vector. Map the exception vector (.exceptions) to the HyperRAM (sll_hyperbus_controller_top_0). This is generated by Qsys and depends on the location of the Nios II exception vector. Map the instruction code (.text) in the HyperRAM (sll_hyperbus_controller_top_0) Map all other data regions (.bss,.heap,.rodata,.rwdata,.stack) to the HyperRAM (sll_hyperbus_controller_top_0) This will map all memory regions generated by the GCC tools to the HyperRAM memory. For more information see: Nios II Gen2 Software Developer's Handbook, NII5V2Gen2, 2017.05.08 Section 5, Nios II Software Build Tools https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/nios2/n2sw_nii5v2gen2.pdf Now: Click on the [ Exit ] button on the bottom right hand corner of the BSP Editor window. Then click on the [Yes, Save] button on the Save Changes window to save the BSP settings. page 33
6.4 Generate the BSP and clean the project The software developer must re-generate the BSP every time the Qsys project is regenerated. This ensures that the device drivers and addresses of peripherals are reflected correctly in the hardware abstract library. To (re)generate the BSP: Go to the Nios II eclipse window. Right click on HelloWorld_bsp project then select Nios II then select Generate BSP. Right click on the HelloWorld_bsp project then select Clean Project to delete any intermediate files generated by the gcc compiler for this application library. Right click on the HelloWorld project then select Clean Project to delete any intermediate files generated by the gcc compiler for this application folder. 6.6 Build the Nios II Application We now want to run the compiler and linker: Go to the Nios II eclipse window. Go to the menu bar and select: Project ->Build All If the project produces warning / error messages, you may need to build the project twice. The HelloWorld executable firmware (.ELF) is now generated. The.ELF can be downloaded directly into HyperRAM using the Nios II Debugger. page 34
7. Program the FPGA Bitstream into the FPGA device Connect the HyperMAX/Intel C10LP Evaluation kit to the USB port of your computer Open the Quartus Prime window In the menubar, click on Tools then Programmer to start the Altera Programmer Click on Hardware Setup. A new window will open. Double Click on the HyperMax (or Intel C10LP Evaluation kit) device, then click the [ Close ] button. If the NIOS_HyperRAM_time_limited.sof is not already selected: Click Add File... in the programmer window. Go to the output_files folder Double click on NIOS_HyperRAM_time_limited.sof Click the [ Start ] button and the FPGA bitstream will be programmed into the SRAM configuration memory of the FPGA device. A window called OpenCore Plus Status should open. page 35
8. Run the HelloWorld application from within Nios II SBT Select the Nios II Software Built Tools for Eclipse window. Right click on Benchmark Run As Run Configurations... page 36
A new window will open Make sure the Project name: field says HelloWorld. Select the Target Configuration tab. Press the [Refresh Connection] button to detect the Nios II processor. Tick the [Ignore mismatched System ID] field. Tick the [Ignore mismatched System timestamp] field. Press the [ Run ] button to download the firmware from the desktop and copy it directly into HyperRAM and then run the firmware from HyperRAM. Messages similar to the one below are displayed in the Nios II Console Window. page 37