General Objective: Determine the hardware requirement of a digital computer based on its instruction set. Specific Objectives: Describe the general concepts in designing the data path of a digital computer from its instruction set. Design the data processing elements such as the arithmetic circuits, counters and registers. Design data routing circuits that transport data to various processing elements. Draw the interconnections of the various elements. 1
General concepts in designing the data path of a digital computer from its instruction set. Instruction Set Mnemonic OpCode LDA ADD 1 SUB 1 OUT HLT 11 1111 Description Load ACC with the contents of the memory specified address. Add the contents of the ACC with the contents of the B register and place the result in the ACC. SUBtract the contents of the B register from the ACC and store the result in the ACC. OUTput he contents of the ACC to the OUTR register. Halt or stop MSAP. Instruction Format D7 D6 D5 D4 OPCODE D3 D2 D1 D OPERAND 2
Extracting hardware requirements from the Instruction Set 1. Starting with the arithmetic instructions, ADD and SUB, ADD M[address] and SUB M[address] which mean add (subtract) the contents of the memory specified in the instruction from the contents of the accumulator and store the results to the accumulator. Symbolically, ACC <= ACC + M[address] or ACC <= ACC - M[address] one addend (minuend) is already in the ACC, while the other addend (subtrahend is found in the memory. It is typical that the data read from the memory is stored in a temporary register. This will lead to a configuration below; ACC ACC + TMP TMP 3
combining the add and subtract operations, ACC +/TMP su The addition or subtraction operation is selected by su. When su =, add operation is performed. when su = 1, subtraction is performed. 4
2. Memory Operation. Data manipulated by the arithmetic operations are stored in the memory. Accessing the memory requires two signals; the address signal which specifies the location of the data in the memory, and the rd control signal which specifies the exact time data is outputted by the memory. The address must be constantly applied to the memory during the entire memory read cycle. This necessitates the use of a register to hold the address, thus it is named the Memory Address Register (MAR).The size of MAR is equal to the number of address bits. Symbolically, memory read operation is represented as, rd : REG <= M[MAR] Memory Unit (2N x M MAR N Address Data out M REG rd 5
3. Sequencing of memory access. The memory contains both sequences of instruction codes (computer program), and operands (data to be manipulated by the program). The instruction code must be first read (fetched) from memory, decoded, and the memory is read again to get the operand (operand fetch). Processing of data then can be carried out (executed), in the processing elements. The type of processing ( arithmetic) is indicated by the instruction code. Thus, the computer cycles between operation code and operand fetch cycle (opcode and operand fetch), and the execute cycle. To keep track of the instruction code to be fetched next from memory, a Program Counter (PC) is used to always point to a memory address containing the next instruction code to be fetched. PC Memory Unit (2N x M) opcode/ operand fetch cycle EXecute Cycle MAR N Address Data out M rd 6
4. Fetch Cycle and Operand Fetch During the OpCode Fetch, the instruction code is read from memory and then stored in a special register called as the Instruction Register (IR). During the operand fetch, the address of the operand is stored in MAR in preparation to read the data from memory. Generally, data read from memory during operand fetch is stored in a general purpose register (example, the ACCumulator register). PC PC Memory Unit (2N x M) MAR N MAR Address Data out rd Memory Unit (2N x M) M IR N Address Data out M ACC rd 7
5. To support Data Transfer Operations, registers should have the capability to receive data in parallel (parallel load). The load control input when active enables the data at the data inputs to be loaded in parallel on the next clock pulse. Din Load clk Dout 8
6. Data Transfer Operations. To support instructions that moves data between registers (to support arithmetic operations), various registers must be organized (interconnected) to facilitate the transfer of data. Data Routing Circuits, route data from source registers to the inputs of all registers. Source registers are selected by multiplexers and the target register is selected by a decoder. DECODER MXN 1 destination select 2 N N - 1 MUX Reg Reg1 1 Reg2 2 RegN N Y source select 9
Summary: the instruction set of a digital computer defines the set of operation its datapath can support. instructions defines the characteristics and capabilities of the processing elements of the datapath. arithmetic instructions such as addition and subtraction can be implemented using adder and subtractor circuit. registers are provided to hold data needed by arithmetic circuits. computer cycles involve the fetch cycle and the execute cycle. registers are organized to facilitate transfer of data to required parts of the system. 1
Control Unit Reset Control Signals Combinational Network Memory (State) 11
Reset Control Unit Datapath Combinational Network (Binary Multiplier) Memory (State) 12
Reset Control Unit Datapath Combinational Network General Purpose Processor Instruction Set Architecture Complex Instruction Set Computer Direct Addressing Mode Memory (State) 13
(General Data Processor): Fetch Cycle Control Unit Reset Combinational Network Memory (State) Datapath IR PC Memory 14
(General Data Processor) : Execute Cycle Control Unit Reset Combinational Network Memory (State) Datapath IR PC Memory ACC TMP Processing Elements +/su 15
(General Data Processor) : Execute Cycle Control Unit Reset Combinational Network Datapath IR PC Data Routing circuits Memory (State) Memory ACC TMP Processing Elements +/su 16
Simple As Possible Computer (SAP) 17
Simple As Possible Computer (SAP) MEMORY 18
Simple As Possible Computer (SAP) Fetch Cycle Elements 19
Simple As Possible Computer (SAP) Processing Elements (EXecute Cycle) 2
Simple As Possible Computer (SAP) Data Routing Circuits 21
Parts of a Digital Computer Control Unit Memory Unit Central Processing Unit InputOutput Unit 22
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Read Only Memory 24
Memory Address Register 25
2-1 MULTIPLEXER 26
ALU -Arithmetic Logic Unit 27
Adder/Subtractor Circuit 28
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8-BIT REGISTERS 3
8-BIT REGISTER TIMING 31
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clrpc incpc dessel srcsel rd su 1 ' ' PC CLEAR PC or reset ' ' MAR PC PC to MAR 1' 1' 1 IR M[MAR] MEMORY TO IR (opcode fetch) 1 ' ' PC PC + 1 INCrement PC ' 11 MAR IR[3:] IR TO MAR Transfer operand 1' 1' 1 A M[MAR] MEMory to ACC memory read to A 1' 1' 1 B M[MAR] MEMory to B memory read to B 1' 1' A A+ B ALU to ACC (addition) 1' 1' 1 A A- B ALU to ACC (subtraction) 11' 1' OUTR A ACC to OUTR Micro operations Description 35
clrpc incpc dessel srcsel rd su Hexcode Micro operations RESET 1 ' ' 2 PC Fetch Cycle ' ' ' MAR PC 1 1' 1' 1 186 IR M[MAR], PC PC + 1 LDA ' 11 1' MAR IR[3:] 1' 1' 1 26' A M[MAR], goto Fetch ADD ' 11 1' MAR IR[3:] 1' 1' 1 46' B M[MAR] 1' 1' 3' A A + B, goto Fetch SUB ' 11 1' MAR IR[3:] 1' 1' 1 46' B M[MAR] 1' 1' 1 31' A A - B, goto Fetch OUT 11' 1' 68' OUTR A, goto Fetch HLT ' ' ' enstate 36
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Designing the Simple As Possible Computer Control Unit Memory Unit THANK YOU Central Processing Unit InputOutput Unit 38