Dierential I DDQ Testable Static RAM Architecture Walee K. Al-Assai Anura P. Jayasumana Yashwant K. Malaiya y Technical Report CS-96-102 February 1996 Department of Electrical Engineering/ y Department of Computer Science Colorao State University Fort Collins, CO 0523
Dierential I DDQ Testable Static RAM Architecture W. K. Al-Assai, A. P. Jayasumana, an Y. K. Malaiya y Electrical Engineering Department y Computer Science Department Colorao State University Fort Collins, CO 0523 Abstract A testable esign that enhances the I DDQ testability of ranom access memories (SRAMs) for o-line testing is propose. Increase accuracy an test spee can be achieve by memory array partitioning. Comaparision of I DDQ values from two blocks is performe uring parallel write/rea operations to memory locations of the two blocks. Simultaneous write/rea operations to all locations within physically interleave block can signicantly enhance the test spee as well as fault activation. 1 Introuction With the increasing complexity of semiconuctor memories, the nature of the failure moes have become more complex an subtle [1, 2]. Failure moes such as gate-oxie shorts, briging efects, parasitic transistor leakage, efective p-n junctions, an transistors with incorrect threshol voltages, o not aect the logical behavior. Such faults may pass the functional an logical testing, but may malfunction overtime, causing reliability hazars. Many of those faults cause elevate quiescentpower supply current(i DDQ ), whichistypically several orers of magnitue greater than the I DDQ of a fault-free evice. In static ranom-access memories (SRAMs), most of the I DDQ testable faults are activate uring the write/rea cycles [3, 4, 5, 6]. In [3], an analysis of the eectiveness of the I DDQ testing has been one using SRAM of K X -bit wors manufacture by Philips, using Inuctive Fault Analysis technique. The results show that a high fault coverage is achieve when I DDQ testing is performe in combination with functional testing. In [7], experimental results were reporte on eploying current testing to etect efects that cause ata retention This work was supporte partly by a BMDO fune project monitore by ONR.
problems. The iea of I DDQ testing is expane for fault localization in [6]. In [], a testable SRAM structure was propose for observing the internal switching behavior of the memory cells. The propose structure provies a high coverage of isturb-type pattern sensitive faults. In [4], the etaile fault moel of the 6-transistor memory cell was investigate for possible transistor level faults. It was shown that intra-cell efects can cause inter-cell faults in the memory array, such as coupling faults. Such faults were shown to cause elevate I DDQ when activate. In [5] a testable esign for memory array was shown to enhance I DDQ testing by allowing parallel access to the whole memory cells uring the write cycle. The above work clearly establishes the promise of I DDQ testing for SRAMs. However, it oes not establish testability requirements that can improve the eectiveness of current testing. In aition the above work oes not aress the problem of current measurements an the eects of the size of the circuit uner test on the accuracy an testing spee. In this paper, we propose a testable scheme for o-line testing that enhances the I DDQ testability for CMOS SRAMs. The propose scheme partitions the memory arrayinto ientical partitions each with its own operational groun noe (GND(O)). Quiescentpower supply currents can be monitore uring parallel access of locations or subset of locations (blocks) of each partition. Test spee is enhance by comparing currents in the two partitions using a built-in current comparator (BICC). This paper is an extension of the ierential concept propose in [9]. In that work, a testable esign for a wor-organize SRAM architecture, which is a special case of SRAMs, was presente. 2 Dierential I DDQ Testing of SRAMs The propose scheme is intene to minimize the impact of the conventional built-in current sensor (BICS) circuit on spee testing, by using a current comparator. The memory array is partitione physically into ientical partitions each with its own operational groun noe (GND(O)). The partitioning is one uring the esign phase. The number of partitions epen on the size of the memory array. In most SRAM architectures, bits are physically separate such that iniviual bits belonging to several logical wors may resie on a segment on the same chip, i.e. a segment i hols bit i of each wor. Hence a partition in Figure 1 may represent a segment or several segments of the same chip, connecte to a certain GND(O) noe. GND(O) noes are use uring normal operations, thus bypassing the current comparator. During the test moe, the GND(O) noes are open, an the test groun GND(T) noe (groun noe of the current comparators) will be the common groun noe for the circuit, i.e. the tester will consier GND(T) as the groun noe. Ientical partition sizes imply similar groun line capacitance values for each partition. A built-in current comparator (BICC) is use to compare the quiescent power supply
currents of two partitions uring the testing moe while accessing their locations simultaneously. A sensor similar to the Dierential BIC (D-BIC) propose in [10] may be use as the BICC. With the D-BIC, testing is performe in two phases. The circuit is partitione into two ientical parts CUT1 an CUT2. Test vectors are applie to CUT1 an the current is compare to a reference current value in one phase. Then in the secon phase, CUT2 is similarly teste. When using BICC, testing is performe in one phase, such that if the ierence between the currents of two partitions (e.g. ji1-i2j in Figure 1) excees a suitably chosen I th, the ag line is raise inicating a fault. If several BICCs are use, the ag signals can be connecte to an OR gate to generate apass/fail signal. If the ierence is less than I th, no fault is etecte. However, this may occur in case of faults riving similar currents in each partition. To overcome this problem, each partition can be ivie into blocks. A block is a subset of contiguous or interleave memory locations. Testing can be employe by simultaneously accessing two ientical blocks, each belonging to a separate partition. Reucing the size of the accesse array will allow the resolution to be maintaine. In aition, reucing the size of the partition will ensure that leakage currents will not a up to the point where they become comparable to the abnormal quiescent current expecte of a fault. Therefore the accuracy an testing spee is expecte to improve signicantly. VDD Chip bounary Partition 1 Partition 2 Partition (i-1) Partition (i) Block Block Block Block GND(O) I I I 1 2 i I i+1 GND(O) C Current Comparator C C Current Comparator C I th GND(T) Flag Flag GND(T) I th GND(O) GND(O) Pass/Fail GND(O): Operational Groun Noe GND(T): Test Groun Noe Figure 1: Principle of I DDQ comparison
3 Partitioning an Decoer Design In this section we propose a I DDQ testable esign for a SRAM architecture. Physical separation of the bits reuces the likelyhoo of an alpha particle erasing more than one bit of a logical wor, thus allowing eective single-bit error correction an enhances reliability. In this work we assume the the architecture shown in Figure 2. When the logical wor length is `' bits, the memory array is compose of `' of segments. Each segment hols one bit of each logical wor. A segment ecoer is require to route input ata to ierent segments. Data in 0 1 Data-in register Segment ecoer Bit rivers Bit rivers Bit rivers W 0 W1 Aress lines 0 1 bit 0 of all logical wors S 0 bit 1 of all logical wors bit of all logical wors S 1 S W p Decoer lines Bit rivers an sense amplifiers Output register Data out Figure 2: A SRAM Architecture ToachieveaI DDQ testable scheme with high test accuracy an spee with small harware overhea, esign moications are require to meet three basic goals [9]: 1 Ecient partitioning of memory array into ientical blocks of a reasonable size. 2 Block write/rea operations uring the testing moe to access locations within a block in each partition in parallel. 3 Ecient BICC circuit with high sensitivity an accurate I th selection. The rst an secon goals are achieve by certain moications to aress an segment ecoers, an memory array. Consier the memory array of K X -bit wors shown in Figure 3. This array is compose of eight segments. The three most signifacent bits (a 10,a 12 ) of the row register are use for the segments ecoer. The remaining bits (a 0, a 9 ) are use for the 1K aress ecoer.
Test signal (t) W/R Data-in register 0 1 2 3 4 5 6 7 a a 0 1 a 12 a 11 a 10 3-to- ecoer segment ecoel A0 A1 A7 A0 A1 A7 t c t c tc Bit rives a 0 a 1 Block 0 Block 1 Block 2 Block 3 Aress register 10 1 -to- 1K ecoer bits 0 bits 1 bits 2 3 4 5 6 7 bits bits bits bits bits bits a 10 a a 11 12 S 0 S 1 S S 2 3 S 4 S 5 S 6 S 7 GND2(O) GND1(O) Figure 3: The I DDQ K X testable SRAM If we are assuming only one BICC is use, i.e. the array can only be partitione into two partitions, then two GND(O) noes are require. Segments are ivie equally among the GND(O) noes. Segments S 0, S 2, S 4, an S 6 are connecte to a one GND(O) noe an the other segments are connecte to the other GND(O) noe. However, epening on the size of the memory array, more than two partitions may be require. If four partitions are to be use, then two segments are connecte to a GND(O) noe (i.e. four GND(O) noes) an two BICCs are require. For the example uner consieration, let us assume two partitions. A test signal (t) is require such that uring normal operation moe t=0. During test moe when t=1, memory cells in both partitions are accesse simultaneously for
parallel write/rea operations. The segment ecoer is moie by aing the test signal (t). The write operation is performe when W=R signal is low. The most crucial issue is the aress ecoer moications that allow selective access to several physically contiguous or physically interleave memory locations simultaneously. The conventional aress ecoer is moie to allow two moes of operation, normal an testing. To achieve high test spee, the process of current comparisons is neee to be limite to a minimum number, which implies minimum number of comparan blocks neee (goal 1 above). For the example uner consieration, we assume that each of the 1K X cell segment can only be ivie into four blocks. In general it can be more than four blocks epening on the size of the memory array. During the normal operation moe (t=0), the ecoer works normally an is able to activate only one wor line for each write or rea operation. During the testing moe (t=1), the ecoer is able to activate one block of locations simulatenously. To achieve this moe of operation, the two least signicant bits a 0 an a 1 of the aress register, an the test signal (t) are use to perform block selection uring the testing moe as shown in Figure 3. Another test signal t c is require to perform state-coupling test. Moications to the bit rivers are shown in Figure 4. Bit rivers are moie such that when t c = 1, test vectors of interchangeably complemente bits like (01010101) vector can be written to each physical wor. Consier Figure 4 for the write operation to segment 0. When t c = 1, ecoer output lines A 1, A 3, A 5, an A 7 are activating their corresponing bit rivers to allow complement of the input bit to be written to the corresponing memory cells of the segment. This applie for each segment. However, the ecoer works normally when t c =0. In the test moe, each partition contains four blocks. Physical locations of the four blocks are interleave with each other. The remaining higher orer bits are to select the locations within the block in the normal moe of operation. The operation is such that uring the testing moe, the AND gate that correspons to a combination of (a 0 ;a 1 ) is active,thus the corresponing 1K aress lines of the aress ecoer are active. These active lines of the aress ecoer are going to select 1K interleave wors (a block) in each partition. These two blocks are accesse simulatenously. The currents from both blocks are compare while parallel write/rea operations are performe into both blocks. From this esign shown in Figure 3, only one block is selecte from each partition for current comaparision.
Test signal (t) W/R a 10 a 11 a 12 Segment ecoer A 0 A1 0 Data-in 7 A 7 A 0 A 2 t c t c A1 A 7 Bit Bit Bit Bit Bit Bit Bit Bit Segment 0 Figure 4: Bit-rive Moications 4 Test Scheme Faults that enhance I DDQ are mainly transition faults, state coupling an briging faults, an neighborhoo pattern sensitive faults. To etect state coupling an briging faults, all states of two ajacent cells i an j in a segment shoul be consiere [11]. The testing sequence contains a set of parallel write/rea operations to the blocks, such that if a test vector v is applie to block i, then v is applie to block (i + 1). A minimal test sequence contains two patterns each of (00000000) an (11111111) test vectors. The proceure is to apply a pattern without activating t c signal. Then the same pattern is applie when t c is activate. For example, when t c is active an test vector (00000000) is applie, then vector (01010101) is written to the array. However, when vector (11111111) is applie while t c is active, vector (10101010) will be written to the array. This test sequence is capable of etecting stuck-at an a large fraction of state coupling an briging faults. For each test vector applie, four block write operations an four block rea operations are require as shown:
Write: block 0 (00000000) Write: block 1 (11111111) Write: block 2 (00000000) Write: block 3 (11111111) Rea : block 0 Rea : block 1 Rea : block 2 Rea : block 3 The above sequence is repeate for t c =1. Ift c is not use, it will take times as long to write a pattern like (01010101) to a physical wor. Although neighborhoo pattern sensitive faults are consiere complex faults an require a series of write/rea operations into small sets of interleave locations, the sequence above is capable of etecting some of those faults. From above, it is clear that 16 parallel write/rea operations are require to test the SRAM for the faults assume. This scheme may not cover some non I DDQ testable failure moes which may nee to be consiere separately. Several of the well known SRAM testing algorithms have a complexity proportional to n, where n is the number of memory locations. With the testable scheme propose, the complexity of testing is proportional to b, where b is the number of blocks. Since b n, the testing process is speee-up proportional to (n/b). However the accuracy of testing epens also on the performance an sensitivity of the comparator BICS use for current monitoring. 5 Conclusions We have extene the ierential concept in [9] for a general I DDQ testable SRAM esign. The propose scheme employs memory array partitioning an parallel write/rea operations, uring which several faults are activate with elevate quiescent power supply current. The currents are compare in one phase for each opearion. This enhances the testability such that testing can be performe in a signicantly shorter time. A possible test sequence is presente. However, several questions remain unanswere in this area. For example, how to make optimal partitioning such that it will not a more harware overhea, an accoringly how to make the selection of the of the threshol current I th. References [1] C. A. Papachristou an N. B. Sahgal, \An Improve Metho for Detecting Functional Faults in Semiconuctor Ranom Access Memories," IEEE Trans. on Computers, vol. c-34, no. 2, pp. 110-116, February 195.
[2] R. Rajsuman an K. Rajkanan, \An Architecture to Test Ranom Access Memories," Proc. 4th. Int'l. VLSI Design Conf., pp.144-147, Bangalore, Inia, January 1992. [3] R. Meershoek, B. Verhest, R. McInerney an L. Thijssen, \ Functional an I DDQ Testing on a Static RAM," Proc. Int'l Test Conf., pp.929-937, 1990. [4] W. K. Al-Assai, Y. K. Malaiya, an A. P. Jayasumana, \Moeling of Intra-Cell Defects in CMOS SRAM," Recors of the 1993 IEEE International Workshop on Memory Testing, pp. 7-1, August 1993. [5] H. Yokoyama, H. Tamamoto an Y. Narita, \A Current Testing for CMOS Static RAMs," Recors of the 1993 IEEE Int'l Workshop on Memory Testing, pp. 137-142, August 1993. [6] C. Elm an D. Tavangarian, \Fault Detection an Fault Localization Using I DDQ -Testing in Parallel Testable FAST-SRAMs," Proc. IEEE VLSI Test Symp., pp. 30-35, April 1994. [7] C. Kuo, T. Toms, B. T. Neel, J. Jelemensky, E. A. Carter, an P. Smith, \Soft-Defect Detection (SDD) Technique for a High-Reliability CMOS RAM," IEEE Journal of Soli- State Circuits, vol. 25, no.1, pp. 61-66, February 1990. [] S. T. Su an R. Z. Makki, \Testing of Static Ranom Access Memories by Monitoring Dynamic Poer Supply Current," Journal of Electronic Testing: Theory an Applications, vol. 3, no. 3, August 1992, pp. 265-27. [9] W. K. Al-Assai, A. P. Jayasumana an. K. Malaiya, \ A Bipartite, Dierential I DDQ Testable Static RAM Design," Recors of the 1995 IEEE International Workshop on Memory Technology, Design an Testing, pp. 36-41, August 1995. [10] A. D. Singh an J. P. Hurst, \Incorporating IDDQ Testing in BIST: Improve Coverage through Test Diversity," Proc. IEEE VLSI Test Symp., pp.374-379, April 1994. [11] R. Dekker, F. Beenker, an L. Thijssen, \A Realistic Fault Moel an Test Algorithms for Static Ranom Access Memories," IEEE Transaction on Computer-Aie Design, vol. 9, no.6, June 1990, pp.567-572.