RAM Testing Algorithms for Detection Multiple Linked Faults

Transcription

1 RAM Testing Algorithms for Detection Multiple Linked Faults V.G. Mikitjuk, V.N. Yarmolik, A.J. van de Goor* Belorussian State Univ. of Informatics and Radioelectronics, P.Brovki 6, Minsk, Belarus *Delft Univ. of Technology, P.O.Box 5031, 2600 GA Delft, The Netherlands Abstract Many fault models for RAMs and tests for faults of these models are available. In most cases these tests allow for the detection of single faults only. This paper contains fault coverage analysis of march tests which detect multiple faults. It is shown there are faults which are not detected by any of the existing march tests. So we propose new test algorithms which cover multiple faults and particularly are effective to detect linked faults while, at the same time, having short test time. Key words: traditional RAM fault models, multiple linked faults, march tests, inductive fault analysis. 1. Introduction Testing Random Access Memories for all possible failures is not feasible. We have to restrict the class of faults to be considered. This restricted class is called a fault model. Many fault models for RAMs have been proposed. In this paper we consider traditional fault models and tests which allow to detect not only single but also multiple faults. We choose only march test algorithms which require test times on the order of n (where n is the number of bits on the memory). Algorithms which require test time on order of n 2 or n 3/2 are impractical for modern high density RAM chips (16 megabits and more). Memory faults can be single or multiple. Multiple faults additionally can be linked or unlinked. A fault is linked when that fault may influence the behaviour of other faults [1]. A fault is unlinked when that fault does not influence the behaviour of other faults. In [1,2] it is shown that faults are linked when they affect the same cell. The "link" between faults can cause the test not to find any faults; this effect is called masking. We show that not all linked multiple faults are detected by existing tests. So we propose new effective algorithms for testing linked faults. We prove that new algorithms have higher fault coverage than existing march tests for linked multiple faults. Then, we consider fault models based on physical defects analysis [3,4] and show that the new tests are effective for these faults too. 2. Concept of march tests Many types of tests for RAMs have been proposed in the past. Currently, one family of the tests, called march tests [5,6], has proven to be superior for test time and simplicity of the algorithms. A march test consists of a sequence of march elements. A march element consists of a sequence of operation applied to each cell in the memory, before proceeding to the next cell. An operation can consist of writing a 0 into a cell (w0), writing a 1 (w1), reading a cell with expected value (r0 and r1). The address of the next cell is determined by the address order. Two exist: an increasing address order from address 0 to n-1 denoted by the symbol; and a decreasing address order denoted by the symbol. When the address order is irrelevant, the is used. 3. Traditional RAM fault models For the development of a fault model, a RAM is divided into three blocks: 1) The address decoder. 2) The memory cell array. 3) The R/W logic Faults in the memory cell array. Many different faults can occur in a memory cell array. The following notation [2,7] will help to describe the faults: - denotes a w1 operation to a cell containing a 0; - denotes a w0 operation to a cell containing a 1; ED&TC /96 $ IEEE

2 - denotes a wx operation to a cell containing an x; - denotes any operation; Ax Cx Ax Cx Ax Cx <S/F> - denotes a fault in a single cell; Ax Cx S - describes the value/operation sensitizing the fault; Ay Cy Ay Cy Ay Cy S {0,1,,, }; S T - says that the sensitization effect appears after a Failt A (1+2) Fault B (1+3) Fault C (2+4) Fault D (3+4) time T; F - describes the faulty value of the cell; F {0,1} Figure 1. Combinations of address decoder faults <S 1,S 2,..., S m-1 ; F> - denotes a fault involving m cells. S 1, S 2,..., S either fault 2 or fault 3 must also occur. With fault 2, at m-1 describes the conditions of the m-1 cells least fault 1 or fault 4 occur; with fault 3, at least fault 1 required to sensitise the fault in the cell m, the faulty or 4; with fault 4, fault 2 or 3. These four fault value is denoted by F. combinations are shown in Figure 1 [2]. A stuck-at fault (SAF) means that the logic value of the cell can not be changed by any action on the cell or by influences from other cells. The notation < /1> denotes an SA1 fault and < /0> - SA0 fault. A memory cell with a transition fault (TF) fails to undergo at least one of the transitions 0 1(< /0>) or 1 0(< /1>). An inversion coupling fault (CF in ) [2,5-7] involves two cells i and j; the fault is sensitised by a transition write operation to a particular cell j. Cell j is called the coupling cell and inverts the contents of cell i, which is called the coupled cell. Two different CF ins can be recognized: the < ; > and the < ; >. An idempotent coupling fault (CF id ) [2,5-7] involves two cells i and j. The fault is sensitized by a transition write operation to a cell j, which forces the contents of another cell i to a fixed value (0 or 1). In this paper we consider CFs for which one cell may influence to another cell by one way only. So four different CF ids can be recognised: < ;0>, < ;1>, < ;0>, < ;1>. Linked faults may occur between faults of the same type or between faults of the different types. The SAF is always detected even when TFs or CFs are linked with the SAF [2]. So we have to consider next linked faults in the memory array: TF-CF, CF id -CF id, CF id -CF in, CF in - CF in. These linked faults can involve not only two but any number of faults of these types. Faults A and B are inherently unlinked: it is not possible to mask the fault when one reads A x Faults C as well as fault D may be linked. AFs linked and unlinked are detected by march tests for the memory cell array if they satisfy the conditions of Table 1 [2]. If the technology of RAM is known (i.e. whether the memory device returns the AND function or the OR function when multiple cells are read), the conditions of Table 1 can be simplified. The simplified conditions are depicted in Table 2 [2] Faults in the R/W logic The R/W logic passes the data information from I/O pins to the memory array and vice versa. All faults in the R/W logic can be regarded as faults in the memory array [2]. It means that no separate tests for read/write logic are required. 4. March tests for detection linked multiple faults. There are many march tests optimized for a particular set of functional faults [2]. Descriptions of their algorithms are presented in the Table 3. Table 4 contains fault coverage analysis of these march tests. The columns CF in -CF in, CF in -CF id in this table are empty. It says that there is a problem to detect these faults Address decoder faults (AFs) Table 1. Conditions for detecting AFs Functional faults that occur in the address decoder can Condition March element be the next [2]: 1 (rx,..., wx ) Fault 1. With a certain address, no cell will be accessed. 2 Fault 2. A certain cell will not be accessible. (rx,..., wx) Fault 3. With a certain address, multiple cells are accessed simultaneously. Table 2. Conditions for known technology. Fault 4. A certain cell can be accessed with multiple Cond. OR technology AND technology addresses. 1 (..., w0);(r0, (..., w1);(r1,...,w0) Because there are as many cells as addresses, none of the above faults can stand alone. When fault 1 occurs 2...,w1) (..., w1);(r1,...) (..., w0);(r0,...)

3 Table 3. March test algorithms with the expected state as result. Thus no fault can be Test Description of algorithm detected. So March M also cannot detect the faults which satisfy MATS+ (w0); (ro,w1); (r1,w0) theorem 1. But these faults constitute only small part of all linked inversion CFs. So, in Table 4 and further, by MATS++ (w0); (ro,w1); (r1,w0,r0) linked CF ins we will mean faults which do not satisfy theorem 1. March X (w0); (ro,w1); (r1,w0); (r0) Table 5 contains a description of the new 16n-length test algorithm. This test is shorter than March B (the most March C- (w0); (ro,w1); (r1,w0); (ro,w1); universal march for traditional RAM faults) and has higher fault coverage. It can be proven that March M (r1,w0); (r0) detects all these faults. March A (w0); (r0,w1,w0,w1); (r1,w0,w1); Theorem 2. March M detects all SAFs. (r1,w0,w1,w0); Proof : it is easy to show that March M detects all SAFs. (r0,w1,w0); A 0 and 1 is written into and read from every memory cell March B (w0); (r0,w1,r1,w0,r0,w1); (for example in M1), so SAF0 and SAF1 are detected. (r1,w0,w1); (r1,w0,w1,w0); (r0,w1,w0); Theorem 3. March M detects all TFs and TFs linked with CFs. Proof : these faults are detected by M1 and M5. M1 The new test March M which we present in this paper detects all linked multiple faults under the fault models. Note that, in general, not every linked CF in can be generates an transition in every cell and immediately thereafter the cell is read, so < /0> faults are detected. As no other cells are written in between, the TF cannot be detected by march tests. To simplify the discussion, the masked by a CF. < /1> faults will be detected by M5 following notation will be used: <S;F> - fault in which the coupled cell has a higher address then a coupling cell; and cannot be masked by a CF for reasons similar to those for < /0> TFs. Theorem 4. March M detects all CF ids. <S;F> - fault in which the coupled cell has a lower address then a coupling cell. So there are four different types of inversion CFs: < ; >, < ; >, < ; >, < ; >. Theorem 1. Linked inversion CFs are not detected by any march test if they contain an even number (or 0) of inversion CFs of each type. Proof : if there are these faults, any march element will Proof : march elements M1 and M5 which contain 2 write operations and the following march elements M2 and M6 which contain only one read operation allow to detect every CF id. The address order of these march elements is irrelevant. M1 sensitizes and then detects any faults < ;1>, < ;1>. Moreover M1 sensitizes any faults < ;1>, < ;1> which afterwards are detected by r0 operations in M2. Note: if M1 would have the address order, it generate an even number of inversions in the coupled cell Table 4. Fault coverage of march tests. Test Detected faults MATS+ AF SAF TF CF in CF id TF-CF CF id - CF in - CF in - CF id CF in CF id MATS++ March X March C- March A March B

4 Proof : as follows from theorem 1 linked CF Table 5. Test March M. in can be detected by march tests only if it involves an odd number March element Description of faults if only one from four types of CF ins. M0 w0 March element M3 is surrounded by march elements M1 r0,w1,r1,w0 M2 and M4 which do not generate CF ins, what rules out M2 r0 the possibility of compensation one another CF ins which M3 r0,w1 are initiated by neighbouring march elements. M3 M4 r1 sensitizes and detects any faults < ; > and linked CF ins which involve an odd number of < ; >. M5 r1,w0,r0,w1 Moreover M3 sensitizes < ; > faults and linked CF M6 r1 ins which involve an odd number of < ; > These faults M7 r1,w0 are detected by read operation in M4. Then it remains to be proved that March M detects < sensitizes and then detects any faults < ;1>, < ;1>, ; > and < ; > CF ins and linked CF ins which involve and sensitizes any faults < ;1>, < ;1> which then are an odd number of < ; > or. < ; > faults (but do not detected by M2. Similarly we can show that faults < involve an odd number of < ; > faults as they detects by ;0>, < ;0> and < ;0>, < ;0> are detected by march M3 and M4). These faults will be detected by march elements M5 and M6. element M5 and M6. < ; > faults will be sensitized Theorem 5. March M detects every CF id -CF id. and detected by M5 but < ; > faults will be sensitized Proof : for detection of every linked CF ids the address by M5 and then will be detected by the read operation in orders of march elements M1 and M5 have to coincide as M6. in table 5. In this case one of the CF ids which are linked will be always detected : - the CF id with the shortest distance between a coupled and a coupling cell if the coupled cell has a larger address than the coupling one ( < ;1>, < ;1> are detected by M1; < ;0>, < ;0> are detected by M4); - the CF id with the largest distance between a coupling and a coupled cells if the coupled cell has a smaller address than the coupling one ( < ;1>, < ;1> are detected by M1 and M2; < ;0>, < ;0> are detected by M5 and M6). These faults never can be masked by another CF id in these march elements and so they will be detected. Theorem 6. March M detects every CF in -CF id. Proof : march elements M1, M2 and M5, M6 detect every CF in -CF id. < ;1> and < ;1> CF ids are detected by M1 and they can be masked in this march element only by an odd number of < ; > or < ; > CF ins, if the the coupling cells of these CF ins have larger addresses than the coupling cell of the CF id. But such linked faults will be detected by M5. < ;1> and < ;1> CF ids are sensitized by M1 and are detected by M2; they can be masked only by an odd number of < ; > or < ; > CF ins, if the coupling cells of these CF ins have larger addresses than the coupling cell of the CF id. But such linked faults will be detected by M5 and M6. Similarly we can show that CF ids < ;0>, < ;0> and < ;0>, < ;0>, if they are masked by CF ins in march elements M5 and M6 will always be detected by march elements M1 and M2. Theorem 7. March M detects all CF ins and linked CF ins. Theorem 8. March M detects all AFs. Proof : March elements M3 and M7 satisfy the condition of table 1, so AFs are detected. We have proved that the new 16n test detects all linked multiple faults. As follows from proofs of theorems 2-8 march element M7 is required only for the detection of AFs. So we present two new 14n algorithms March M-- OR and March M-- AND which allow to detect all linked multiple faults when the technology of the RAM is known. Descriptions of their algorithms are presented below. March M-- OR : (w0); (r0,w1,r1,w0); (r0); (r0,w1); (r1); (r1,w0,r0,w1); (r1) March M-- AND : (w1); (r1,w0,r0,w1); (r1); (r1,w0); (r0); (r0,w1,r1,w0); (r0) Theorems 2-7 prove that all linked multiple faults in the memory array are detected by the new 14n tests. Both these algorithms satisfy the conditions of Table 2, so they allow to detect AFs if the technology is known. 5. Development of the new tests to detect faults based on real phisi-cal defects The traditional fault models were largely based upon the mathematics and not on the actual manufacturing defects. Dekker et. al. [3] applied defect oriented inductive fault analysis (IFA) to evolve a SRAM fault models. Spot defects were the basis of this analysis.

5 Oberle [4] attempted a similar approach on DRAMs. (w0); (r0,w1,r1,w0); Del; (r0); (r0,w1); (r1); Efficient fault models of the circuits can be derived from (r1,w0,r0,w1); Del; (r1) this analysis: March M-- AND : 1. A memory cell is stuck-at 0 or stuck-at 1. (w1); (r1,w0,r0,w1); Del; (r1); (r1,w0); (r0); 2. A memory cell is stuck-open. (r0,w1,r1,w0); Del; (r0) 3. A memory cell is coupled to another cell. 4. A memory cell has multiple access faults. 5. A memory cell suffers from a data retention fault. As we see two new fault models there are in this list. A stuck-open fault (SOF) means that a cell cannot be accessed, perhaps because of an open word line [3,7]. When a read operation is performed on a cell, the differential sense amplifier (SA) has to sense a voltage difference between the bit lines of that cell. In the case of SOF, both bit lines will have the same voltage level; consequently the output value produced by the sense amplifier depends on the way it is implemented. If the SA is combinational or if the SA has only a single input, it will pass a defined logical value to the output pin. In this case a stuck-open fault will be detected as if it was a stuck-at fault. However, some designs of sense amplifiers include a latch in the read path. Then a SOF may have the effect that the latch is not update because the voltage difference between the bit lines is too small. The previous output value is produced as the output value for the SOF. Dekker et al. [3] highlighted the problem of stuck-open detectability for sequential R/W logic. They suggested that there must be a march element in which the value x and the value x are read from a cell, and another, or possibly the same, march element, where value x and the value x are read from a cell. As march elements M1 and M5 in the new tests satisfy these conditions so tests which we presented allow to detect SOFs. It is easy to see that SOF is always detected even if it linked. A data retention fault (DRF) occurs when a cell fails to retain its logical value after some period of time [3]. Two different DRFs can be recognized (both may be simultaneously present in a single cell): <1 T /0> and <0 T /1>. When both are present in one cell, the cell behaves as if it contains an SOF (because there will not be a voltage difference between bit lines) [7]. Any march test can be extended to cover DRFs [7]. The detection of a DRF requires that a memory cell be brought into one of its logic states. A certain time (called delay time) must pass while DRF develops. Thereafter the contents of the cell are verified. This test must be repeated with the inverse logic value stored into the cell. So below we present a development of the new tests to detect DRFs. March M: (w0); (r0,w1,r1,w0); Del; (r0); (r0,w1); (r1); (r1,w0,r0,w1); Del; (r1); (r1,w0). March M-- OR : The Del elements represent the delay time which one must wait before applying the next march element. The amount of time to wait depends on the amount of charge stored in the capacitor of the node and magnitude of the leakage current. For example the delay time for the Philips 8k8 design can be up 100ms [3]. As our tests have march elements which contain only a read operation (M2 and M6) there is no need for the addition of a special data retention test as in [3,7]. In our case fault masking can not occur. 6. Conclusion In this paper we have presented new efficient march tests for RAMs. These tests allow to detect not only single but also multiple linked faults under the fault models. March M is the most universal test algorithm which detects 100% of the faults when the RAM technology is unknown. If the RAM technology is known March M-- OR or March M-- AND may be applied. The proposed algorithms show excellent features in both test time and fault coverage. They are shorter than another algorithms for linked faults and have higher fault coverage. Moreover new tests allow to detect faults based on real phisical defects with minimal overheads. References 1. C.A. Papachristou and N.B.Saghal, "An Improved Method for Detecting Functional Faults in Random Access Memories", IEEE Trans. Computers, Vol. C-34, No. 2, 1985, pp A.J. van de Goor, Testing Semiconductor Memories, Theory and Practice, John Wiley & Sons, Chichester, UK, R.Dekker, F.Beenker and L.Thijssen, "Fault Modelling and Test Algorithm Development for Static Random Access Memories", Proc. of Int. Test Conf., pp , H.D.Oberle and P.Muhmenthaler, "Test Pattern-Development and Evaluation for DRAMs with Fault Simulator RAMSIM", Proc. of Int. Test Conf., pp , D.S Suk and S.M.Reddy, "A March Test for Functional Faults in Semiconductor Random-Access Memories", IEEE Trans. Computers, Vol. C-30, No.12, 1981, pp M.Marinescu, "Simple and Efficient Algorithms for Functional RAM Testing", Proc. IEEE Int. Test Conf., 1982, pp A.J. van de Goor, "Using March Tests to Test SRAMs", Design & Test of Computers, Vol. 10, No.1, 1993, pp.8-14