AltaSens A5262-4T 4.5 Megapixel CMOS Image Sensor 0.18 µm IBM Process Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Package and Die 2.1 Package 2.2 Die 2.3 Die Features 3 Process 3.1 General Structure 3.2 Organic Layers 3.3 Bond Pads 3.4 Dielectrics 3.5 Metals 3.6 Vias and Contacts 3.7 Peripheral Transistors and Poly 3.8 MIM Capacitors 3.9 Isolation 3.10 Wells, Epi, and Substrate 4 Pixel Array Analysis 4.1 Pixel Schematic 4.2 Pixel Array Plan View Analysis 4.3 Pixel Array Cross-Sectional Analysis 5 Memory Cell Analysis 5.1 Multi-Port SRAM Overview 5.2 Multi-Port SRAM Plan View Analysis 6 Critical Dimensions 6.1 Package and Die 6.2 Vertical Dimensions 6.3 Horizontal Dimensions
Imager Process Review 7 References 8 Statement of Measurement Uncertainty and Scope Variation Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Package and Die 2.1.1 Hitachi DZ-BD7H HD Camcorder 2.1.2 Identification Markings of Hitachi DZ-BD7H HD Camcorder 2.1.3 Hitachi DZ-BD7H HD Camcorder Side View 2.1.4 Hitachi DZ-BD7H HD Camcorder Front View 2.1.5 Inside of Hitachi DZ-BD7H HD Camcorder 2.1.6 A5262-4T Image Sensor and Lens Assembly Extracted from the Hitachi DZ-BD7H 2.1.7 A5262-4T Package on PCB Top View 2.1.8 A5262-4T Package on PCB X-Ray 2.1.9 A5262-4T Package on PCB with Copper Plate Intact Bottom View 2.1.10 A5262-4T Package on PCB With Copper Plate Removed Bottom View 2.1.11 A5262-4T Package on PCB X-Ray Top View 2.2.1 Die Photograph Intact 2.2.2 Die Photograph Decapsulated 2.2.3 Die Markings 1 2.2.4 Die Markings 2 2.2.5 A5262-4T Metal 1 Die Photograph 2.2.6 Annotated Die Photograph 2.3.1 Die Corner A 2.3.2 Die Corner B 2.3.3 Die Corner C 2.3.4 Die Corner D 2.3.5 Die Edge A 2.3.6 Die Edge B 2.3.7 Die Edge C 2.3.8 Die Edge D 2.3.9 Minimum Pitch Bond Pads 2.3.10 Minimum Pitch Bond Pads Detail 2.3.11 Pixel Array Corner A 2.3.12 Pixel Array Corner B 2.3.13 Pixel Array Corner C 2.3.14 Pixel Array Corner D 2.3.15 SRAM Block
Overview 1-2 3 Process 3.1.1 Array General Structure 3.1.2 Peripheral General Structure 3.1.3 Die Edge and Die Seal 3.1.4 Die Seal and Organic Layer Edge 3.2.1 Blue Filter Edge 3.2.2 Organic Lens Boundary 3.3.1 Bond Pad 3.3.2 Right Bond Pad Edge 3.3.3 Left Bond Pad Edge 3.3.4 Left Bond Pad Edge Detail 3.4.1 Passivation 3.4.2 ILD 3 3.4.3 ILD 2 3.4.4 PMD 3.4.5 PMD 1 and Pixel AR Layer 3.5.1 Minimum Peripheral Metal 4 3.5.2 Minimum Pitch Metal 3 3.5.3 Minimum Metal 2 3.5.4 Metal 2 TEM 3.5.5 Minimum Metal 1 3.5.6 Metal 1 TEM 3.6.1 Minimum Pitch Via 3s 3.6.2 Minimum Pitch Via 2s 3.6.3 Minimum Pitch Via 1s 3.6.4 Minimum Pitch Contacts to Poly 3.6.5 Contact to Poly TEM 3.6.6 Minimum Pitch Contacts to Substrate 3.7.1 Peripheral NMOS Glass Etch 3.7.2 Peripheral NMOS Si Etch 3.7.3 Peripheral PMOS Si Etch 3.8.1 MIM Capacitor 3.8.2 MIM Capacitor in Detail Contact to Lower Plate 3.8.3 MIM Capacitor in Detail Contact to Upper Plate 3.9.1 Minimum Width STI in Periphery 3.9.2 Poly Over STI 3.9.3 TEM Minimum Width STI in Pixel Area 3.10.1 Peripheral P-Wells at the Die Edge 3.10.2 Peripheral P-Wells and N-Wells 3.10.3 SCM Peripheral Wells at Die Edge 3.10.4 SCM Peripheral Wells at Die Edge Detail 3.10.5 SCM Peripheral Wells Detail 3.10.6 SRP Periphery P-Well 3.10.7 SRP in Periphery Shallow N-Well 2 3.10.8 SRP in Pixel Array
Overview 1-3 4 Pixel Array Analysis 4.1.1 Pixel Schematic Circuit 4.2.1 Pixel Array Corner Optical 4.2.2 Pixel Array Lenses 4.2.3 Pixel Array Lenses Tilt View 4.2.4 Pixel Array at Metal 3 4.2.5 Pixel Array at Metal 2 4.2.6 Pixel Array at Metal 2 Detail 4.2.7 Pixel Array at Via 1 4.2.8 Pixel Array at Metal 1 4.2.9 Pixel Array at Poly 4.2.10 Pixel Array at Poly Detail 4.2.11 Pixel Array at Substrate 4.2.12 Pixel Array at Substrate SCM 4.2.13 Pixel Array at Substrate Detail SCM 4.3.1 Pixel at Poly Showing Cross-Sectional Planes Plan View 4.3.2 Pixel Array General Structure (S1 Blue-Green Filters) 4.3.3 Pixel Array General Structure (S1 Red-Green Filters) 4.3.4 Pixel Array Right Edge (S1) 4.3.5 Pixel Array Bottom Edge (S2) 4.3.6 Lenses and Green Color Filters (S2) TEM 4.3.7 Lenses and Red Color Filters (S2) TEM 4.3.8 Blue Color Filters (S2) TEM 4.3.9 Blue and Green Color Filter Edge (S2) TEM 4.3.10 General Structure T1 and T4 Transfer Transistors (S2) 4.3.11 General Structure T2 and T3 Transfer Transistors (S2) 4.3.12 T2/T3 Transfer Transistors (S2) TEM 4.3.13 General Structure T5 Transistor (S1) 4.3.14 General Structure T6 and T7 Transistors (S1) 4.3.15 T1 Transfer Transistor (S2) Glass Etch 4.3.16 T1 Transfer Transistor (S2) Silicon Etch 4.3.17 T2 Transfer Transistor (S2) Silicon Etch 4.3.18 T3 Transfer Transistor (S2) Silicon Etch 4.3.19 T4 Transfer Transistor (S2) Silicon Etch 4.3.20 Transfer Transistor and FD Contact TEM 4.3.21 Transfer Transistor in Detail TEM 4.3.22 Right Edge of Transfer Transistor TEM 4.3.23 TEM Transfer Transistor Gate Oxide TEM 4.3.24 SCM Pixel Through Transfer Transistors (S2) 4.3.25 SCM Pixel Through Transfer Transistors (S2) Detail
Overview 1-4 4.3.26 Reset Transistor T5 (S1) 4.3.27 Source Follower Transistor T6 (S1) 4.3.28 Row Select Transistor T7 (S1) 4.3.29 Reset Transistor T5 Width (S2) 4.3.30 Source Follower Transistor T6 Width (S2) 4.3.31 Row Select Transistor T7 Width (S2) 5 Memory Cell Analysis 5.1.1 Single Multi-Port SRAM Sub-Block 5.2.1 Multi-Port SRAM Metal 3 5.2.2 Multi-Port SRAM Poly 5.2.3 Multi-Port SRAM in Detail Poly 5.2.4 SRAM Transistor Width TEM 5.2.5 SRAM Transistor Gate Oxide 5.2.6 ROM Block 5.2.7 ROM Poly
Overview 1-5 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.6.1 Summary of Major Findings 2 Package and Die 2.2.1 Functional Block Sizes 2.3.1 Die and Bond Pad Dimensions 3 Process 3.4.1 Dielectric Composition and Thicknesses 3.5.1 Metallization Composition and Thicknesses 3.5.2 Minimum Metals Horizontal Dimensions 3.6.1 Via and Contact Horizontal Dimensions 3.7.1 Transistor and Polysilicon Horizontal Dimensions 3.7.2 Transistor and Polysilicon Vertical Dimensions 3.9.1 Isolation Horizontal Dimensions 3.10.1 Wells and Epi Vertical Dimensions 4 Pixel Array Analysis 4.2.1 Pixel Horizontal Dimensions 4.3.1 Pixel Vertical Dimensions 4.3.2 Transistor Dimensions in Pixel Array 6 Critical Dimensions 6.1.1 Die and Bond Pad Dimensions 6.2.1 Dielectric Composition and Thicknesses 6.2.2 Metallization Composition and Thicknesses 6.2.3 Transistor and Polysilicon Vertical Dimensions 6.2.4 Wells and Epi Vertical Dimensions 6.2.5 Pixel Vertical Dimensions 6.3.1 Minimum Metals Peripheral Horizontal Dimensions 6.3.2 Minimum Metals Pixel Array Horizontal Dimensions 6.3.3 Via and Contact Horizontal Dimensions 6.3.4 Transistor and Polysilicon Horizontal Dimensions 6.3.5 Isolation Horizontal Dimension 6.3.6 Pixel Horizontal Dimensions 6.3.7 Transistor Dimensions in Pixel Array
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