Nokia N90 (Toshiba ET8EA3-AS) 2.0 Megapixel CMOS Image Sensor Process Review
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1 November 21, 2005 Nokia N90 (Toshiba ET8EA3-AS) 2.0 Megapixel CMOS Image Sensor Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.
2 Process Review Table of contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Package and Die 2.1 Package 2.2 Die 2.3 Die Features 3 Process 3.1 General Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metals 3.5 Vias and Contacts 3.6 MOS Transistors and Poly 3.7 Isolation 3.8 Wells and Epi 4 Pixel Array Analysis 4.1 Pixel Schematic 4.2 Pixel Array Plan-View Analysis 4.3 Pixel Array Cross-Sectional Analysis 5 Embedded SRAM Analysis 5.1 Cell Schematic 5.2 SRAM Plan-View Analysis 6 References 7 Critical Dimension 7.1 Vertical Dimensions 7.2 Horizontal Dimensions Report Evaluation
3 Overview Overview 1.1 List of Figures 2 Package and Die Nokia N90 Cell Phone Front Nokia N90 Cell Phone Open Nokia N90 Cell Phone Side Identification Markings on Nokia N90 Cell Phone N90 CIS Assembly Top-View N90 CIS Assembly Back-View N90 CIS Assembly X-Ray Top-View Die Photograph Color Filters Intact Die Photograph Color Filters Removed Die Markings Annotated Die Photograph Analysis Sites Die Corner a Die Corner b Die Corner c Die Corner d Die Markings Minimum Pitch Bond Pads Single Bond Pad Detail SRAM Block
4 Overview Process Peripheral General Structure Array General Structure Die Edge Dielectrics at Die Edge Bond Pad Bond Pad Edge Passivation ILD ILD PMD and STI Minimum Metal Minimum Metal Minimum Metal Minimum Pitch Via 2s Minimum Pitch Via 1s Minimum Pitch Contacts to Substrate Contacts to Poly and Diffusion Peripheral MOS Transistor (Glass Etch) Pixel Array NMOS Transistor (Si-Etch) Peripheral NMOS (Si-Etch) Peripheral PMOS (Si-Etch) Minimum Pitch Poly (Glass Etch) Minimum Width STI Poly over STI Peripheral N-Wells and Embedded P-Wells SCM SRP of Peripheral P-Well SRP of Peripheral N-Well SRP of Embedded Peripheral P-Well Pixel Array Epi and Substrate SCM SRP in Pixel Array
5 Overview Pixel Array Analysis Pixel Schematic Circuit Pixel Array Corner Optical Pixel Array Detail Optical Pixel Array Lenses Pixel Array Lenses AFM Tilt-View Pixel Array Lenses AFM Cross-Section Pixel Array at Metal 3 Optical Pixel Array at Metal Pixel Array at Metal Pixel Array at Metal Pixel Array at Poly Pixel Array at Substrate Pixel Array at Diffusions SCM Pixel Array at Photocathode SCM Pixel at Poly Showing Cross-Sectional Planes Plan-View Pixel Array General Structure (Glass Etch; Cross-Section A) Pixel Read Out Transistors (Glass Etch; Cross-Section B) Lenses and Blue and Green Color Filters (Cross-Section A) Lenses and Red-Green Color Filters (Cross-Section A) T1 and T2 Transfer Transistors (Glass Etch; Cross-Section A) T1 and T2 Transfer Transistors (Si-Etch; Cross-Section A) T1/T2 Transfer Transistor Width (Cross-Section C) T1/T2 Transfer Transistor Active Width (Cross-Section D) Pixel Through Transfer Transistors and Pixel (SCM Cross-Section) Transistors T3, T4 and T5 (Si-Etch, Cross-Section B) T3 Reset Transistors Length (Si-Etch, Cross-Section B) T3 Reset Transistors Length (Glass Etch, Cross-Section B) T3 Reset Transistor Width (Glass Etch, Cross-Section E) T4 Source Follower and T5 Row Select Transistors (Si-Etch, Cross-Section B) T4 Source Follower and T5 Row Select Transistors (Glass Etch, Cross-Section B) T4 Source Follower Transistor Width (Glass Etch, Cross-Section F) T5 Row Select Transistor Width (Glass Etch, Cross-Section G) 5 Embedded SRAM Analysis Die Photo Showing SRAM Location T SRAM Cell SRAM at Metal SRAM at Metal SRAM at Poly SRAM at Diffusion
6 Overview List of Tables 1 Overview Device Summary Summary of Major Findings 2 Package and Die Package and Die Dimensions 3 Process Dielectric Composition and Thicknesses Metallization Composition and Thicknesses Minimum Metals Horizontal Dimensions Via and Contact Horizontal Dimensions Transistor and Polysilicon Horizontal Dimensions Transistor and Polysilicon Vertical Dimensions Isolation Horizontal Dimension Wells and Epi Vertical Dimension 4 Pixel Array Analysis Pixel Horizontal Dimensions Pixel Vertical Dimensions Transistor Dimensions in Pixel Array 5 Embedded SRAM Analysis SRAM Transistor Sizes 7 Critical Dimension Package and Die Dimensions Dielectric Composition and Thicknesses Metallization Composition and Thicknesses Transistor and Polysilicon Vertical Dimensions Wells and Epi Vertical Dimension Minimum Metals Horizontal Dimensions Via and Contact Horizontal Dimensions Transistor and Polysilicon Horizontal Dimensions Isolation Horizontal Dimension
7 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com
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