Low Supply-Voltage Range,.8 V to 3.6 V Ultralow-Power Consumption: Active Mode: 28 µa at MHz, 2.2 V Standby Mode:. µa Off Mode (RAM Retention):. µa Five Power Saving Modes Wake-Up From Standby Mode in Less Than 6 µs 6-Bit RISC Architecture, 25-ns Instruction Cycle Time 2-Bit A/D Converter With Internal Reference, Sample-and-Hold and Autoscan Feature 6-Bit Timer_B With Three or Seven Capture/Compare-With-Shadow Registers 6-Bit Timer_A With Three Capture/Compare Registers On-Chip Comparator Serial Communication Interface (USART), Select Asynchronous UART or Synchronous SPI by Software: Two USARTs (USART, USART) One USART (USART) Brownout Detector Supply Voltage Supervisor/Monitor With Programmable Level Detection Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse Integrated LCD Driver for up to 6 Segments Bootstrap Loader Family Members Include: MSP43F435, MSP43F435 : 6KB+256B Flash Memory, 52B RAM MSP43F436, MSP43F436 : 24KB+256B Flash Memory, KB RAM MSP43F437, MSP43F437 : 32KB+256B Flash Memory, KB RAM MSP43F447: 32KB+256B Flash Memory, KB RAM MSP43F448, MSP43F448 : 48KB+256B Flash Memory, 2KB RAM MSP43F449, MSP43F449 : 6KB+256B Flash Memory, 2KB RAM For Complete Module Descriptions, See The MSP43x4xx Family User s Guide, Literature Number SLAU56 MSP43F43x, and MSP43F43x devices MSP43F44x, and MSP43F44x devices The MSP43F43x and MSP43F44x devices are identical to the MSP43F43x and MSP43F44x devices, respectively with the exception that the ADC2 module is not implemented. description The Texas Instruments MSP43 family of ultralow power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The devices feature a powerful 6-bit RISC CPU, 6-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 µs. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 29, Texas Instruments Incorporated POST OFFICE BOX 65533 DALLAS, TEXAS 75265
description (continued) The MSP43x43x() and the MSP43x44x() series are microcontroller configurations with two built-in 6-bit timers, a fast 2-bit A/D converter (not implemented on the MSP43F43x and MSP43F44x devices), one or two universal serial synchronous/asynchronous communication interfaces (USART), 48 I/O pins, and a liquid crystal driver (LCD) with up to 6 segments. Typical applications include sensor systems that capture analog signals, convert them to digital values, and process and transmit the data to a host system, or process this data and display it on a LCD panel. The timers make the configurations ideal for industrial control applications such as ripple counters, digital motor control, EE-meters, hand-held meters, etc. The hardware multiplier enhances the performance and offers a broad code and hardware-compatible family solution. T A AVAILABLE OPTIONS PLASTIC 8-PIN QFP (PN) MSP43F435IPN MSP43F436IPN MSP43F437IPN PACKAGED DEVICES PLASTIC -PIN QFP (PZ) MSP43F435IPZ MSP43F436IPZ MSP43F437IPZ 4 C to 85 C MSP43F435IPN MSP43F436IPN MSP43F437IPN MSP43F435IPZ MSP43F436IPZ MSP43F437IPZ MSP43F447IPZ MSP43F448IPZ MSP43F449IPZ DEVELOPMENT TOOL SUPPORT MSP43F448IPZ MSP43F449IPZ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. All MSP43 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging and programming through easy to use development tools. Recommended hardware options include the following: Debugging and Programming Interface MSP-FET43UIF (USB) MSP-FET43PIF (Parallel Port) Debugging and Programming Interface with Target Board MSP-FET43U (PZ package) Stand-Alone Target Board MSP-TS43PZ (PZ package) Production Programmer MSP-GANG43 2 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
pin designation, MSP43x435IPN, MSP43x436IPN, MSP43x437IPN P6. P6. RST/NMI TCK PN PACKAGE (TOP VIEW) TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P./TA P./TA/MCLK P.2/TA P.3/TBOUTH/SVSOUT P.4/TBCLK/SMCLK P.5/TACLK/ACLK DV CC P6.3 P6.4 P6.5 P6.6 P6.7/SVSIN Reserved XIN XOUT DV SS DV SS P5./S P5./S P4.7/S2 P4.6/S3 P4.5/S4 P4.4/S5 P4.3/S6 P4.2/S7 P4./S8 8 79 78 77 76 75 74 73 72 7 7 69 68 67 66 65 64 63 62 6 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 MSP43F435IPN MSP43F436IPN MSP43F437IPN 6 59 58 57 56 55 54 53 52 5 5 49 48 47 46 45 44 43 42 2 4 2 22 23 24 25 26 27 28 29 3 3 32 33 34 35 36 37 38 39 4 P.7/CA P2./TA2 P2./TB P2.2/TB P2.3/TB2 P2.4/UTXD P2.5/URXD DV SS2 DV CC2 P5.7/R33 P5.6/R23 P5.5/R3 R3 P5.4/COM3 P5.3/COM2 P5.2/COM COM P3./STE/S3 P3./SIMO/S3 P3.2/SOMI/S29 P4./S9 S S S2 S3 S4 S5 S6 S7 P2.7/S8 P2.6/CAOUT/S9 S2 S2 S22 S23 P3.7/S24 P3.6/S25 P3.5/S26 P3.4/S27 P3.3/UCLK/S28 P.6/CA AV CC DV SS AV SS P6.2 POST OFFICE BOX 65533 DALLAS, TEXAS 75265 3
pin designation, MSP43x435IPZ, MSP43x436IPZ, MSP43x437IPZ PZ PACKAGE (TOP VIEW) AV CC DV SS AV SS P6.2 P6. P6. RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P./TA P./TA/MCLK P.2/TA P.3/TBOUTH/SVSOUT P.4/TBCLK/SMCLK P.5/TACLK/ACLK P.6/CA P.7/CA P2./TA2 P2./TB P2.2/TB P2.3/TB2 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 25 99 98 97 96 95 94 93 92 9 9 89 88 87 86 85 84 83 82 8 8 79 78 77 76 75 74 73 72 7 7 69 68 67 66 65 64 63 62 6 6 59 58 57 56 55 54 53 52 5 26 27 28 29 3 3 32 33 34 35 36 37 38 39 4 4 42 43 44 45 46 47 48 49 5 DV CC P6.3 P6.4 P6.5 P6.6 P6.7/SVSIN Reserved XIN XOUT DV SS DV SS P5./S P5./S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 MSP43F435IPZ MSP43F436IPZ MSP43F437IPZ P2.4/UTXD P2.5/URXD P2.6/CAOUT P2.7 P3./STE P3./SIMO P3.2/SOMI P3.3/UCLK P3.4 P3.5 P3.6 P3.7 P4. P4. DV SS2 DV CC2 P5.7/R33 P5.6/R23 P5.5/R3 R3 P5.4/COM3 P5.3/COM2 P5.2/COM COM P4.2/S39 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 P4.7/S34 P4.6/S35 P4.5/S36 P4.4/S37 P4.3/S38 4 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
pin designation, MSP43x435IPN, MSP43x436IPN, MSP43x437IPN P6./A P6./A RST/NMI TCK PN PACKAGE (TOP VIEW) TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P./TA P./TA/MCLK P.2/TA P.3/TBOUTH/SVSOUT P.4/TBCLK/SMCLK P.5/TACLK/ACLK DV CC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7/SVSIN VREF+ XIN XOUT VeREF+ VREF /VeREF P5./S P5./S P4.7/S2 P4.6/S3 P4.5/S4 P4.4/S5 P4.3/S6 P4.2/S7 P4./S8 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 8 79 78 77 76 75 74 73 72 7 7 69 68 67 66 65 64 63 62 6 6 59 58 57 56 55 54 53 MSP43F435IPN 52 MSP43F436IPN 5 MSP43F437IPN 5 49 48 47 46 45 44 43 42 2 4 2 22 23 24 25 26 27 28 29 3 3 32 33 34 35 36 37 38 39 4 P.7/CA P2./TA2 P2./TB P2.2/TB P2.3/TB2 P2.4/UTXD P2.5/URXD DV SS2 DV CC2 P5.7/R33 P5.6/R23 P5.5/R3 R3 P5.4/COM3 P5.3/COM2 P5.2/COM COM P3./STE/S3 P3./SIMO/S3 P3.2/SOMI/S29 P4./S9 S S S2 S3 S4 S5 S6 S7 P2.7/ADC2CLK/S8 P2.6/CAOUT/S9 S2 S2 S22 S23 P3.7/S24 P3.6/S25 P3.5/S26 P3.4/S27 P3.3/UCLK/S28 P.6/CA AV CC DV SS AV SS P6.2/A2 POST OFFICE BOX 65533 DALLAS, TEXAS 75265 5
pin designation, MSP43x435IPZ, MSP43x436IPZ, MSP43x437IPZ PZ PACKAGE (TOP VIEW) AV CC DV SS AV SS P6.2/A2 P6./A P6./A RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P./TA P./TA/MCLK P.2/TA P.3/TBOUTH/SVSOUT P.4/TBCLK/SMCLK P.5/TACLK/ACLK P.6/CA P.7/CA P2./TA2 P2./TB P2.2/TB P2.3/TB2 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 25 99 98 97 96 95 94 93 92 9 9 89 88 87 86 85 84 83 82 8 8 79 78 77 76 75 74 73 72 7 7 69 68 67 66 65 64 63 62 6 6 59 58 57 56 55 54 53 52 5 26 27 28 29 3 3 32 33 34 35 36 37 38 39 4 4 42 43 44 45 46 47 48 49 5 DV CC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7/SVSIN VREF+ XIN XOUT VeREF+ VREF /VeREF P5./S P5./S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 MSP43F435IPZ MSP43F436IPZ MSP43F437IPZ P2.4/UTXD P2.5/URXD P2.6/CAOUT P2.7/ADC2CLK P3./STE P3./SIMO P3.2/SOMI P3.3/UCLK P3.4 P3.5 P3.6 P3.7 P4. P4. DV SS2 DV CC2 P5.7/R33 P5.6/R23 P5.5/R3 R3 P5.4/COM3 P5.3/COM2 P5.2/COM COM P4.2/S39 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 P4.7/S34 P4.6/S35 P4.5/S36 P4.4/S37 P4.3/S38 6 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
pin designation, MSP43x448IPZ, MSP43x449IPZ PZ PACKAGE (TOP VIEW) AV CC DV SS AV SS P6.2 P6. P6. RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P./TA P./TA/MCLK P.2/TA P.3/TBOUTH/SVSOUT P.4/TBCLK/SMCLK P.5/TACLK/ACLK P.6/CA P.7/CA P2./TA2 P2./TB P2.2/TB P2.3/TB2 DV CC P6.3 P6.4 P6.5 P6.6 P6.7/SVSIN Reserved XIN XOUT DV SS DV SS P5./S P5./S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 25 99 98 97 96 95 94 93 92 9 9 89 88 87 86 85 84 83 82 8 8 79 78 77 76 75 74 73 72 7 7 69 68 67 66 65 64 63 62 6 6 59 58 57 56 55 54 53 52 5 26 27 28 29 3 3 32 33 34 35 36 37 38 39 4 4 42 43 44 45 46 47 48 49 5 MSP43F448IPZ MSP43F449IPZ P2.4/UTXD P2.5/URXD P2.6/CAOUT P2.7 P3./STE P3./SIMO P3.2/SOMI P3.3/UCLK P3.4/TB3 P3.5/TB4 P3.6/TB5 P3.7/TB6 P4./UTXD P4./URXD DV SS2 DV CC2 P5.7/R33 P5.6/R23 P5.5/R3 R3 P5.4/COM3 P5.3/COM2 P5.2/COM COM P4.2/STE/S39 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 P4.7/S34 P4.6/S35 P4.5/UCLK/S36 P4.4/SOMI/S37 4.3/SIMO/S38 POST OFFICE BOX 65533 DALLAS, TEXAS 75265 7
pin designation, MSP43x447IPZ, MSP43x448IPZ, MSP43x449IPZ PZ PACKAGE (TOP VIEW) AV CC DV SS AV SS P6.2/A2 P6./A P6./A RST/NMI TCK TMS TDI/TCLK TDO/TDI XT2IN XT2OUT P./TA P./TA/MCLK P.2/TA P.3/TBOUTH/SVSOUT P.4/TBCLK/SMCLK P.5/TACLK/ACLK P.6/CA P.7/CA P2./TA2 P2./TB P2.2/TB P2.3/TB2 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 25 99 98 97 96 95 94 93 92 9 9 89 88 87 86 85 84 83 82 8 8 79 78 77 76 75 74 73 72 7 7 69 68 67 66 65 64 63 62 6 6 59 58 57 56 55 54 53 52 5 26 27 28 29 3 3 32 33 34 35 36 37 38 39 4 4 42 43 44 45 46 47 48 49 5 DV CC P6.3/A3 P6.4/A4 P6.5/A5 P6.6/A6 P6.7/A7/SVSIN VREF+ XIN XOUT VeREF+ VREF /VeREF P5./S P5./S S2 S3 S4 S5 S6 S7 S8 S9 S S S2 S3 MSP43F447IPZ MSP43F448IPZ MSP43F449IPZ P2.4/UTXD P2.5/URXD P2.6/CAOUT P2.7/ADC2CLK P3./STE P3./SIMO P3.2/SOMI P3.3/UCLK P3.4/TB3 P3.5/TB4 P3.6/TB5 P3.7/TB6 P4./UTXD P4./URXD DV SS2 DV CC2 P5.7/R33 P5.6/R23 P5.5/R3 R3 P5.4/COM3 P5.3/COM2 P5.2/COM COM P4.2/STE/S39 S4 S5 S6 S7 S8 S9 S2 S2 S22 S23 S24 S25 S26 S27 S28 S29 S3 S3 S32 S33 P4.7/S34 P4.6/S35 P4.5/UCLK/S36 P4.4/SOMI/S37 4.3/SIMO/S38 8 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
MSP43x43x functional block diagram XIN XOUT DV CC/2 DV SS/2 AV CC AV SS P 8 P2 8 P3 8 P4 8 P5 8 P6 8 XT2IN XT2OUT Oscillator FLL+ MCLK ACLK SMCLK Flash 32KB 24KB 6KB RAM KB 52B Port 8 I/O Interrupt Capability Port 2 8 I/O Interrupt Capability Port 3 8 I/O Port 4 8 I/O Port 5 8 I/O Port 6 6 I/O USART UART Mode SPI Mode 8 MHz CPU incl. 6 Registers MAB MDB Emulation Module JTAG Interface POR/ SVS/ Brownout Watchdog Timer WDT 5/6-Bit Timer_B3 3 CC Reg Shadow Reg Timer_A3 3 CC Reg Comparator_ A Basic Timer Interrupt Vector f LCD LCD 28/6 Segments,2,3,4 MUX RST/NMI MSP43x43x functional block diagram XIN XOUT DV CC/2 DV SS/2 AV CC AV SS P 8 P2 8 P3 8 P4 8 P5 8 P6 8 XT2IN XT2OUT Oscillator FLL+ MCLK ACLK SMCLK Flash 32KB 24KB 6KB RAM KB 52B Port 8 I/O Interrupt Capability Port 2 8 I/O Interrupt Capability Port 3 8 I/O Port 4 8 I/O Port 5 8 I/O Port 6 6 I/O USART UART Mode SPI Mode 8 MHz CPU incl. 6 Registers MAB MDB Emulation Module JTAG Interface POR/ SVS/ Brownout ADC2 2-Bit 8 Channels <µs Conv. Watchdog Timer WDT 5/6-Bit Timer_B3 3 CC Reg Shadow Reg Timer_A3 3 CC Reg Comparator_ A Basic Timer Interrupt Vector f LCD LCD 28/6 Segments,2,3,4 MUX RST/NMI POST OFFICE BOX 65533 DALLAS, TEXAS 75265 9
MSP43x44x functional block diagram XIN XOUT DV CC/2 DV SS/2 AV CC AV SS P 8 P2 8 P3 8 P4 8 P5 8 P6 8 XT2IN XT2OUT Oscillator FLL+ MCLK ACLK SMCLK Flash 6KB 48KB RAM 2KB Port 8 I/O Interrupt Capability Port 2 8 I/O Interrupt Capability Port 3 8 I/O Port 4 8 I/O Port 5 8 I/O Port 6 6 I/O USART USART UART Mode SPI Mode 8 MHz CPU incl. 6 Registers MAB MDB Emulation Module JTAG Interface Hardware Multiplier MPY, MPYS MAC,MACS POR/ SVS/ Brownout Watchdog Timer WDT 5/6-Bit Timer_B7 7 CC Reg Shadow Reg Timer_A3 3 CC Reg Comparator_ A Basic Timer Interrupt Vector f LCD LCD 6 Segments,2,3,4 MUX RST/NMI MSP43x44x functional block diagram XIN XOUT DV CC/2 DV SS/2 AV CC AV SS P 8 P2 8 P3 8 P4 8 P5 8 P6 8 XT2IN XT2OUT Oscillator FLL+ MCLK ACLK SMCLK Flash 6KB 48KB 32KB RAM 2KB KB Port 8 I/O Interrupt Capability Port 2 8 I/O Interrupt Capability Port 3 8 I/O Port 4 8 I/O Port 5 8 I/O Port 6 6 I/O USART USART UART Mode SPI Mode 8 MHz CPU incl. 6 Registers MAB MDB Emulation Module JTAG Interface Hardware Multiplier MPY, MPYS MAC,MACS POR/ SVS/ Brownout ADC2 2-Bit 8 Channels <µs Conv. Watchdog Timer WDT 5/6-Bit Timer_B7 7 CC Reg Shadow Reg Timer_A3 3 CC Reg Comparator_ A Basic Timer Interrupt Vector f LCD LCD 6 Segments,2,3,4 MUX RST/NMI POST OFFICE BOX 65533 DALLAS, TEXAS 75265
NAME PN NO. TERMINAL I/O NAME MSP43x43x Terminal Functions PZ NO. I/O DESCRIPTION DV CC DV CC Digital supply voltage, positive terminal. P6.3 2 I/O P6.3 2 I/O General-purpose digital I/O P6.4 3 I/O P6.4 3 I/O General-purpose digital I/O P6.5 4 I/O P6.5 4 I/O General-purpose digital I/O P6.6 5 I/O P6.6 5 I/O General-purpose digital I/O P6.7/SVSIN 6 I/O P6.7/SVSIN 6 I/O General-purpose digital I/O / input to brownout, supply voltage supervisor Reserved 7 Reserved 7 Reserved, do not connect externally XIN 8 I XIN 8 I Input port for crystal oscillator XT. Standard or watch crystals can be connected. XOUT 9 O XOUT 9 O Output terminal of crystal oscillator XT DV SS I DV SS I Connect to DV SS DV SS I DV SS I Connect to DV SS P5./S 2 I/O P5./S 2 I/O General-purpose digital I/O / LCD segment output P5./S 3 I/O P5./S 3 I/O General-purpose digital I/O / LCD segment output P4.7/S2 4 I/O S2 4 O General-purpose digital I/O / LCD segment output 2 P4.6/S3 5 I/O S3 5 O General-purpose digital I/O / LCD segment output 3 P4.5/S4 6 I/O S4 6 O General-purpose digital I/O / LCD segment output 4 P4.4/S5 7 I/O S5 7 O General-purpose digital I/O / LCD segment output 5 P4.3/S6 8 I/O S6 8 O General-purpose digital I/O / LCD segment output 6 P4.2/S7 9 I/O S7 9 O General-purpose digital I/O / LCD segment output 7 P4./S8 2 I/O S8 2 O General-purpose digital I/O / LCD segment output 8 P4./S9 2 I/O S9 2 O General-purpose digital I/O / LCD segment output 9 S 22 O S 22 O LCD segment output S 23 O S 23 O LCD segment output S2 24 O S2 24 O LCD segment output 2 S3 25 O S3 25 O LCD segment output 3 S4 26 O S4 26 O LCD segment output 4 S5 27 O S5 27 O LCD segment output 5 S6 28 O S6 28 O LCD segment output 6 S7 29 O S7 29 O LCD segment output 7 P2.7/S8 3 I/O S8 3 O General-purpose digital I/O / LCD segment output 8 P2.6/CAOUT/S9 3 I/O S9 3 O General-purpose digital I/O / Comparator_A output / LCD segment output 9 S2 32 O S2 32 O LCD segment output 2 S2 33 O S2 33 O LCD segment output 2 S22 34 O S22 34 O LCD segment output 22 S23 35 O S23 35 O LCD segment output 23 P3.7/S24 36 I/O S24 36 O General-purpose digital I/O / LCD segment output 24 P3.6/S25 37 I/O S25 37 O General-purpose digital I/O / LCD segment output 25 P3.5/S26 38 I/O S26 38 O General-purpose digital I/O / LCD segment output 26 P3.4/S27 39 I/O S27 39 O General-purpose digital I/O / LCD segment output 27 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
NAME PN NO. TERMINAL I/O MSP43x43x Terminal Functions (Continued) NAME PZ NO. I/O DESCRIPTION P3.3/UCLK/S28 4 I/O S28 4 O General-purpose digital I/O / ext. clock i/p USART/UART or SPI mode, clock o/p USART/SPI mode / LCD segment output 28 P3.2/SOMI/S29 4 I/O S29 4 O General-purpose digital I/O / slave out/master in of USART/SPI mode / LCD segment output 29 P3./SIMO/S3 42 I/O S3 42 O General-purpose digital I/O / slave out/master out of USART/SPI mode / LCD segment output 3 P3./STE/S3 43 I/O S3 43 O General-purpose digital I/O / slave transmit enable-usart/spi mode / LCD segment output 3 S32 44 O LCD segment output 32 S33 45 O LCD segment output 33 P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34 P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35 P4.5/S36 48 I/O General-purpose digital I/O / LCD segment output 36 P4.4/S37 49 I/O General-purpose digital I/O / LCD segment output 37 P4.3/S38 5 I/O General-purpose digital I/O / LCD segment output 38 P4.2/S39 5 I/O General-purpose digital I/O / LCD segment output 39 COM 44 O COM 52 O COM 3 are used for LCD backplanes. P5.2/COM 45 I/O P5.2/COM 53 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. P5.3/COM2 46 I/O P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. P5.4/COM3 47 I/O P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. R3 48 I R3 56 I Input port of fourth positive (lowest) analog LCD level (V5) P5.5/R3 49 I/O P5.5/R3 57 I/O General-purpose digital I/O / input port of third most positive analog LCD level (V4 or V3) P5.6/R23 5 I/O P5.6/R23 58 I/O General-purpose digital I/O / input port of second most positive analog LCD level (V2) P5.7/R33 5 I/O P5.7/R33 59 I/O General-purpose digital I/O / output port of most positive analog LCD level (V) DV CC2 52 DV CC2 6 Digital supply voltage, positive terminal. DV SS2 53 DV SS2 6 Digital supply voltage, negative terminal. P4. 62 I/O General-purpose digital I/O P4. 63 I/O General-purpose digital I/O P3.7 64 I/O General-purpose digital I/O P3.6 65 I/O General-purpose digital I/O P3.5 66 I/O General-purpose digital I/O P3.4 67 I/O General-purpose digital I/O P3.3/UCLK 68 I/O General-purpose digital I/O / external clock input USART/UART or SPI mode, clock output USART/SPI mode P3.2/SOMI 69 I/O General-purpose digital I/O / slave out/master in of USART/SPI mode P3./SIMO 7 I/O General-purpose digital I/O / slave in/master out of USART/SPI mode P3./STE 7 I/O General-purpose digital I/O / slave transmit enable USART/SPI mode P2.7 72 I/O General-purpose digital I/O P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output P2.5/URXD 54 I/O P2.5/URXD 74 I/O General-purpose digital I/O / receive data in USART/UART mode 2 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
NAME PN NO. TERMINAL I/O MSP43x43x Terminal Functions (Continued) NAME PZ NO. I/O DESCRIPTION P2.4/UTXD 55 I/O P2.4/UTXD 75 I/O General-purpose digital I/O / transmit data out USART/UART mode P2.3/TB2 56 I/O P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B3 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output P2.2/TB 57 I/O P2.2/TB 77 I/O General-purpose digital I/O / Timer_B3 CCR. Capture: CCIA/CCIB input, compare: Out output P2./TB 58 I/O P2./TB 78 I/O General-purpose digital I/O / Timer_B3 CCR. Capture: CCIA/CCIB input, compare: Out output P2./TA2 59 I/O P2./TA2 79 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output P.7/CA 6 I/O P.7/CA 8 I/O General-purpose digital I/O / Comparator_A input P.6/CA 6 I/O P.6/CA 8 I/O General-purpose digital I/O / Comparator_A input P.5/TACLK/ ACLK P.4/TBCLK/ SMCLK P.3/TBOUTH/ SVSOUT 62 I/O P.5/TACLK/ ACLK 63 I/O P.4/TBCLK/ SMCLK 64 I/O P.3/TBOUTH/ SVSOUT 82 I/O 83 I/O 84 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by, 2, 4, or 8) General-purpose digital I/O / input clock TBCLK Timer_B3 / submain system clock SMCLK output General-purpose digital I/O / switch all PWM digital output ports to high impedance Timer_B3 TB to TB2 / SVS: output of SVS comparator P.2/TA 65 I/O P.2/TA 85 I/O General-purpose digital I/O / Timer_A, Capture: CCIA input, compare: Out output P./TA/MCLK 66 I/O P./TA/MCLK 86 I/O General-purpose digital I/O / Timer_A. Capture: CCIB input / MCLK output. Note: TA is only an input on this pin / BSL receive P./TA 67 I/O P./TA 87 I/O General-purpose digital I/O / Timer_A. Capture: CCIA input, compare: Out output / BSL transmit XT2OUT 68 O XT2OUT 88 O Output terminal of crystal oscillator XT2 XT2IN 69 I XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be connected. TDO/TDI 7 I/O TDO/TDI 9 I/O Test data output port. TDO/TDI data output or programming data input terminal TDI/TCLK 7 I TDI/TCLK 9 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TMS 72 I TMS 92 I Test mode select. TMS is used as an input port for device programming and test. TCK 73 I TCK 93 I Test clock. TCK is the clock input port for device programming and test. RST/NMI 74 I RST/NMI 94 I General-purpose digital I/O / reset input or nonmaskable interrupt input port P6. 75 I/O P6. 95 I/O General-purpose digital I/O P6. 76 I/O P6. 96 I/O General-purpose digital I/O P6.2 77 I/O P6.2 97 I/O General-purpose digital I/O AV SS 78 AV SS 98 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_a, port, and LCD resistive divider circuitry. DV SS 79 DV SS 99 Digital supply voltage, negative terminal. AV CC 8 AV CC Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_a, port, and LCD resistive divider circuitry; must not power up prior to DV CC /DV CC2. POST OFFICE BOX 65533 DALLAS, TEXAS 75265 3
NAME PN NO. TERMINAL I/O NAME MSP43x43x Terminal Functions PZ NO. I/O DESCRIPTION DV CC DV CC Digital supply voltage, positive terminal. P6.3/A3 2 I/O P6.3/A3 2 I/O General-purpose digital I/O / analog input a3 2-bit ADC P6.4/A4 3 I/O P6.4/A4 3 I/O General-purpose digital I/O / analog input a4 2-bit ADC P6.5/A5 4 I/O P6.5/A5 4 I/O General-purpose digital I/O / analog input a5 2-bit ADC P6.6/A6 5 I/O P6.6/A6 5 I/O General-purpose digital I/O / analog input a6 2-bit ADC P6.7/A7/SVSIN 6 I/O P6.7/A7/SVSIN 6 I/O General-purpose digital I/O / analog input a7 2-bit ADC, analog / input to brownout, supply voltage supervisor V REF+ 7 O V REF+ 7 O Output of positive terminal of the reference voltage in the ADC XIN 8 I XIN 8 I Input port for crystal oscillator XT. Standard or watch crystals can be connected. XOUT 9 O XOUT 9 O Output terminal of crystal oscillator XT Ve REF+ I Ve REF+ I Input for an external reference voltage to the ADC V REF /Ve REF I V REF /Ve REF I Negative terminal for the ADC s reference voltage for both sources, the internal reference voltage, or an external applied reference voltage. P5./S 2 I/O P5./S 2 I/O General-purpose digital I/O / LCD segment output P5./S 3 I/O P5./S 3 I/O General-purpose digital I/O / LCD segment output P4.7/S2 4 I/O S2 4 O General-purpose digital I/O / LCD segment output 2 P4.6/S3 5 I/O S3 5 O General-purpose digital I/O / LCD segment output 3 P4.5/S4 6 I/O S4 6 O General-purpose digital I/O / LCD segment output 4 P4.4/S5 7 I/O S5 7 O General-purpose digital I/O / LCD segment output 5 P4.3/S6 8 I/O S6 8 O General-purpose digital I/O / LCD segment output 6 P4.2/S7 9 I/O S7 9 O General-purpose digital I/O / LCD segment output 7 P4./S8 2 I/O S8 2 O General-purpose digital I/O / LCD segment output 8 P4./S9 2 I/O S9 2 O General-purpose digital I/O / LCD segment output 9 S 22 O S 22 O LCD segment output S 23 O S 23 O LCD segment output S2 24 O S2 24 O LCD segment output 2 S3 25 O S3 25 O LCD segment output 3 S4 26 O S4 26 O LCD segment output 4 S5 27 O S5 27 O LCD segment output 5 S6 28 O S6 28 O LCD segment output 6 S7 29 O S7 29 O LCD segment output 7 P2.7/ADC2CLK/ S8 3 I/O S8 3 O General-purpose digital I/O / conversion clock 2-bit ADC / LCD segment output 8 General-purpose digital I/O / Comparator_A output / LCD segment output 9 P2.6/CAOUT/S9 3 I/O S9 3 O S2 32 O S2 32 O LCD segment output 2 S2 33 O S2 33 O LCD segment output 2 S22 34 O S22 34 O LCD segment output 22 S23 35 O S23 35 O LCD segment output 23 P3.7/S24 36 I/O S24 36 O General-purpose digital I/O / LCD segment output 24 P3.6/S25 37 I/O S25 37 O General-purpose digital I/O / LCD segment output 25 P3.5/S26 38 I/O S26 38 O General-purpose digital I/O / LCD segment output 26 P3.4/S27 39 I/O S27 39 O General-purpose digital I/O / LCD segment output 27 4 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
NAME PN NO. TERMINAL I/O MSP43x43x Terminal Functions (Continued) NAME PZ NO. I/O DESCRIPTION P3.3/UCLK/S28 4 I/O S28 4 O General-purpose digital I/O / ext. clock i/p USART/UART or SPI mode, clock o/p USART/SPI mode / LCD segment output 28 P3.2/SOMI/S29 4 I/O S29 4 O General-purpose digital I/O / slave out/master in of USART/SPI mode / LCD segment output 29 P3./SIMO/S3 42 I/O S3 42 O General-purpose digital I/O / slave out/master out of USART/SPI mode / LCD segment output 3 P3./STE/S3 43 I/O S3 43 O General-purpose digital I/O / slave transmit enable-usart/spi mode / LCD segment output 3 S32 44 O LCD segment output 32 S33 45 O LCD segment output 33 P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34 P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35 P4.5/S36 48 I/O General-purpose digital I/O / LCD segment output 36 P4.4/S37 49 I/O General-purpose digital I/O / LCD segment output 37 P4.3/S38 5 I/O General-purpose digital I/O / LCD segment output 38 P4.2/S39 5 I/O General-purpose digital I/O / LCD segment output 39 COM 44 O COM 52 O COM 3 are used for LCD backplanes. P5.2/COM 45 I/O P5.2/COM 53 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. P5.3/COM2 46 I/O P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. P5.4/COM3 47 I/O P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. R3 48 I R3 56 I Input port of fourth positive (lowest) analog LCD level (V5) P5.5/R3 49 I/O P5.5/R3 57 I/O General-purpose digital I/O / input port of third most positive analog LCD level (V4 or V3) P5.6/R23 5 I/O P5.6/R23 58 I/O General-purpose digital I/O / input port of second most positive analog LCD level (V2) P5.7/R33 5 I/O P5.7/R33 59 I/O General-purpose digital I/O / output port of most positive analog LCD level (V) DV CC2 52 DV CC2 6 Digital supply voltage, positive terminal. DV SS2 53 DV SS2 6 Digital supply voltage, negative terminal. P4. 62 I/O General-purpose digital I/O P4. 63 I/O General-purpose digital I/O P3.7 64 I/O General-purpose digital I/O P3.6 65 I/O General-purpose digital I/O P3.5 66 I/O General-purpose digital I/O P3.4 67 I/O General-purpose digital I/O P3.3/UCLK 68 I/O General-purpose digital I/O / external clock input USART/UART or SPI mode, clock output USART/SPI mode P3.2/SOMI 69 I/O General-purpose digital I/O / slave out/master in of USART/SPI mode P3./SIMO 7 I/O General-purpose digital I/O / slave in/master out of USART/SPI mode P3./STE 7 I/O General-purpose digital I/O / slave transmit enable USART/SPI mode P2.7/ADC2CLK 72 I/O General-purpose digital I/O / conversion clock 2-bit ADC P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output P2.5/URXD 54 I/O P2.5/URXD 74 I/O General-purpose digital I/O / receive data in USART/UART mode POST OFFICE BOX 65533 DALLAS, TEXAS 75265 5
NAME PN NO. TERMINAL I/O MSP43x43x Terminal Functions (Continued) NAME PZ NO. I/O DESCRIPTION P2.4/UTXD 55 I/O P2.4/UTXD 75 I/O General-purpose digital I/O / transmit data out USART/UART mode P2.3/TB2 56 I/O P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B3 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output P2.2/TB 57 I/O P2.2/TB 77 I/O General-purpose digital I/O / Timer_B3 CCR. Capture: CCIA/CCIB input, compare: Out output P2./TB 58 I/O P2./TB 78 I/O General-purpose digital I/O / Timer_B3 CCR. Capture: CCIA/CCIB input, compare: Out output P2./TA2 59 I/O P2./TA2 79 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output P.7/CA 6 I/O P.7/CA 8 I/O General-purpose digital I/O / Comparator_A input P.6/CA 6 I/O P.6/CA 8 I/O General-purpose digital I/O / Comparator_A input P.5/TACLK/ ACLK P.4/TBCLK/ SMCLK P.3/TBOUTH/ SVSOUT 62 I/O P.5/TACLK/ ACLK 63 I/O P.4/TBCLK/ SMCLK 64 I/O P.3/TBOUTH/ SVSOUT 82 I/O 83 I/O 84 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by, 2, 4, or 8) General-purpose digital I/O / input clock TBCLK Timer_B3 / submain system clock SMCLK output General-purpose digital I/O / switch all PWM digital output ports to high impedance Timer_B3 TB to TB2 / SVS: output of SVS comparator P.2/TA 65 I/O P.2/TA 85 I/O General-purpose digital I/O / Timer_A, Capture: CCIA input, compare: Out output P./TA/MCLK 66 I/O P./TA/MCLK 86 I/O General-purpose digital I/O / Timer_A. Capture: CCIB input / MCLK output. Note: TA is only an input on this pin / BSL receive P./TA 67 I/O P./TA 87 I/O General-purpose digital I/O / Timer_A. Capture: CCIA input, compare: Out output / BSL transmit XT2OUT 68 O XT2OUT 88 O Output terminal of crystal oscillator XT2 XT2IN 69 I XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be connected. TDO/TDI 7 I/O TDO/TDI 9 I/O Test data output port. TDO/TDI data output or programming data input terminal TDI/TCLK 7 I TDI/TCLK 9 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TMS 72 I TMS 92 I Test mode select. TMS is used as an input port for device programming and test. TCK 73 I TCK 93 I Test clock. TCK is the clock input port for device programming and test. RST/NMI 74 I RST/NMI 94 I General-purpose digital I/O / reset input or nonmaskable interrupt input port P6./A 75 I/O P6./A 95 I/O General-purpose digital I/O / analog input a 2-bit ADC P6./A 76 I/O P6./A 96 I/O General-purpose digital I/O / analog input a 2-bit ADC P6.2/A2 77 I/O P6.2/A2 97 I/O General-purpose digital I/O / analog input a2 2-bit ADC AV SS 78 AV SS 98 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_a, ADC2, port, and LCD resistive divider circuitry. DV SS 79 DV SS 99 Digital supply voltage, negative terminal. AV CC 8 AV CC Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_a, ADC2, port, and LCD resistive divider circuitry; must not power up prior to DV CC /DV CC2. 6 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
TERMINAL NAME NO. I/O MSP43x44x Terminal Functions DV CC Digital supply voltage, positive terminal. P6.3 2 I/O General-purpose digital I/O P6.4 3 I/O General-purpose digital I/O P6.5 4 I/O General-purpose digital I/O P6.6 5 I/O General-purpose digital I/O DESCRIPTION P6.7/SVSIN 6 I/O General-purpose digital I/O / analog input to brownout, supply voltage supervisor Reserved 7 O Reserved, do not connect externally XIN 8 I Input port for crystal oscillator XT. Standard or watch crystals can be connected. XOUT 9 O Output terminal of crystal oscillator XT DV SS I Connect to DV SS DV SS I Connect to DV SS P5./S 2 I/O General-purpose digital I/O / LCD segment output P5./S 3 I/O General-purpose digital I/O / LCD segment output S2 4 O LCD segment output 2 S3 5 O LCD segment output 3 S4 6 O LCD segment output 4 S5 7 O LCD segment output 5 S6 8 O LCD segment output 6 S7 9 O LCD segment output 7 S8 2 O LCD segment output 8 S9 2 O LCD segment output 9 S 22 O LCD segment output S 23 O LCD segment output S2 24 O LCD segment output 2 S3 25 O LCD segment output 3 S4 26 O LCD segment output 4 S5 27 O LCD segment output 5 S6 28 O LCD segment output 6 S7 29 O LCD segment output 7 S8 3 O LCD segment output 8 S9 3 O LCD segment output 9 S2 32 O LCD segment output 2 S2 33 O LCD segment output 2 S22 34 O LCD segment output 22 S23 35 O LCD segment output 23 S24 36 O LCD segment output 24 S25 37 O LCD segment output 25 S26 38 O LCD segment output 26 S27 39 O LCD segment output 27 S28 4 O LCD segment output 28 POST OFFICE BOX 65533 DALLAS, TEXAS 75265 7
TERMINAL NAME MSP43x44x Terminal Functions (Continued) PN I/O DESCRIPTION NO. S29 4 O LCD segment output 29 S3 42 O LCD segment output 3 S3 43 O LCD segment output 3 S32 44 O LCD segment output 32 S33 45 O LCD segment output 33 P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34 P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35 P4.5/UCLK/S36 48 I/O General-purpose digital I/O / external clock input USART/UART or SPI mode, clock output USART/SPI MODE / LCD segment output 36 P4.4/SOMI/S37 49 I/O General-purpose digital I/O / slave out/master in of USART/SPI mode / LCD segment output 37 P4.3/SIMO/S38 5 I/O General-purpose digital I/O / slave in/master out of USART/SPI mode / LCD segment output 38 P4.2/STE/S39 5 I/O General-purpose digital I/O / slave transmit enable USART/SPI mode / LCD segment output 39 COM 52 O COM 3 are used for LCD backplanes. P5.2/COM 53 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. R3 56 I Input port of fourth positive (lowest) analog LCD level (V5) P5.5/R3 57 I/O General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3) P5.6/R23 58 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2) P5.7/R33 59 I/O General-purpose digital I/O / Output port of most positive analog LCD level (V) DV CC2 6 Digital supply voltage, positive terminal. DV SS2 6 Digital supply voltage, negative terminal. P4./URXD 62 I/O General-purpose digital I/O / receive data in USART/UART mode P4./UTXD 63 I/O General-purpose digital I/O / transmit data out USART/UART mode P3.7/TB6 64 I/O General-purpose digital I/O / Timer_B7 CCR6 / Capture: CCI6A/CCI6B input, compare: Out6 output P3.6/TB5 65 I/O General-purpose digital I/O / Timer_B7 CCR5 / Capture: CCI5A/CCI5B input, compare: Out5 output P3.5/TB4 66 I/O General-purpose digital I/O / Timer_B7 CCR4 / Capture: CCI4A/CCI4B input, compare: Out4 output P3.4/TB3 67 I/O General-purpose digital I/O / Timer_B7 CCR3 / Capture: CCI3A/CCI3B input, compare: Out3 output P3.3/UCLK 68 I/O General-purpose digital I/O / external clock input USART/UART or SPI mode, clock output USART/SPI mode P3.2/SOMI 69 I/O General-purpose digital I/O / slave out/master in of USART/SPI mode P3./SIMO 7 I/O General-purpose digital I/O / slave in/master out of USART/SPI mode P3./STE 7 I/O General-purpose digital I/O / slave transmit enable USART/SPI mode P2.7 72 I/O General-purpose digital I/O P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output P2.5/URXD 74 I/O General-purpose digital I/O / receive data in USART/UART mode P2.4/UTXD 75 I/O General-purpose digital I/O / transmit data out USART/UART mode P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output P2.2/TB 77 I/O General-purpose digital I/O / Timer_B7 CCR. Capture: CCIA/CCIB input, compare: Out output P2./TB 78 I/O General-purpose digital I/O / Timer_B7 CCR. Capture: CCIA/CCIB input, compare: Out output P2./TA2 79 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output P.7/CA 8 I/O General-purpose digital I/O / Comparator_A input 8 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
TERMINAL NAME MSP43x44x Terminal Functions (Continued) PN I/O DESCRIPTION NO. P.6/CA 8 I/O General-purpose digital I/O / Comparator_A input P.5/TACLK/ ACLK P.4/TBCLK/ SMCLK P.3/TBOUTH/ SVSOUT 82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by, 2, 4, or 8) 83 I/O General-purpose digital I/O / input clock TBCLK Timer_B7 / submain system clock SMCLK output 84 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance Timer_B7 TB to TB6 / SVS: output of SVS comparator P.2/TA 85 I/O General-purpose digital I/O / Timer_A, Capture: CCIA input, compare: Out output P./TA/MCLK 86 I/O General-purpose digital I/O / Timer_A. Capture: CCIB input / MCLK output. Note: TA is only an input on this pin / BSL receive P./TA 87 I/O General-purpose digital I/O / Timer_A. Capture: CCIA input, compare: Out output / BSL transmit XT2OUT 88 O Output terminal of crystal oscillator XT2 XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be connected. TDO/TDI 9 I/O Test data output port. TDO/TDI data output or programming data input terminal TDI/TCLK 9 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TMS 92 I Test mode select. TMS is used as an input port for device programming and test. TCK 93 I Test clock. TCK is the clock input port for device programming and test. RST/NMI 94 I Reset input or nonmaskable interrupt input port P6. 95 I/O General-purpose digital I/O P6. 96 I/O General-purpose digital I/O P6.2 97 I/O General-purpose digital I/O AV SS 98 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_a, port, and LCD resistive divider circuitry. DV SS 99 Digital supply voltage, negative terminal. AV CC Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_a, port, and LCD resistive divider circuitry; must not power up prior to DV CC /DV CC2. POST OFFICE BOX 65533 DALLAS, TEXAS 75265 9
TERMINAL NAME NO. I/O MSP43x44x Terminal Functions DV CC Digital supply voltage, positive terminal. DESCRIPTION P6.3/A3 2 I/O General-purpose digital I/O / analog input a3 2-bit ADC P6.4/A4 3 I/O General-purpose digital I/O / analog input a4 2-bit ADC P6.5/A5 4 I/O General-purpose digital I/O / analog input a5 2-bit ADC P6.6/A6 5 I/O General-purpose digital I/O / analog input a6 2-bit ADC P6.7/A7/SVSIN 6 I/O General-purpose digital I/O / analog input a7 2-bit ADC / analog input to brownout, supply voltage supervisor V REF+ 7 O Output of positive terminal of the reference voltage in the ADC XIN 8 I Input port for crystal oscillator XT. Standard or watch crystals can be connected. XOUT 9 O Output terminal of crystal oscillator XT Ve REF+ I Input for an external reference voltage to the ADC V REF /Ve REF I Negative terminal for the ADC s reference voltage for both sources, the internal reference voltage, or an external applied reference voltage P5./S 2 I/O General-purpose digital I/O / LCD segment output P5./S 3 I/O General-purpose digital I/O / LCD segment output S2 4 O LCD segment output 2 S3 5 O LCD segment output 3 S4 6 O LCD segment output 4 S5 7 O LCD segment output 5 S6 8 O LCD segment output 6 S7 9 O LCD segment output 7 S8 2 O LCD segment output 8 S9 2 O LCD segment output 9 S 22 O LCD segment output S 23 O LCD segment output S2 24 O LCD segment output 2 S3 25 O LCD segment output 3 S4 26 O LCD segment output 4 S5 27 O LCD segment output 5 S6 28 O LCD segment output 6 S7 29 O LCD segment output 7 S8 3 O LCD segment output 8 S9 3 O LCD segment output 9 S2 32 O LCD segment output 2 S2 33 O LCD segment output 2 S22 34 O LCD segment output 22 S23 35 O LCD segment output 23 S24 36 O LCD segment output 24 S25 37 O LCD segment output 25 S26 38 O LCD segment output 26 S27 39 O LCD segment output 27 S28 4 O LCD segment output 28 2 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
TERMINAL NAME MSP43x44x Terminal Functions (Continued) PN I/O DESCRIPTION NO. S29 4 O LCD segment output 29 S3 42 O LCD segment output 3 S3 43 O LCD segment output 3 S32 44 O LCD segment output 32 S33 45 O LCD segment output 33 P4.7/S34 46 I/O General-purpose digital I/O / LCD segment output 34 P4.6/S35 47 I/O General-purpose digital I/O / LCD segment output 35 P4.5/UCLK/S36 48 I/O General-purpose digital I/O / external clock input USART/UART or SPI mode, clock output USART/SPI MODE / LCD segment output 36 P4.4/SOMI/S37 49 I/O General-purpose digital I/O / slave out/master in of USART/SPI mode / LCD segment output 37 P4.3/SIMO/S38 5 I/O General-purpose digital I/O / slave in/master out of USART/SPI mode / LCD segment output 38 P4.2/STE/S39 5 I/O General-purpose digital I/O / slave transmit enable USART/SPI mode / LCD segment output 39 COM 52 O COM 3 are used for LCD backplanes. P5.2/COM 53 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. P5.3/COM2 54 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. P5.4/COM3 55 I/O General-purpose digital I/O / common output, COM 3 are used for LCD backplanes. R3 56 I Input port of fourth positive (lowest) analog LCD level (V5) P5.5/R3 57 I/O General-purpose digital I/O / Input port of third most positive analog LCD level (V4 or V3) P5.6/R23 58 I/O General-purpose digital I/O / Input port of second most positive analog LCD level (V2) P5.7/R33 59 I/O General-purpose digital I/O / Output port of most positive analog LCD level (V) DV CC2 6 Digital supply voltage, positive terminal. DV SS2 6 Digital supply voltage, negative terminal. P4./URXD 62 I/O General-purpose digital I/O / receive data in USART/UART mode P4./UTXD 63 I/O General-purpose digital I/O / transmit data out USART/UART mode P3.7/TB6 64 I/O General-purpose digital I/O / Timer_B7 CCR6 / Capture: CCI6A/CCI6B input, compare: Out6 output P3.6/TB5 65 I/O General-purpose digital I/O / Timer_B7 CCR5 / Capture: CCI5A/CCI5B input, compare: Out5 output P3.5/TB4 66 I/O General-purpose digital I/O / Timer_B7 CCR4 / Capture: CCI4A/CCI4B input, compare: Out4 output P3.4/TB3 67 I/O General-purpose digital I/O / Timer_B7 CCR3 / Capture: CCI3A/CCI3B input, compare: Out3 output P3.3/UCLK 68 I/O General-purpose digital I/O / external clock input USART/UART or SPI mode, clock output USART/SPI mode P3.2/SOMI 69 I/O General-purpose digital I/O / slave out/master in of USART/SPI mode P3./SIMO 7 I/O General-purpose digital I/O / slave in/master out of USART/SPI mode P3./STE 7 I/O General-purpose digital I/O / slave transmit enable USART/SPI mode P2.7/ADC2CLK 72 I/O General-purpose digital I/O / conversion clock 2-bit ADC P2.6/CAOUT 73 I/O General-purpose digital I/O / Comparator_A output P2.5/URXD 74 I/O General-purpose digital I/O / receive data in USART/UART mode P2.4/UTXD 75 I/O General-purpose digital I/O / transmit data out USART/UART mode P2.3/TB2 76 I/O General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output P2.2/TB 77 I/O General-purpose digital I/O / Timer_B7 CCR. Capture: CCIA/CCIB input, compare: Out output P2./TB 78 I/O General-purpose digital I/O / Timer_B7 CCR. Capture: CCIA/CCIB input, compare: Out output P2./TA2 79 I/O General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output P.7/CA 8 I/O General-purpose digital I/O / Comparator_A input POST OFFICE BOX 65533 DALLAS, TEXAS 75265 2
TERMINAL NAME MSP43x44x Terminal Functions (Continued) PN I/O DESCRIPTION NO. P.6/CA 8 I/O General-purpose digital I/O / Comparator_A input P.5/TACLK/ ACLK P.4/TBCLK/ SMCLK P.3/TBOUTH/ SVSOUT 82 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by, 2, 4, or 8) 83 I/O General-purpose digital I/O / input clock TBCLK Timer_B7 / submain system clock SMCLK output 84 I/O General-purpose digital I/O / switch all PWM digital output ports to high impedance Timer_B7 TB to TB6 / SVS: output of SVS comparator P.2/TA 85 I/O General-purpose digital I/O / Timer_A, Capture: CCIA input, compare: Out output P./TA/MCLK 86 I/O General-purpose digital I/O / Timer_A. Capture: CCIB input / MCLK output. Note: TA is only an input on this pin / BSL receive P./TA 87 I/O General-purpose digital I/O / Timer_A. Capture: CCIA input, compare: Out output / BSL transmit XT2OUT 88 O Output terminal of crystal oscillator XT2 XT2IN 89 I Input port for crystal oscillator XT2. Only standard crystals can be connected. TDO/TDI 9 I/O Test data output port. TDO/TDI data output or programming data input terminal TDI/TCLK 9 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK. TMS 92 I Test mode select. TMS is used as an input port for device programming and test. TCK 93 I Test clock. TCK is the clock input port for device programming and test. RST/NMI 94 I Reset input or nonmaskable interrupt input port P6./A 95 I/O General-purpose digital I/O, analog input a 2-bit ADC P6./A 96 I/O General-purpose digital I/O, analog input a 2-bit ADC P6.2/A2 97 I/O General-purpose digital I/O, analog input a2 2-bit ADC AV SS 98 Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, comparator_a, ADC2, port, and LCD resistive divider circuitry. DV SS 99 Digital supply voltage, negative terminal. AV CC Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, comparator_a, ADC2, port, and LCD resistive divider circuitry; must not power up prior to DV CC /DV CC2. 22 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
short-form description CPU The MSP43 CPU has a 6-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. The CPU is integrated with 6 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 5 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table shows examples of the three types of instruction formats; Table 2 shows the address modes. Program Counter Stack Pointer Status Register Constant Generator General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register General-Purpose Register PC/R SP/R SR/CG/R2 CG2/R3 R4 R5 R6 R7 R8 R9 R R R2 R3 R4 R5 Table. Instruction Word Formats Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 > R5 Single operands, destination only e.g. CALL R8 PC >(TOS), R8 > PC Relative jump, un/conditional e.g. JNE Jump-on-equal bit = Table 2. Address Mode Descriptions ADDRESS MODE S D SYNTAX EXAMPLE OPERATION Register MOV Rs,Rd MOV R,R R > R Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) > M(6+R6) Symbolic (PC relative) MOV EDE,TONI M(EDE) > M(TONI) Absolute MOV &MEM,&TCDAT M(MEM) > M(TCDAT) Indirect MOV @Rn,Y(Rm) MOV @R,Tab(R6) M(R) > M(Tab+R6) Indirect autoincrement MOV @Rn+,Rm MOV @R+,R M(R) > R R + 2 > R Immediate MOV #X,TONI MOV #45,TONI #45 > M(TONI) NOTE: S = source D = destination POST OFFICE BOX 65533 DALLAS, TEXAS 75265 23
operating modes The MSP43 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: Active mode (AM) All clocks are active Low-power mode (LPM) CPU is disabled ACLK and SMCLK remain active, MCLK is disabled FLL+ loop control remains active Low-power mode (LPM) CPU is disabled FLL+ loop control is disabled ACLK and SMCLK remain active, MCLK is disabled Low-power mode 2 (LPM2) CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO s dc generator remains enabled ACLK remains active Low-power mode 3 (LPM3) CPU is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO s dc generator is disabled ACLK remains active Low-power mode 4 (LPM4) CPU is disabled ACLK is disabled MCLK, FLL+ loop control, and DCOCLK are disabled DCO s dc generator is disabled Crystal oscillator is stopped 24 POST OFFICE BOX 65533 DALLAS, TEXAS 75265
interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range FFFFh to FFEh. The vector contains the 6-bit address of the appropriate interrupt-handler instruction sequence. Table 3. Interrupt Sources, Flags, and Vectors INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT Power-Up External Reset Watchdog Flash Memory NMI Oscillator Fault Flash Memory Access Violation WDTIFG KEYV (see Note ) NMIIFG (see Notes and 3) OFIFG (see Notes and 3) ACCVIFG (see Notes and 3) WORD ADDRESS PRIORITY Reset FFFEh 5, highest (Non)maskable (Non)maskable (Non)maskable FFFCh 4 Timer_B7 TBCCR CCIFG (see Note 2) Maskable FFFAh 3 Timer_B7 TBCCR to TBCCR6 CCIFGs TBIFG (see Notes and 2) Maskable FFF8h 2 Comparator_A CAIFG Maskable FFF6h Watchdog Timer WDTIFG Maskable FFF4h USART Receive URXIFG Maskable FFF2h 9 USART Transmit UTXIFG Maskable FFFh 8 ADC2 (see Note 4) ADC2IFG (see Notes and 2) Maskable FFEEh 7 Timer_A3 TACCR CCIFG (see Note 2) Maskable FFECh 6 Timer_A3 TACCR and TACCR2 CCIFGs, TAIFG (see Notes and 2) Maskable FFEAh 5 I/O Port P (Eight Flags) PIFG. to PIFG.7 (see Notes and 2) Maskable FFE8h 4 USART Receive URXIFG Maskable FFE6h 3 USART Transmit UTXIFG Maskable FFE4h 2 I/O Port P2 (Eight Flags) P2IFG. to P2IFG.7 (see Notes and 2) Maskable FFE2h Basic Timer BTIFG Maskable FFEh, lowest 43x() uses Timer_B3 with TBCCR, and 2 CCIFG flags, and TBIFG. 44x() uses Timer_B7 with TBCCR CCIFG, TBCCR to TBCCR6 CCIFGs, and TBIFG USART is implemented in 44x() only. NOTES:. Multiple source flags 2. Interrupt flags are located in the module. 3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable it. 4. ADC2 is not implemented in MSP43x43x and MSP43x44x devices. POST OFFICE BOX 65533 DALLAS, TEXAS 75265 25