Optimizing HW/SW Partition of a Complex Embedded Systems. Simon George November 2015.

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Transcription:

Optimizing HW/SW Partition of a Complex Embedded Systems Simon George November 2015

Zynq-7000 All Programmable SoC HP ACP GP Page 2

Zynq UltraScale+ MPSoC Page 3

HW/SW Optimization Challenges application() Func_A() Func_B() Func_C() HW/SW Partition? Processor Func_A Func_B,Func_C Programmable Logic HP Port ACP Port GP Port HW/SW Connectivity? Axi4-Stream DMA Axi4-Full Axi4-Lite Func_A Datamover PS-PL interfaces SW drivers Func_B,Func_C Page 4

Before SDSoC: Connectivity Exploration Met Req? C/C++ SDK Application C SDK, OS Tools PS Driver IPI project IP Integrator Datamover PS-PL interface PL HLS Verilog, VHDL Vivado IP HW-SW partition spec Need to Modify Multiple Levels of Design Entry Page 5

Before SDSoC: HW/SW Partition Exploration Met Req? C/C++ SDK Application C SDK, OS Tools PS Driver IPI project IP Integrator Datamover PS-PL interface PL HLS Verilog, VHDL Vivado IP HW-SW partition spec Involves Multiple Disciplines to Explore Architecture Page 6

SDSoC: Automatic System Generation Met Req? C/C++ Application PS Driver Func_A(); Func_B(); Func_C(); SDSoC Datamover PS-PL interface PL IP Select functions for PL C/C++ Applications to System in hours Page 7

SDSoC: HW Acceleration from C/C++ Applications Performance Estimation C/C++ Applications System-level Profiling Specify Functions for Acceleration Move C/C++ functions to hardware Full system generation including driver and hardware connectivity System-level debug and profile Rapid HW partitioning and exploration Full System Generation Page 8

SDSoC: Embedded C/C++ Applications Programming Experience C/C++ Development Easy to use Eclipse IDE Estimator Compiler Debugger Profiler One click to accelerate functions in Programmable Logic (PL) Optimized libraries Xilinx, ARM and Partners DSP, Video, fixed point, linear algebra, BLAS, OpenCV Support for Linux, FreeRTOS and baremetal Additional OS support in future releases Page 9

SDSoC: System Level Profiling Rapid system performance estimation Full system estimation (programmable logic, data communication, processing system) Reports SW/HW cycle level performance and hardware utilization Automated performance measurement Runtime measurement by instrumentation of cache, memory, and bus utilization Page 10

SDSoC: Full System Optimizing Compiler Rapid software configurable application acceleration using C/C++ Automated function acceleration in programmable logic Up to 100X increase in performance vs software System optimized for latency, bandwidth, and hardware utilization Page 11

Automated Generation of System Connectivity Find the lowest latency 32X32 floating point matrix multiply (latency in processor cycles) Explore system performance and power Rapidly configure, generate macro and micro architectures Explore optimal interconnect and memory interfaces Automatic insertion of AXI-Performance Monitor (APM) to obtain detailed cache/port/memory performance data Shorten development time over traditional Hardware/Software flows Page 12

SDSoC: Productivity Advantage

SDSoC: Supported Development Platforms Start today with: Xilinx development platforms: ZC702 & ZC706, Alliance Member platforms: Zedboard, MicroZed, ZYBO, Zynq SDR, ZC702+HDMI IO, SVDK, any many more Visit http://wwwxilinxcom/products/designtools/softwarezone/sdsochtml#boardskits Customer platform flow supported today (UG1146) Page 14

Custom Platform Creation IP I/O Vivado project I/O HW Metadata IP OS BSPs Software Project SW Metadata Libraries Target customer s own board for production design with SDSoC Add metadata to existing Vivado project and existing Software projects (OS, BSPs and libraries) Page 15

Summary Performance Estimation C/C++ Applications System-level Profiling Specify Functions for Acceleration Move C/C++ functions to hardware Full system generation including driver and hardware connectivity System-level debug and profile Rapid HW partitioning and exploration Full System Generation Page 16

Learn More About SDSoC Xilinxcom/sdsoc 10 Videos 3 User Guides Backgrounder Worldwide ATP Classes Self-guided labs (part of UG1028) Page 17

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