MATLAB/Simulink 기반의프로그래머블 SoC 설계및검증

Transcription

1 MATLAB/Simulink 기반의프로그래머블 SoC 설계및검증 이웅재부장 Application Engineering Group 2014 The MathWorks, Inc. 1

2 Agenda Introduction ZYNQ Design Process Model-Based Design Workflow Prototyping and Verification Processor In the Loop UDP Interface Conclusions 2

3 What is Zynq? ARM Processor Dual Core Cortex -A9 Interface FPGA 7-series fabric New product family from Xilinx All Programmable System on Chip (SoC) FPGA + ARM on one chip Enables high-performance system development Reduces BOM cost over multi-chip solutions 3

4 Zynq Design Challenge ARM Processor C-Code Software Typically programmed in C Often runs a Linux operating system Well-established workflows exist CHALLENGES FPGA Designers not familiar with programming processors What should run on the processor vs. the FPGA? 4

5 Zynq Design Challenge FPGA HDL Code Hardware Typically programmed in VHDL/Verilog Established workflows exist CHALLENGES DSP/Processor programmers not familiar with FPGA Design What should run on the FPGA vs. the processor? 5

6 Zynq Design Challenge Interface Zynq uses standard AXI4 interface between FPGA and ARM CHALLENGES No established rules for hooking up the interface Different versions of AXI interface for different bandwidth requirements 6

7 Zynq Design Challenges ARM Processor C-Code Software Interface FPGA HDL Code Hardware FPGA Designers not familiar with programming processors DSP/Processor programmers not familiar with FPGAs What should run on the FPGA vs. what should run on the ARM? No established rules for hooking up the interface between FPGA and ARM processor 7

8 How can I address these challenges and get my project onto Zynq quickly? Model-Based Design provides a single environment from requirements to prototype A guided workflow for hardware and software development 8

9 Agenda Introduction ZYNQ Design Process Model-Based Design Workflow Prototyping and Verification Processor In the Loop UDP Interface Conclusions 9

10 Model-Based Design for Zynq RESEARCH Embedded Coder ARM DESIGN Top-Level System Model Software Model IMPLEMENTATION REQUIREMENTS Hardware Model HDL Coder FPGA Zynq Template Xilinx Embedded System Integration Real-Time Parameter Tuning and Verification User defines partitioning MathWorks automates code and interface-model generation MathWorks automates the build and download through the Xilinx tools 11

11 Model-Based Design for Zynq RESEARCH REQUIREMENTS Embedded Coder ARM DESIGN Embedded Coder Top-Level System Model Software Model Hardware Model IMPLEMENTATION C, C++ HDL Coder FPGA Real-Time Parameter Tuning and Verification HDL Coder VHDL, Verilog FPGA Boards ASIC Zynq Template Xilinx Embedded System Integration Zynq 12

12 Zynq Model-Based Design Workflow MATLAB and Simulink Algorithm and System Design AXI FPGA AXI ARM 13

13 Zynq Model-Based Design Workflow MATLAB and Simulink Algorithm and System Design HW HDL IP Core Generation SW Simulink Model HDL IP Core Generation AXI Lite Accessible Registers AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink External Ports Programmable Logic IP Core 14

14 Zynq Model-Based Design Workflow HDL IP Core Generation MATLAB and Simulink Algorithm and System Design AXI Lite Accessible Registers AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink Programmable Logic IP Core External Ports EDK Integration EDK Integration FPGA Bitstream Zynq Platform Processing System AXI4-Lite AXI Video DMA AXI Lite Accessible Registers AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink External Ports Programmable Logic IP Core EDK Project 15

15 Zynq Model-Based Design Workflow MATLAB and Simulink Algorithm and System Design HW HDL IP Core Generation SW EDK Integration SW Interface Model Generation SW Simulink Interface Model Model Generation FPGA Bitstream Zynq Platform SW Build SW I/O Driver Blocks SW SW Interface Model 16

16 Zynq Model-Based Design Workflow HDL IP Core Generation EDK Integration FPGA Bitstream MATLAB and Simulink Algorithm and System Design SW Interface Model Generation SW Build Real-time Parameter Tuning and Verification External Mode Processor-in-the-loop More probe and debug capability in the future Zynq Platform External Mode PIL 17

17 Zynq IP Core Generation R2013a Generate sharable and re-usable Xilinx IP core module from MATLAB/Simulink Support AXI4 interfaces to connect FPGA IP core to Zynq ARM processor Generate IP core report 19

18 Zynq Embedded System Tool Integration R2013b Integrate Xilinx EDK tool flow into HDL Workflow Advisor Insert the generated IP core into existing EDK Reference Design Build and Download to Zynq board AXI Lite Accessible Registers AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink FPGA IP Core EDK Project Example: Xilinx Zynq Base Targeted Reference Design HDL Coder generated IP Core 20

19 AXI4-Lite AXI4-Lite Interface setup R2013b Insert AXI4 Interface blocks Configure the base-address for the IP Core Configure the offset address of IP Core registers AXI4-Lite Blocks BASE_ADDRESS C Algorithm IP Core Registers BASE_ADDRESS ARM Cortex-A9 MP (Running Linux) FPGA IPCore 21

20 Demo 22

21 AXI4-Lite Bus Embedded System Integration Zynq HW/SW Co-design Workflow Summary FPGA IP Core HW Design IP Core Generation AXI Lite Accessible registers Algorithm from MATLAB and Simulink External Ports SW Simulink Model SW I/O Driver Blocks Generate SW Interface Model Processor AXI Lite Accessible registers Algorithm from MATLAB and Simulink External Ports SW FPGA IP Core SW Interface Model Embedded System Project SW Build FPGA Bitstream 23

22 Agenda Introduction ZYNQ Design Process Model-Based Design Workflow Prototyping and Verification Processor In the Loop UDP Interface Conclusions 24

23 Model Architectures Simulink Top-Level Model: Execution in Simulink Top-Level Model Model Reference Data Zynq Model UDP Send/Receive Zynq Model: Running on Zynq Platform PL Subsystem: Part of the Zynq Model PS Components PL Subsystem 25

24 Processor-In-the Loop(PIL) Test Code Generation (C/HDL) ZYNQ Help you evaluate the behavior of a candidate algorithm on the target both PS/PL and profile the execution times demo 26

25 AXI4-Lite Verification through UDP Interface Fast prototyping, iteration, and live probing/tuning directly on ZYNQ hardware UDP AXI4-Lite Blocks IP Core Registers demo C Algorithm ARM Cortex-A9 MP (Running Linux) FPGA IPCore 28

26 Agenda Introduction ZYNQ Design Process Model-Based Design Workflow Prototyping and Verification Processor In the Loop UDP Interface Conclusions 29

27 Conclusions: Abstraction is Key AXI4-Lite Interface AXI4-Lite AXI Lite Accessible Registers Processor AXI Video DMA AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink External Ports FPGA IP Core AXI4-Stream Interface 30

28 Conclusions: Abstraction is Key Focus on algorithm and system design Stay on higher level of abstraction AXI4-Lite Interface Automatic code generation and HW/SW integration AXI4-Lite AXI Lite Accessible Registers Processor AXI Video DMA AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink External Ports FPGA IP Core AXI4-Stream Interface 31

29 AXI4-Lite Bus Embedded System Integration HW/SW Co-design Workflow for Zynq FPGA IP Core HW Design IP Core Generation AXI Lite Accessible registers Algorithm from MATLAB and Simulink External Ports SW Simulink Model SW I/O Driver Blocks Generate SW Interface Model Processor AXI Lite Accessible registers Algorithm from MATLAB and Simulink External Ports SW FPGA IP Core SW Interface Model Embedded System Project SW Build FPGA Bitstream 32