ECEN454 Digital Integrated Circuit Design Memory ECEN 454 Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports DRAM Outline Serial Access Memories ROM ECEN 454 12.2 1
Memory Arrays Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) Read Only Memory (ROM) (Nonvolatile) Shift Registers Queues Static RAM (SRAM) Dynamic RAM (DRAM) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) First In First Out (FIFO) Last In First Out (LIFO) Mask ROM Programmable ROM (PROM) Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM (EEPROM) Flash ROM ECEN 454 12.3 Array Architecture 2 n s of 2 m s each If n >> m, fold by 2 k into fewer rows of more columns lines line conditioning lines row decoder memory cells: 2 n-k rows x 2 m+k columns n-k n k column decoder 2 m s column circuitry Good regularity easy to design Very high density if good cells are used ECEN 454 12.4 2
Basic building block: SRAM Cell 12T SRAM Cell Holds one of information, like a latch Must be read and written 12-transistor (12T) SRAM cell Use a simple latch connected to line 46 x 75 unit cell write write_b read read_b ECEN 454 12.5 6T SRAM Cell Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters Read: Precharge, _b Raise line Write: Drive data onto, _b Raise line _b ECEN 454 12.6 3
SRAM Read Precharge both lines high Then turn on line One of the two lines will be pulled down by the cell Ex: A = 0, A_b = 1 discharges, _b stays high But A bumps up slightly Read stability A must not flip _b P1 P2 N2 A N1 N3 A_b N4 A_b _b 1.5 1.0 0.5 A 0.0 0 100 200 300 400 500 600 time (ps) ECEN 454 12.7 SRAM Read Precharge both lines high Then turn on line One of the two lines will be pulled down by the cell Ex: A = 0, A_b = 1 discharges, _b stays high But A bumps up slightly Read stability A must not flip N1 >> N2 _b P1 P2 N2 N4 A A_b N1 N3 A_b _b 1.5 1.0 0.5 A 0.0 0 100 200 300 400 500 600 time (ps) ECEN 454 12.8 4
SRAM Write Drive one line high, the other low Then turn on line Bitlines overpower cell with new value Ex: A = 0, A_b = 1, = 1, _b = 0 Force A_b low, then A rises high Writability Must overpower feedback inverter N2 A P1 N1 P2 N3 A_b _b N4 A_b 1.5 A 1.0 _b 0.5 0.0 0 100 200 300 400 500 600 700 time (ps) ECEN 454 12.9 SRAM Write Drive one line high, the other low Then turn on line Bitlines overpower cell with new value Ex: A = 0, A_b = 1, = 1, _b = 0 Force A_b low, then A rises high Writability Must overpower feedback inverter N2 A P1 N1 P2 N3 A_b _b N4 N2 >> P1 A_b 1.5 A 1.0 _b 0.5 0.0 0 100 200 300 400 500 600 700 time (ps) ECEN 454 12.10 5
SRAM Sizing High lines must not overpower inverters during reads But low lines must write new value into cell _b med weak med A strong A_b ECEN 454 12.11 Read SRAM Column Example Write Bitline Conditioning Bitline Conditioning 2 _q1 More Cells More Cells 2 _q1 _v1f H SRAM Cell out_b_v1r H _b_v1f out_v1r write_q1 _v1f SRAM Cell _b_v1f 1 2 _q1 data_s1 _v1f out_v1r ECEN 454 12.12 6
Cell size is critical: 26 x 45 SRAM Layout Tile cells sharing V DD, GND, line contacts GND BIT BIT_B GND VDD WORD Cell boundary ECEN 454 12.13 Decoders n:2 n decoder consists of 2 n n-input AND gates One needed for each row of memory Build AND from NAND or NOR gates Static CMOS Pseudo-nMOS A1 A0 A1 A0 0 1 A1 A0 1 1 1 1 8 4 0 1 1/2 A0 A1 1 1 4 2 16 8 2 2 3 3 ECEN 454 12.14 7
Decoder Layout Decoders must be pitch-matched to SRAM cell Requires very skinny gates A3 A3 A2 A2 A1 A1 A0 A0 VDD GND NAND gate buffer inverter ECEN 454 12.15 Large Decoders For n > 4, NAND gates become slow Break large gates into multiple smaller gates A3 A2 A1 A0 0 1 2 3 15 ECEN 454 12.16 8
Predecoding Many of these gates are redundant A3 Factor out common gates into predecoder A2 Saves area A1 Same path effort A0 predecoders 1 of 4 hot predecoded lines 0 1 2 3 15 ECEN 454 12.17 Column Circuitry Some circuitry is required for each column Bitline conditioning Sense amplifiers Column multiplexing ECEN 454 12.18 9
Bitline Conditioning Precharge lines high before reads _b Equalize lines to minimize voltage difference when using sense amplifiers _b ECEN 454 12.19 Sense Amplifiers Bitlines have many cells attached Ex: 32-k SRAM has 256 rows x 128 cols 128 cells on each line t pd (C/I) V Even with shared diffusion contacts, 64C of diffusion capacitance (big C) Discharged slowly through small transistors (small I) Sense amplifiers are triggered on small voltage swing (reduce V) ECEN 454 12.20 10
Twisted Bitlines Sense amplifiers also amplify noise Coupling noise is severe in modern processes Try to couple equally onto and _b Done by twisting lines b0 b0_b b1 b1_b b2 b2_b b3 b3_b ECEN 454 12.21 Column Multiplexing Recall that array may be folded for good aspect ratio Ex: 2 k x 16 folded into 256 rows x 128 columns Must select 16 output s from the 128 columns Requires 16 8:1 column multiplexers ECEN 454 12.22 11
Tree Decoder Mux Column mux can use pass transistors Use nmos only, precharge outputs One design is to use k series transistors for 2 k :1 mux No external decoder logic needed A0 A0 A0_bar A0 A1_bar A1 A1 A1 A2_bar A2 A2 A2 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 Y to sense amps and write circuits Y ECEN 454 12.23 Single Pass-Gate Mux Or eliminate series transistors with separate decoder A1 A0 B0 B1 B2 B3 Y ECEN 454 12.24 12
Ex: 2-way Muxed SRAM 2 _q1 More Cells More Cells A0 A0 write0_q1 2 write1_q1 data_v1 ECEN 454 12.25 Multiple Ports We have considered single-ported SRAM One read or one write on each cycle Multiported SRAM are needed for register files Examples: Multicycle MIPS must read two sources or write a result on some cycles Pipelined MIPS must read two sources and write a third result each cycle Superscalar MIPS must read and write many sources and results each cycle ECEN 454 12.26 13
Dual-Ported SRAM Simple dual-ported SRAM Two independent single-ended reads Or one differential write A B _b Do two reads and one write by time multiplexing Read during ph1, write during ph2 ECEN 454 12.27 Multi-Ported SRAM Adding more access transistors hurts read stability Multiported SRAM isolates reads from state node Single-ended design minimizes number of lines A B C D E F G ba bb bc bd be bf bg write circuits read circuits ECEN 454 12.28 14
Dynamic RAM (DRAM) Capacitor can hold charge Transistor acts as gate No charge is a 0 Can add charge to store a 1 Then open switch (disconnect) Can read by closing switch ECEN 454 12.29 Precharge and Sense Amps You ll see precharge time B is precharged to ½ V Charge/no-charge on C will increase or decrease voltage Sense amps detect this ECEN 454 12.30 15
Destructive Read DRAM Characteristics When cell read, charge removed Must be restored after a read Refresh Also, there s steady leakage Charge must be restored periodically ECEN 454 12.31 Serial Access Memories Serial access memories do not use an address Shift Registers Tapped Delay Lines Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) Queues (FIFO, LIFO) ECEN 454 12.32 16
Shift Register Shift registers store and delay data Simple design: cascade of registers Watch your hold times! clk Din 8 Dout ECEN 454 12.33 Denser Shift Registers Flip-flops aren t very area-efficient For large shift registers, keep data in SRAM instead Move read/write pointers to RAM rather than data Initialize read address to first entry, write to last Increment address on each cycle clk Din 00...00 11...11 counter counter readaddr writeaddr dual-ported SRAM reset Dout ECEN 454 12.34 17
Tapped Delay Line A tapped delay line is a shift register with a programmable number of stages Set number of stages with delay controls to mux Ex: 0 63 stages of delay clk Din SR32 SR16 SR8 SR4 SR2 SR1 Dout delay5 delay4 delay3 delay2 delay1 delay0 ECEN 454 12.35 Serial In Parallel Out 1- shift register reads in serial data After N steps, presents N- parallel output clk Sin P0 P1 P2 P3 ECEN 454 12.36 18
Parallel In Serial Out Load all N s in parallel when shift = 0 Then shift one out per cycle shift/load clk P0 P1 P2 P3 Sout ECEN 454 12.37 Queues Queues allow data to be read and written at different rates. Read and write each use their own clock, data Queue indicates whether it is full or empty Build with SRAM and read/write counters (pointers) WriteClk WriteData FULL Queue ReadClk ReadData EMPTY ECEN 454 12.38 19
FIFO, LIFO Queues First In First Out (FIFO) Initialize read and write pointers to first element Queue is EMPTY On write, increment write pointer If write almost catches read, Queue is FULL On read, increment read pointer Last In First Out (LIFO) Also called a stack Use a single stack pointer for read and write ECEN 454 12.39 Read-Only Memories Read-Only Memories are nonvolatile Retain their contents when power is removed Mask-programmed ROMs use one transistor per Presence or absence determines 1 or 0 ECEN 454 12.40 20
ROM Example 4- x 6- ROM Represented with dot diagram Dots indicate 1 s in ROM Word 0: 010101 Word 1: 011001 A1 A0 weak pseudo-nmos pullups Word 2: 100101 Word 3: 101010 2:4 DEC ROM Array Y5 Y4 Y3 Y2 Y1 Y0 Looks like 6 4-input pseudo-nmos NORs ECEN 454 12.41 ROM Array Layout Unit cell is 12 x 8 (about 1/10 size of SRAM) GND Unit Cell ECEN 454 12.42 21
Programmable ROMs PROMs and EPROMs Build array with transistors at every site Burn out fuses to disable unwanted transistors Electrically Programmable ROMs Use floating gate to turn off unwanted transistors Trapped negative charges on the floating gate increase V t and shut off the transistor all the time EPROM, EEPROM, Flash Source Gate Drain Polysilicon Floating Gate Thin Gate Oxide (SiO 2) n+ n+ p bulk Si ECEN 454 12.43 PROMs and EPROMs Erasable Programmable ROM EPROM Programmed electronically Erased through exposure to UV light Electrically Erasable Programmable ROM EEPROM Electronically programmable/erasable in bytes Flash Electrically Programmable in bytes Electrically erasable in large blocks or entire chip (early flash) Can be thought as a special EEPROM NAND flash (vs. NOR flash): high density, less expensive; mainstream for today s memory cards & USB flash drives. ECEN 454 12.44 22