Memory in Digital Systems

Transcription

1 MEMORIES

2 Memory in Digital Systems Three primary components of digital systems Datapath (does the work) Control (manager) Memory (storage) Single bit ( foround ) Clockless latches e.g., SR latch Clocked transparent latches e.g., D latch Clocked edge-triggered flip flops e.g., D FF Array memories ( background ) B. Baas 22

3 Memories Use in general digital processors Instructions Data Usage is more widespread in DSP, multimedia, embedded processors Buffering input/intermediate/output data (e.g., rate matching) Storing fixed numbers (e.g., coefficients) Often relatively small (e.g., words) and numerous (dozens are not unusual) Key design goal: density, especially for the memory s. This means fitting the largest amount of memory storage into a certain amount of chip area B. Baas 23

4 wordlines Memories Memories generally contain several components: Array of s Address decoder Write circuitry Read circuitry (sense amplifiers) wordlines bitlines Interface signals Address (one for each port) Data (one for each port) Enable_write Enable_read (likely) Clock (sometimes) word or address decoder Addr bitlines write/read circuitry B. Baas 24 Data_rd Data_wr

5 bitlines Memories Differential bitlines Differential bitlines (bitline and bitline_) require more area but dramatically increase robustness and speed Much smaller voltage differences can be detected Much more noise can be tolerated Address decoder Read / (Write) circuitry wordline B. Baas 25

6 Array Memory View 1: Types 1. Read-write memories SRAM: Static random access memory Data is stored as the state of a bistable circuit typically using back-to-back inverters State is retained without refresh as long as power is supplied DRAM: Dynamic random access memory Data is stored as a charge on a capacitor State leaks away, refresh is required 2. ROM: Read-only memory, non-volatile Basic ROM mask programmed at design time PROM: Programmable read-only memory; typically programmed at manufacture time by a PROM burner Using fuse or anti-fuse circuits Synthesized from standard s 3. NVRWM: Non-volatile read-write memory EPROM: Erasable ROM, erasable with UV light Flash: ROM at low voltages, writable at high voltages B. Baas 26

7 Memory View 2: Logical Categories Combinational (output depends on present inputs only) ROM: read-only memory May be truly straight-through combinational, or istered Feels like Combinational but technically Sequential PROM: programmable read-only memory EPROM: ROM, but erasable with UV light Sequential (output depends on present and past inputs) SRAM: static memory DRAM: dynamic memory Flash: ROM at low voltages, writable at high voltages B. Baas 27

8 INV INV INV INV INV INV INV INV Decoder Design Example: 256-word memory (8 addr bits) Straightforward approach Route 8 address wires plus inverted versions (16 wires) along array Each word uses an 8-input AND gate Each long wire has N/2=128 gate loads AND AND AND B. Baas 28

9 Decoder Design Critical path INV + 8-input AND Neglect assertion level because we ll have to add a number of inverters (buffers) anyway Building an 8-input AND: AND-AND (inefficient) NAND-NOR (better) Total critical path INV + 4-input NAND + 2-input NOR, or INV + 3-input NAND + 3-input NOR INV 8-in AND 8-in AND 8-in AND B. Baas 29

10 Decoder Design Predecoding Example: 256-word memory (8 addr bits) Predecode Ex: take groups of 2 address bits Four possibilities; activate one of four wires (use 2 INVs, 4 ANDs) Wires along array: 4 * (8/2) = 4 groups of 4 = 16 (same as nonpredecoded) Each word uses a 4-input AND gate (much faster) Each long wire has N/4=64 gate loads (half of other approach!) Works best with large memories May have less toggling May be faster AND AND AND B. Baas 30

11 Decoder Design Predecoding Critical path Predecoder + 4-input AND Neglect assertion level because we ll have to add a number of inverters (buffers) anyway INV + 2-input AND + 4-input AND May be able to use NANDs instead of ANDs 4AND 4AND 4AND AND INV B. Baas 31

12 Six-Transistor (6T) SRAM Cell BL BL Q Q WL Cross-coupled inverters: a bistable element (two stable states) Density is critically important in memories Single NMOS used for reading/writing A lot of effort spent packing transistors and even pushing process design rules just for the 6T memory the area of a 6T is typically one of the top critical parameters of a fabrication technology! B. Baas

13 SRAM Cell Cross-coupled inverters: a bistable element (two stable states) Density is critically important in memories Single NMOS used for reading/writing A lot of effort spent packing transistors and even pushing process design rules just for the 6T memory B. Baas 33 Retrieved November 17, 2016

14 6-Transistor (6T) Cells Micro-photograph of 0.16 µm 2 6T SRAM s from an AMD Radeon graphics processor fabraicated in TSMC s 28 nm HP process B. Baas 36 [Chipworks]

15 Memory Array Human hair on a 256 Kbit memory chip B. Baas 40 Source: Helmut Föll

16 Multi-ported SRAM Frequently used in ister files Classic RISC computers have 1 write and 2 read ports Modern multiple-instruction-issue computers can have many ports (22 (12 Rd, 10 Wr) in Itanium [ISSCC 05]) More commonly use single-ended (non-differential) bitlines Addr/Data Addr/Data 2 write ports Memory 4 read ports B. Baas 45

17 Multi-ported SRAM Example: one write port, two read ports Write bitline Read bitline 0 Read bitline 1 Write wordline Read wordline 0 Read wordline 1 B. Baas

18 DRAM Smaller size (1T ) One transistor to access Often has special structure for capacitor (trench capacitor) that is not available in standard fabrication technologies Single bitline to read and write the memory Must be periodically refreshed Write operation: Wordline at Vdd Bitline value stored on capacitor Trench capacitor B. Baas 51 WL BL Q

19 DRAM Classic DRAM High density dedicated DRAM chips typically packaged in DIMMs Top manufacturers include: Samsung (47%), Hynix (26%), Micron (19%), and others. [Source: Statista, for Q2 2016] Embedded DRAM (edram) DRAM arrays are also available as a process option for standard logic -type CMOS fabrication technologies Ex: IBM 22 nm z Processor CP Microprocessor chip on left: 8 cores, 64MB of edram Level-3 cache, 678 mm2 die area, 4.0 billion transistors, 17 metal layers. edram is used for Level-3 cache and memory controller; and also inside each processor for Level-2 and Branch Target Buffer caches. SC System Controller chip on right: 480 MB of edram Level-4 cache, 678 mm2 die area, 7.1 billion transistors, 15 metal layers [Source: 22nm Next-Generation IBM System z Microprocessor, ISSCC, 2015.] B. Baas 52

20 DRAM Read operation: Wordline at Vdd Bitline precharged to intermediate voltage level (e.g., Vdd/2) Read bitline voltage is the charge shared result of storage capacitor and bitline capacitance C_ ~ C_bitline / (10-100) ΔV_bitline ~ 250 mv Read is a destructive read and value must be re-written to be read again Circuit challenges: More complex sense amplifiers Many use differential sense amplifier with dummy Higher noise susceptibility Vdd not needed in array B. Baas 53 WL BL Q

21 Trench Capacitor Deep trench capacitor provides high capacitance per area Example to the right shows a DRAM cross section B. Baas

22 Memory Array Human hair on a 4 Mbit memory chip Note DRAM trench capacitors B. Baas 55 Source: Helmut Föll

23 Memory Array Red blood s on a 1 Mbit memory chip B. Baas 56 Source: Helmut Föll

24 ROM Similar to DRAM except the source of the access transistor is tied to Gnd directly For the other value (BL 0), the circuit is modified so that nothing happens when WL goes high. Possibilities include: Omit -Gnd to global-gnd connection Omit source-to-gnd or drain-to-bitline contact Omit poly to WL contact Omit MOS transistor diffusion Omit transistor entirely In this particular example circuit: A circuit to precharge bitlines is needed but not shown bitline is driven low very strongly when a transistor is present ROMs are typically among the densest of all circuits Keep in mind that sometimes it is more efficient to use synthesized random logic instead of a ROM, especially if the stored data contains patterns and is not highly random WL WL BL Gnd Gnd B. Baas 57

25 Memory View 3: Memory Types for Custom- Designed Chips (Also known as "ASICs") Memories for custom processors can be built in a number of ways: 1) On-chip macro memory arrays Think of as a single giant standard FPGAs include them ( block RAMs or block memory ) 2) On-chip memory synthesized from standard s 3) Off-chip memories (perhaps for > approx. 10 MB) Very large DRAM Non-volatile memory such as flash memory (We could also include disks, NAS, cloud, etc.) B. Baas 60

26 1) Memory Macro-s Memory macro- generators are available for larger memories Typically a software tool generates a large variety of possible memories where a user may select options such as: Number of words Word-width (in bits) Number of read ports Number of write ports Rd/wr or ROM Built-in test circuits Registered inputs and/or outputs Tool produces models for verilog, place & route, and other CAD views RAM macro B. Baas 61

27 1) On-chip macro memory arrays Generally very area efficient due to dense memory s (singleported memories likely use 6-transistor (6T) memory s) Generally good energy efficiency due to lowactivity memory array architecture Example: CMOS chip B. Baas 62 [T. Nanya, et al., TITAC um CMOS, 496K transistors, mm mm processor]

28 1) On-chip macro memory arrays: FPGAs Example: FPGA Altera Max 10 10M50DAF484C7G chip Yellow rectangles are M9K memory blocks Each block contains 8192 bits (9216 including parity) 182 on each chip Total of 182 KBytes (204 KB) Light-blue rectangles: Logic Array Blocks (LAB) White rectangles: hardware 18x18 multipliers (144 on chip) B. Baas 63

29 2) Synthesized Memory Can synthesize memory from standard s clk Memory s are now flip-flops clk likely routed to all s Probably best for small memories only Read bitline logic may be muxes word or address decoder write/read circuitry B. Baas 64

30 2) Synthesized Memory Standard layout is typically irular Wires not shown Clocks routed to each (flip-flop) INV & BUF OR BUF & MUX MUX BUF OR & MUX BUF OR B. Baas 65

31 Verilog Memories Declaring a 16-bit, 128-word memory [15:0] Mem [0:127]; Reading a memory source1 = Mem[addr_rd]; Writing a memory For this class, always use non-blocking writes Read operation reads old previous cycle data Mem[addr_wr] <= #1 c_datapath_out; // makes sense for FF memory B. Baas 66

32 Verilog Memories This memory performs writes on the positive edge of the clock when write_enable is high The output is not controlled by the clock and outputs the correct memory word for any address on addr_rd Picture a large mux tree connecting every word in the memory to the output port Sometimes called an asynchronous read [15:0] mem [0:127]; clk) begin if (write_enable == 1 b1) begin mem[addr_wr] <= #1 data_in; end end assign data_out = mem[addr_rd]; B. Baas 67

33 Verilog Memories This memory also performs writes on the positive edge of the clock when write_enable is high However it contains a synchronous read which updates the output port only on the active edge of the clock [15:0] mem [0:127]; clk) begin if (write_enable == 1 b1) begin mem[addr_wr] <= #1 data_in; end data_out <= #1 mem[addr_rd]; end There is now one clock cycle of delay from when addr_rd is valid to when the read output is valid The M9K memory blocks in Altera FPGAs work this way B. Baas 68

34 Verilog Memories Reading and writing Cannot access a portion of a word without first reading the whole word in many simulators and CAD tools (though it is supported in some tools). Good practice to not do it! So don t in this class. source1 = Mem[addr_rd][5]; // won t work sometimes temp = Mem[addr_rd]; // use these 2 lines instead source1 = temp[5]; Multiple unclocked read ports Simply make individual read statements for each read port data1 = Mem[addr_rd1]; data2 = Mem[addr_rd2]; data3 = Mem[addr_rd3]; B. Baas 69

35 ROMs Synthesized Small ROMs can be efficiently synthesized from standard s Implementations are more efficient if the data is less random in an information-theory sense It is advisable to generate tables from a program such as matlab // todo: add default case for safety begin case (input) 4'b0000: begin real=8'b ; imag=8'b ; end // angle = 'b0001: begin real=8'b ; imag=8'b ; end // angle = 'b0010: begin real=8'b ; imag=8'b ; end // angle = 'b0011: begin real=8'b ; imag=8'b ; end // angle = 'b0100: begin real=8'b ; imag=8'b ; end // angle = 'b0101: begin real=8'b ; imag=8'b ; end // angle = 'b0110: begin real=8'b ; imag=8'b ; end // angle = 'b0111: begin real=8'b ; imag=8'b ; end // angle = 'b1000: begin real=8'b ; imag=8'b ; end // angle = 'b1001: begin real=8'b ; imag=8'b ; end // angle = 'b1010: begin real=8'b ; imag=8'b ; end // angle = 'b1011: begin real=8'b ; imag=8'b ; end // angle = 'b1100: begin real=8'b ; imag=8'b ; end // angle = 'b1101: begin real=8'b ; imag=8'b ; end // angle = 'b1110: begin real=8'b ; imag=8'b ; end // angle = 'b1111: begin real=8'b ; imag=8'b ; end // angle = endcase end B. Baas 70

36 ROMs FPGA Block RAM Larger ROMs on FPGAs can make use of block RAMs whose contents can be specified with a verilog initial block Read operations are synchronous and update the output port only on the active edge of the clock [7:0] rom [0:127]; initial begin rom[0] = 8 h35; rom[1] = 8 h2e; rom[2] = 8 hff;... end clk) begin data_out <= #1 rom[addr_rd]; end There is now one clock cycle of delay from when addr_rd is valid to when the read output is valid The M9K memory blocks in Altera FPGAs work this way B. Baas 71

37 Memory Pipelining/Timing Timing Style 1 Style 1: Registers are outside the memory array Memory macros typically ister input addresses and data outside the memory array word or address decoder Memory macro boundary write/read circuitry B. Baas 72

38 Memory Pipelining/Timing Timing Style 1a For cases when the memory is a combinational block Add pipeline isters outside block as appropriate or as needed to meet the target clock frequency Memory Memory B. Baas 73

39 Memory Pipelining/Timing Timing Style 1b For cases when the memory has a built-in ister for its outputs Add a pipeline ister to the inputs as appropriate or as needed to meet the target clock frequency Memory Memory B. Baas 74

40 Memory Pipelining/Timing Timing Style 1c For cases when the memory has a built-in ister for its inputs Add a pipeline ister to the outputs as appropriate or as needed to meet the target clock frequency Memory Memory B. Baas 75

41 Memory Pipelining/Timing Timing Style 2 Style 2: Register is in the middle of the memory array Standard memories store bits in the array in FFs This forces a pipe stage across the middle of the memory array word or address decoder write/read circuitry clk B. Baas 76

42 Memory Pipelining/Timing Timing Style 2 Built-in pipeline stage in memory array May place logic in memory pipe stages to balance pipeline Memory logic Memory logic B. Baas 77