Yafit Snir Arindam Guha, Inc. Accelerating System level Verification of SOC Designs with MIPI Interfaces
Agenda Overview: MIPI Verification approaches and challenges Acceleration methodology overview and advantages Accelerated verification IP Architecture Migration guidelines: from simulation to acceleration Virtual emulation using MIPI virtual device models Demonstration 2
Agenda Overview: MIPI Verification approaches and challenges Acceleration methodology overview and advantages Accelerated verification IP Architecture Migration guidelines: from simulation to acceleration Virtual emulation using MIPI virtual device models Demonstration 3
MIPI CSI-2 & MIPI DSI Widely adopted serial high-speed protocols. Implemented in complex systems, for a variety of applications in different markets: Mobile Automotive Multimedia Virtual reality, augmented reality and others 4
MIPI Interfaces usage example in Complex/Large SOC s ARM CPU Subsystem Customer s Application Specific Components Software A15 A15 L2 cache A7 A7 L2 cache 3D Graphics Core DSP A/V Application Accelerators AES Cache Coherent Fabric SoC Interconnect Further complicated by hardware/ software interactions LPDDR3 PHY 3.0 PHY USB3.0 2.0 PHY PCIe Gen 2,3 PHY High speed, wired interface peripherals Ethernet PHY SATA SAS SD MIPI UFS Other Memory Storage & Memory MIPI CSI-2 MIPI DigRF MIPI D-PHY MIPI DSI MIPI M-PHY MIPI SLIMbus I2C Low-speed MIPI LLI peripheral JTAG subsystem MIPI UniPro MIPI high speed peripheral interfaces, and other.
System Level Verification Challenges Complex and Large Designs. Long simulation time Need to reach system coverage goals prior to RTL freeze. Time to market: Requires parallel development of hardware and software design, early in development cycle.. Validating software and hardware integration. Create and validate real world scenarios in a pre-silicon environment. 6
Overview of Current verification approaches Pure Simulation verification Full controllability and coverage collection. Acceptable performance for module/sub system. Hardware assisted verification Enables High performance for sub system/system verification. Enables pre-silicon HW/SW verification. Enables running longer tests, with high throughput to reach interesting system scenarios, and validate performance. 7
Overview of hardware assisted verification methods Simulation Acceleration Accelerating hardware verification. Virtual Emulation SW Driven HW Verification, SW/HW Validation In-Circuit Emulation Enables real device connection FPGA Prototyping 8
Emulator Use Modes Performance Software Virtual Transaction Signal Synthesizable Hybrid In-Circuit Based Simulation Emulation Based Acceleration Testbench (using Acceleration Virtual Device Models) Workstation Emulator Virtual Simulator Platform Emulator Virtual T Virtual DUT Device Processor T DUT DUT B Interface B DUT Models Model 10,000x Hybrid 1,000x Synthesizable Testbench (STB) In-Circuit Emulation 100x Transaction-Based Acceleration Virtual Emulation 10x Signal-Based Acceleration 1x Software Simulation Block / IP Verification Sub-system / SoC Verification SoC level HW/FW Integration Full System Validation w. App SW 9
Agenda Overview: MIPI Verification approaches and challenges Acceleration methodology overview and advantages Accelerated verification IP Architecture Migration guidelines: from simulation to acceleration Virtual emulation using MIPI virtual device models Demonstration 10
Simulation vs. Acceleration Simulation Performance For small designs or IP level verification, simulation performance is good-enough Testbenc h Design Under Test Workstation Acceleration IP Sub-system System Performance gap increases for more complex designs Design Size Testbenc h P R O X Y T B A T B A B F M Design Under Test Simulation-Acceleration mode DUT runs at higher speeds than in general purpose CPU Acceleration factor determined by TB time and synchronizations between TB and Emulator Workstation Emulator 11
Acceleration Signal Based Acceleration & Transaction Based Acceleration Workstation Communication Channel Emulator Testbench P R O X Y TBA I/F TBA I/F B F M Design Under Test Workstation Emulator Signal Transaction Based Based Acceleration Acceleration (TBA) Bit-by-bit Reduces communication signal level exchange channel between overhead testbench from signal and based DUTto Performance transaction based bottleneck can be the communication Leverages fast hardware channel for testbench DUT time execution 12
Accelerated Verification IP (AVIP) Workstation AVIP Emulator Testbench Seq Drv Mon TBA I/F TBA I/F Optimized Core Design Under Test Workstation Emulator Accelerated Verification IPs optimized for performance 13
Acceleration Methodology Advantages Enables orders-of-magnitude gains in throughput over Simulation Enables re using selected parts of your simulation verification environment Enables advanced technologies with virtual emulation, like: Hybrid operation for optimal partition of the design between HW and SW to achieve maximum speedup Connection to Virtual Devices, Virtual machines, etc. Enables OS-level benchmarks and driver bring-up 14
Agenda Overview: MIPI Verification approaches and challenges Acceleration methodology overview and advantages Accelerated verification IP Architecture Migration guidelines: from simulation to acceleration Virtual emulation using MIPI virtual device models Demonstration 15
Architecture of Accelerated Verification IP (AVIP) Dynamic batching/reactive user control to optimize performance Transaction send/receive channels User API (C/CPP/TLM2/UVM-SV) Functions SW Proxy control/ status channel CallBacks mem rd/wr channels Acceleration Optimized Core Host (SW) Emulator (HW) Optimize transfer types using various standards for simulator/emulator communication. DUT 16
Agenda Overview: MIPI Verification approaches and challenges Acceleration methodology overview and advantages Accelerated verification IP Architecture Migration guidelines: from simulation to acceleration Virtual emulation using MIPI virtual device models Demonstration 17
Optimizing Acceleration performance Color Legend % of time spent in testbench % of time spent in DUT % of time spent in channel Higher acceleration performance TB TB TB C H Transaction Based Acceleration With optimized testbench DUT Testbench optimization Transaction Based Acceleration With optimized channel Signal Based Acceleration With DUT running in HW Introduces channel overhead Simulation High level of acceleration Focus on sub-system & system level verification Optimize testbench by removing verification redundancies from IP-level - stimulus generation. Increase acceleration factor Reduce communication overhead Transactor may need modeling effort Quickest path to acceleration Maximize re-use of testbench Profile simulation runs to identify acceleration candidates Select runs that are long & spend large amount of time in DUT 18
Acceleration Friendly UVC ( at the Simulation Stage ) SW Domain Agent SW Domain SV Interface SV Interface BFM Wrapper Virtual Interface BFM BFM DUT DUT CLK CLK 19
Acceleration Ready UVC (at the Emulation Stage ) SW Domain Agent Events HW Domain SV Interface Proxy Tasks Data (DPI-C) Synthesizable BFM DUT Callbacks CLK 20
Agenda Overview: MIPI Verification approaches and challenges Acceleration methodology overview and advantages Accelerated verification IP Architecture Migration guidelines: from simulation to acceleration Virtual emulation using MIPI virtual device models Demonstration 21
DSI Virtual Device SOC Design Enables you to visualize the HW/SW operation of your video/image processing subsystem in real time SW stack/drivers DSI Virtual Device GPU Image processor Frame buffer DSI Host Controller DSI AVIP BFM DSI AVIP DSI AVIP SW Proxy DSI Virtual Device Model DSI Model Logic Virtual Display Emulator Workstation 22
CSI-2 Virtual Device SOC Design Enables you to visualize the HW/SW operation of your video/image processing subsystem in real time SW stack/drivers CSI-2 Virtual Device Image files GPU Image processor Frame buffer CSI-2 Host Controller CSI-2 AVIP BFM CSI-2 AVIP CSI-2 AVIP SW Proxy CSI-2 Virtual Device Model CSI-2 Model Logic Emulator Workstation 23
Virtual Device Models usage example Application/firmware FM code receiver DRAM running to capture image LPDDR file on camera and route image to display GPS receiver Cellular modem WiFi Bluetooth RFFE DigRF SDIO3 Motion sensors LPDDR 2 Power control LPDDR 3 Applications processor AMBA 4 ACE AMBA AXI, AHB SLIMbus SPMI USB 2.0 NAND NAND Flash FLASH emmc 4.5 UFS LLI USB 3.0 OTG Memory card SD 3.0 SD 4.0 UFS Multimedia processor cjtag I2C OCP 2.0 OCP 3.0 GBT CSI2 CSI3 SLIMbus Camera interface Touch screen controller Display driver DSI SSIC Emulator Simulator Audio interface HDMI 1.4 CSI-2 Virtual Device CSI CSI Virtual AVIP Device Model DSI Virtual Device DSI DSI Virtual AVIP Device Model Image files 24
Agenda Overview: MIPI Verification approaches and challenges Acceleration methodology overview and advantages Accelerated verification IP Architecture Migration guidelines: from simulation to acceleration Virtual emulation using MIPI virtual device models Demonstration 25
SoC VDM Display DSI Device Controller DSI2 Device Controller D-PHY C-PHY D-PHY C-PHY DSI Host Controller DSI2 Host Controller VDM Camera CSI2 Device Controller D-PHY C-PHY D-PHY C-PHY CSI2 Host Controller I2C Controller I2C Controller To discuss Cadence MIPI Accelerated VIPs availability, Please contact: HSV_PM@cadence.com 26