1 of 7 ay 13, 2002 v2 Spring 2002 Final Exam open books, open notes Starts: 7:30 pm Ends: 9:30 pm Name: (please print) ID: Problem ax points Your mark Comments 1 10 5+5 2 40 10+5+5+10+10 3 15 5+10 4 10 5+5 5 10 6 15 10+5 100 This paper will be retained for one year in the Computer Science Department. Computer Science Department
State all your assumptions clearly! v2 2 of 7 1. You know the following about the time distribution of instructions in your favorite application: t i CPI i ALU 50% 4 Load/store 40% 6 Branches 10% 5 a) compute the average CPI for your application. b) compute the IPS for your machine using the above table; the clock rate for your machine is 1 GHz.
State all your assumptions clearly! v2 3 of 7 2. Consider the following fragment of C code: i = 100; while (i) { a[i] = b[i] + c; i = i - 1; } Assume that a and b are arrays of words and that the base address of a is in $a0 and the base address for b is in $a1. i is in $t0, and c is in $s0. a) Write the code for IPS using native instructions. b) How many instructions are executed during the running of this code? c) How many memory references will be made during execution?
State all your assumptions clearly! v2 4 of 7 d) Assume your code will run on the pipelined datapath of Figure 6.30 (see also attached). Identify all pipeline hazards. c) What is the average CPI of your code running on the pipelined datapath of Figure 6.30?
State all your assumptions clearly! v2 5 of 7 3. You have a register-register architecture that has two addressing modes, base-displacement and memory indirect, besides register and immediate. You want to improve this architecture by eliminating the memory indirect addressing mode: this will decrease the clock cycle by 10% but will increase somehow the instruction count because you will have to replace instructions like: lw R1, @(R2) with a sequence of instructions. Assume that the frequency of memory indirect addressing is 5%, and that the overall CPI does not change. a) show the sequence of instructions that will replace every memory indirect addressing; b) how does the performance of the new architecture compare with the performance of the original?
State all your assumptions clearly! v2 6 of 7 4. a) Describe the general characteristics of a program that would exhibit very little temporal locality but very high amounts of spatial locality with regard to instruction fetches. b) Provide an example program (pseudocode is ok). 5. Cache C1 is direct-mapped with 16 one-word blocks. Cache C2 is direct-mapped with 4 four-word blocks. Assume that the miss penalty for C1 is is 8 clock cycles and the miss penalty for C2 is 11 clock cycles. Assuming that the caches are initially empty, find a reference string for which C2 has lower miss rate but spends more cycle on cache misses than C1. Use word addresses.
State all your assumptions clearly! v2 7 of 7 6. Consider a virtual memory system with the following properties: 40-bit virtual byte address 8-KB pages 30-bit physical byte address a) What is the total size of the the page table for each process on this machine assuming that the valid, protection, dirty and use bits take a total of four bits and that all virtual pages are in use? b) Calculate the amount of storage required to implement a fully-associative TLB with a total of 128 TLB entries
PC memory Add [20 16] emtoreg ALUOp Branch RegDst ALUSrc 4 16 32 [15 0] 0 0 u x 0 1 Add Add result Registers Write register Write data data 1 data 2 register 1 register 2 Sign extend u x 1 ALU result Zero Write data data u x 1 ALU control Shift left 2 RegWrite em Control ALU [15 11] 6 EX WB WB WB IF/ID PCSrc ID/EX EX/E E/WB u x 0 1 emwrite Address Data memory Address