10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function F=xy+x 1 z to product of Maxterm. 3. Bring out the difference between Canonical & Standard forms. 4. Minimize the following using Kmaps: i) SOP expression given by f(a,b,c,d) = Σ m(0,1,2,3,5,9,14,15) + Σ Φ(4,8,11,12) ii) POS expression given by f(a,b,c,d) = M(0,1,2,5,8,9,10) Implement the minimal expressions thus obtained using basic gates (both normal and inverted inputs can be used) 5. List out the difference between combinational and sequential logic circuits 6. Convert the following to other canonical form. i) F(x,y,z) = (1,3,7) ii) F(A,B,C,D)= (0,2,6,11,13,14) iii) F(x,y,z) = (0,1,2,3,4,6,12) 7. Expand the following function into canonical SOP form f(x1,x2,x3) = x 1 x 3 + x 2 x 3 + x 1 x 2 x 3 8. Expand the following function into canonical POS form F(W,X,Q) =(Q+W 1 ) (X+Q 1 ) (W+X+Q) (W 1 +X 1 ) 9. Mention different methods of simplifying Boolean functions. 10. Place the following equations into the proper canonical form a) P = f(a,b,c) = ab 1 +ac 1 +bc b) G = f(w,x,y,z) = wx 1 + yz 1 c) T = f(a,b,c) = (a+b 1 )(b 1 +c 1 ) 11. Express the following SOP equations in a minterm list (Short hand decimal notation) form: a) H = f(a,b,c) = A 1 BC + A 1 B 1 C + ABC b) G = f(w,x,y,z) = WXYZ 1 + WX 1 YZ 1 + W 1 XYZ 1 + W 1 X 1 YZ 1 12. Express the following POS equations in a maxterm list (decimal notation) form:
a) T = f(a,b,c) = (a+b 1 +c) (a+b 1 +c 1 ) (a 1 +b 1 +c) 13. Simplify the following a) J = f(x,y,z) = (0,2,3,4,5,7) b) K = f(w,x,y,z) = (0,1,4,5,9,11,13,15) c) R = f(v,w,x,y,z) = (5,7,13,15,21,23,29,31) 14. Draw a model representing combinational circuits. Label the input and output variables. Write a general expression showing the input and output relationship. 15. How does a truth table express a combinational circuit. 16. Convert the following equations into their requested canonical forms: a) (SOP) X = a 1 b+bc b) (POS) P = (w 1 +x)(y+z 1 ) c) (SOP) T = p(q 1 +s) d) (SOP) R = L+M 1 (N 1 M+M 1 L) e) (POS) U = r 1 +s(t+r)+s 1 t E. a) Two motors M2 and M1 are controlled by three sensors S3, S2 and S1. One motor M2 is to run any time all three sensors are on. The other motor is to run whenever sensors S2 or S1 but not both are on and S3 if off. For all sensor combinations where M1 is on, M2 is to be off except when all the three sensors are off and then both motors must remain off. Construct the truth and write the Boolean output equation. (6) (Jan.08) b) Simplify using Karnaugh map. Write the Boolean equation and realize using NAND gates. D = f(w,x,y,z) = (0,2,4,6,8)+ d(10,11,12,13,14,15). (6) c) Simplify P = f(a,b,c) = (0,1,4,5,7) using two variable Karnaugh map. Write the Boolean equation and realize using logic gates. (8) d) Simplify using Karnaugh map L = f(a,b,c,d) = (2,3,4,6,7,10,11,12) (6) 17. Discuss K-map & Quine McCluskey methods for simplification of Boolean expressions. 18. Discuss K-map & Quine McCluskey methods. 19. Write advantages of K-map over Quine McCluskey method. 20. Define term Don t care condition. 21. Explain K-map representation in detail & discuss the merits & demerits. 22. Explain the tabulation procedure in detail & discuss merits & demerits. 23. Compare K-map & Quine-Mcclusky methods for simplification of Boolean Expression.
24. Obtain the simplified expression in sum of products for the following: F(A,B,C,D,E) = (0,1,4,5,16,17,21,25,29) 25. Obtain simplified expression in SOP & POS form i) x1z1+y1z1+yz1+xyz ii) w1yz1+vw1z1+vw1x+v1wz+v1w1y1z1 and draw gate implementation using AND & OR gates 26. Given the function T(w,x,y,z)=Σ(1,3,4,5,7,8,9,11,14,15).Use K map to determine the set of all prime implicants. Indicate essential prime implicants, find three distinct mininmal expressions for T 27. Using tabulation method, determine the set of all prime implicants for the function f(w,x,y,z) = Σ(0,1,2,5,7,8,9,10,13,15) and hence obtain the minimal form of given function, employing decimal notation. 28. Compare K-map & Quine-Mcclusky methods for simplification of Boolean Expression. Give their merits and demerits 29. Using K-map simplify following Boolean expression & give implementation of same using i) NAND gates only ii) AND,OR & Invert gates for F(A,B,C,D) = (2,4,8,16,31)+ D (0,3,9,12,15,18) 30. Using K-map obtain Simplified expression in SOP & POS form of function F(A,B,C,D)=(A 1 +B 1 +C 1 +D 1 )(A 1 +B 1 +C+D 1 )(A+B 1 +C+D 1 )(A+B+C+D 1 )(A+B+C+D) 31. Simplify Boolean function using don t care condition for SOP & POS F=w1(x1y+x1y1+xyz)+x1z1(Y+w), d=w1x(y1z+yz1)+wyz F=ACE+A 1 CD 1 E 1 +A 1 C 1 DE, d= DE 1 +A 1 D 1 E+AD 1 E 1 32. Simplify the following Boolean function using K-map method i) xy+x 1 y 1 z 1 +x 1 yz 1 ii) x 1 yz+xy 1 z+xyz+xyz 1 iii)f=a 1 C+A 1 B+AB 1 C+BC iv)f (w,x,y,z)= (0,1,2,4,5,6,8,9,12,13,14) 33. Determine set of Prime implicants for function F(w,x,y,z)= (0,1,2,5,7,8,9,10,13,15) 34. Minimize the following function with don t care terms using Q.M. method i) f(a,b,c,d)= m(5,7,11,12,27,29)+d(14,20,21,22,23) ii) f(a,b,c,d)= m(1,4,6,9,14,17,22,27,28,)+d(12,15,20,30,31) 35. Determine the set of Prime implicants for function F(w,x,y,z)= (0,1,2,5,7,8,9,10,13,15) 36. Using Quine-McCluskey obtain the set of Prime implicants for function
F(a,b,c,d,e)= (4,12,13,14,16,19,22,24,25,26,29,30)+ d (1,3,5,20,27) 37. Identify the prime and essential prime implicants for the following expressions a) S = f(a,b,c,d) = (1,5,7,8,9,10,11,13,15) b) T = f(a,b,c,d,e) = (0,4,8,9,10,11,12,13,14,15,16,20,24,28) 38. Simplify the SOP equations given below. Let the MEV term be the least significant variable in each expression. a) Construct the MEV truth table b) Create the MEV K-map c) Write the simplified equations d) Is the trial expression optimal (compare it to a regular K-map simplified expression) (i) V = f(a,b,c,d) = (2,3,4,5,13,15) + d(8,9,10,11) (ii) Y = f(u,v,w,x) = (1,5,7,9,13,15) + d(8,10,11,14) (iii) P = f(r,s,t,u) = (0,2,4,8,10,14) + d(5,6,7,12) (iv) F = f(u,v,w,x,y) = (0,2,8,10,16,18,24,26) E. a) Simplify using Quine Mc Clusky tabulation algorithm- (14) V = f(a,b,c,d) = (2,3,4,5,13,15)+ d(8,9,10,11) 39. Define combinational circuit with block diagram, Explain the elements of combinational circuit. 40. Discuss the full adder with an example. 41. Discuss the Half adder with an example. 42. Given 3x8 decoder, show the construction of 4x16 decoder. 43. Explain grouping and simplification process in K maps using the 3 variable and 4 variable maps. 44. Give the main steps for designing combinational circuits. 45. What is decoder? what are its advantages? Design a decimal decoder which converts information from BCD to DECIMAL. 46. Mention the difference between full and half adder. 47. Design BCD to 7 segment decoder using NAND gates only. 48. Mention the application of decoder. 49. Using decoder implement the following Logic functions. a) Active High decoder with OR gate. b) Active Low decoder with NAND gate. c) Active High decoder with NOR gate.
d) Active Low decoder with AND gate. 50. Design 2-4 decoder with enable input E. 51. Design 3-8 decoder. 52. Design 4-16 decoder. 53. Design a combinational circuit that will multiply two two-bit binary values. 54. Design a combinational circuit that will accept a 2421 BCD code and drive a TIL- 312 seven segment display. 55. Realize the following Boolean function using the least number of ICs S= f(a,b,c,d,e) = (8,9,10,11,13,15,17,19,21,23,24,25,26,27,29,31) 56. Design a combinational logic circuit that will convert a straight BCD digit to an excess-3 BCD digit. a) Construct the truth table. b) Write the minterm list equation for each output function. c) Simplify each output function, and write the reduced logic equations. d) Draw the resulting logic diagram. 57. Draw the logic diagram for a 2-to-4 logic decoder with an active low encode and active high data outputs. Construct a truth table and identify the data inputs, the enable input, and the outputs. Describe the circuit s function. What does it do? Draw the logic symbol for the decoder. 58. Draw the logic symbol for a 3-to-8 logic decoder that has active low data inputs, an active high enable, and active low data outputs. Use such a decoder to realize the Boolean function X = f(a,b,c) = (0,3,5,6). 59. Realize the following functions with a decoder. Determine the size the decoder necessary for each Boolean function. a) A = f(x,y) = (0,3); B = f(x,y) = (1) b) X= f(a,b,c) = (1,3,5,7) c) X = f(a,b,c) = (2,5); Y = f(a,b,c) = (3,5,6) d) P = f(w,x,y,z) = (0,5,11) 60. Sketch the logic symbol for a 10-line to BCD encoder. Show how 10 events can be encoded into a four bit data bus. 61. Define the following: a) ALU b) Array multiplier c) BCD adder d) Comparator
e) Decoder f) Encoder g) Full adder and half adder h) Look-ahead carry i) Multiplexer. E. a) Design a combinational circuit that will multiply two two-bit binary values. (8) b) Design a 4 to 16 decoder using two 3 to 8 decoder (74LS138). (6) c) Design a keypad interface to a digital system using ten line BCD encoder (74LS147) (6) 62. Implement the full subtractor with two half adder and OR gate. 63. Using only half adder, draw a circuit that will add 3-bits x i y i z i together,producing carry & sum bits S i,c I as shown in following table. Xi yi zi ci si 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 64. Give the truth table for half adder and full adder, develop the simplified expression for sum & carry of a full adder & realize the full adder using only half adder. 65. Design a full adder & full subtractor,give their truth table,simplified expression and circuit Diagrams. 66. Define full adder & half adder, explain the working of it with an example. 67. Design 2-bit adder circuit using two level NAND gate circuit for each output. The inputs are 2- bit binary number s a1a0 & b1b0,the output s are the 2-bit binary sum s1s0 & carry output c1 only. 68. Implement in FULL ADDER circuit using a 3:8 decoder and two OR gates. 69. Using truth table and k map simplification show implementation of a FULL ADDER
70. Implement the Boolean function: F(A,B,C,D)= m(0,1,2,3,4,8,9,14,15) using an 8:1 MUX. 71. Sketch a diagram illustrating how a digital multiplexer is like a channel selector switch on an old TV. Explain in your own word what digital multiplexing means. 72. Sketch the logic symbol for a 8-to-1 digital multiplexer. Identify the data, select, and strobe inputs as well as the data outputs. Show how several data sources can be connected to a common data destination using a multiplexer. 73. Realize the following Boolean functions using the appropriate multiplexer, whose data inputs are connected directly to logical 1 and 0 levels. a) x = f(a,b,c) = (0,1,3,5,7) b) y = f(a,b,c,d) = (1,4,5,7,8,12,13,15) 74. Design a full adder a) Construct the truth table, and simplify the output equations. b) Draw the resulting logic diagram. c) Realize the adder using a decoder. d) Which design takes fewer ICs. 75. Design a full subtractor. a) Construct the truth table, and simplify the output equations. b) Draw the resulting logic diagram. c) Realize the subtractor using a decoder. 76. Write the logic equations for a two-stage look-ahead carry adder in terms of data and carry inputs. 77. Draw the block diagram for a single-cell look-ahead carry adder. Label all inputs and outputs. Describe the function of the look-ahead carry generator. 78. Design a four-bit comparator that propagates its secondary signals from left to right. a) Sketch a block diagram showing the primary inputs, secondary inputs and Outputs. b) Write the minterm list equations for the secondary outputs and the boundary Outputs. c) Simplify the output equations, and draw the resulting logic diagram. E. a) Design a binary full subtractor using minimum number of gates. (6) b) Explain the terms i) Ripple carry propagation ii) Propagation delay
iii) Look ahead carry iv) Iterative design. c) Realize F = f(x,y,z) = (1,2,4,5,7) using 8 to 1 multiplexer (74LS151). (4) d) Design a two bit binary magnitude comparator (6) 79. Mention the difference between combinational & sequential circuits with block diagram 80. Difference between Latch & Flip flop give example. 81. Define clocked sequential circuit. 82. Explain the operation of SR flip flop. 83. What is Race round condition. Explain. 84. Explain the operation of JK flip-flop. With logic diagram, characteristic table. 85. Discuss how unstable condition S=R=1 is avoided in storage latch of the following a) D latch b) JK flip flop c) T flip flop 86. Explain clocked RS flip flop with logic diagram. 87. Show that clocked D flip-flop can be reduced by one gate. 88. Explain how D & T flip flop works with logic diagram. 89. Discuss about flip flop excitation table write excitation table for SR, JK flip flops. 90. Design sequential circuit with JK flips flops to satisfy the following state equations. A (t+1) = A 1 B 1 CD+A 1 B 1 C+ACD+AC 1 D 1 B (t+1) =A 1 C+CD 1 +A 1 BC 1 C (t+1) = B, D (t+1) = D 1 91. a) Explain positive edge triggered D flip-flop. b) Explain negative edge triggered D flip-flop. 92. Explain the operation of Master slave JK flip flop with circuit diagram. Give benefits of it. 93. Discuss why condition S=R=1 leads to unstable condition for SR latch construct state diagram for following table, what is the logic equation for output variable Z. 0 1 A D/1 B/0
B D/1 C/0 C D/1 A/0 D B/1 C/0 Examine 7476 Jk flip flop, discuss why PRE1 & CLR1 inputs are refereed to as asynchronous inputs. While JK are called synchronous inputs. E. a) Explain with timing diagram the working of a S R latch as a switch debouncer. (6) b) Explain the working of a Master slave JK Flip-Flop with functional table and timing diagram. Show how race around condition of master-slave SR Flip-Flop is over come. (8) c) What is the significance of edge triggering? Explain the working of edge triggered D-flip-flop and T-flip-flop with their functional table. (6) 94. Mention the capabilities of shift register. 95. Explain universal shift register (74194). 96. Design synchronous BCD counter using JK flip flops. 97. Explain how shift register can be used as counters. 98. Mention the difference between ripple & synchronous counters. 99. Discuss shift registers. 100. Discuss state table, state diagram, and state equation with example. 101. Discuss the procedure for designing sequential circuits. 102. Define counter, & write state diagram for 3-bit binary counter. 103. Explain registers. 104. Design the binary counters having following repeated binary sequence. Use IC flip flops Only.0, 4,2,1,6. 105. Clearly distinguish between synchronous & asynchronous circuits, Combinational & sequential ckts, Latch & flip-flop 106. Design BCD counter with JK flip flops 107. Design a counter with following binary sequence a) 0,1,2 b) 0,1,2,3,4 c) 0,1,2,3,4,5,6 108. Discuss serial transfer of information from one register to other. 109. Give a block diagram of sequential circuit employing register as a part of sequential circuit. 110. Give logic diagram of 4 bit bi-directional shift register with parallel capability & briefly explain it s operation.
111. Give logic diagram of 4-bit binary ripple counter & BCD Ripple counter 112. Construct mod 6 counter using MSI chip. 113. Write the logic diagram of a 4 bit bi-directional shift register with parallel load capability and explain its operations. 114. Using logic circuit, truth table and timing diagram explain the operation of a JK Flip-flop.Show excitation table and the characteristics equation. 115. Design a counter that has a repeated sequence of SIX states shown in the state diagram. Use JK flip flops 0 1 2 4 3 5 6 116. Write short notes on: a) JK master slave flip flop b) Synchronous counter E. a) Obtain the characteristic equation for a SR flip-flop (4) b) With a neat circuit diagram, explain the working of a universal shift register. (8) c) Design a synchronous Mod-6 counter clocked JK flip-flop (8) 117. With timing diagram and transition table, explain the operation of 14 bit SISO shift register using D flip flop 118. Explain the structure and operation of Clocked synchronous sequential netwoks. 119. What are uses of Transition tables and Excitation tables. 120. Write short notes on a) Mealy and Moore Models. b) State Machine notation 121. Define the following terms a) Excitation table b) Next state and present state 122. Draw Mealy and Moore synchronous machine models. Label the excitation variables, state variables, input variables, and output variables in both diagrams 123. Explain why unused states generate don t-care terms when translating a state table to a transition table. Illustrate your response with a sample state table.
E. a) Explain Mealy and Moore sequential circuit models. (4) b) For the state machine M1 shown in Fig. obtain i) State table ii) Transition table iii) Exaltation table for T flip-flop iv) Logic circuit for T exaltation realization. (16) (Diagram will be discussed in theory class) 124. Write short notes on a) State Diagram and state table b) Transition table. 125. Construct a Mealy state diagram that will detect a serial input sequence of 10110. The detection of the required bit pattern can occur in a longer data string and the correct pattern can overlap with another pattern. When the input pattern has been detected, cause an output z to be asserted high. For example, let the input string be X = 1 0 1 1 0 1 1 0 1 1 0 Z = 0 0 0 0 1 0 0 1 0 0 1 126. Design a cyclic modulo-8 synchronous binary counter using J-K flip-flops that will count the number of occurrences of an input; that is, the number of times it is 1. The input variable x must be coincident with the clock to be counted. The counter is to count in binary. 127. Construct the state diagram for a Mealy sequential circuit that will detect the serial input sequence x = 010110. When the complete sequence has been detected, then cause output z to go high. 128. Construct the state diagram for a Mealy sequential machine that will detect the following input sequences: x= 01101 or 01111. If input sequence x = 01101 is met, cause z 1 = 1. If x = 01111, cause z 2 = 1. Each input sequence may overlap with itself or the other sequence. 129. Design a Moore sequential machine state diagram that will determine whether a four-bit serial input sequence is a legal 8-4-2-1 BCD code. If a legal BCD code sequence is detected, then z = 1. If an incorrect code is entered, then z = 0. 130. Design a decade counter using a binary state assignment and J-K flip flops such that when two external inputs (x and y) are coincident the counter will increment. A separate clock input provides state transition synchronization.
E. a) Construct a mealy state diagram that will detect a serial sequence of 10110. When the input pattern has been detected, cause an output Z to be asserted high. (8) b) Design a cyclic modulo-8 synchronous counter using J-K flip flop that will count the number of occurrences of an input; that is the number of times it is a 1. The input variable X must be coincident with the clock to be counted. The counter is to count in binary. (12) ----------