Unit I. Introduction Microcontrollers and Embedded processors Overview of the 8051 Inside the 8051 Addressing Modes

Unit I Introduction Microcontrollers and Embedded processors Overview of the 8051 Inside the 8051 Addressing Modes

1.1.1. Basic Introduction

1.1.1. Basic Introduction (contd.)

1.1.1. Basic Introduction (contd.)

1.1.2. Microcontroller and embedded processors (Difference between Microprocessor and microcontroller (contd.))

1.1.2. Microcontroller and embedded processors (Difference between Microprocessor and microcontroller (contd.))

1.1.2. Microcontroller and embedded processors (A Brief about embedded system) What is Embedded System? An embedded system is closely integrated with the main system It may not interact directly with the environment For example A microcomputer in a car ignition control An embedded product uses a microprocessor or microcontroller to do one task only There is only one application software that is typically burned into ROM

1.1.2. Microcontroller and embedded processors (A Brief about embedded system (contd.))

1.1.2. Microcontroller and embedded processors (Three criteria in Choosing a Microcontroller) meeting the computing needs of the task efficiently and cost effectively speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption easy to upgrade cost per unit availability of software development tools assemblers, debuggers, C compilers, emulator, simulator, technical support wide availability and reliable sources of the microcontrollers

1.1.3. Overview of 8051 (8051 Basic Component) Intel Introduced 8051, reffered as MCS-51, in 1981 4K bytes internal ROM 128 bytes internal RAM Four 8-bit I/O ports (P0 - P3). Two 16-bit timers/counters One serial interface 8051 by other manufacturers are code compatible CPU I/O Port RAM Timer ROM Serial COM Port A single chip Microcontroller

1.1.3. Overview of 8051 (Other 8051 features) only 1 On chip oscillator (external crystal) 6 interrupt sources (2 external, 3 internal, Reset) 64K external code (program) memory(only read)psen 64K external data memory(can be read and write) by RD,WR Code memory is selectable by EA (internal or external) We may have External memory as data and code Full duplex serial data transmitter/receiver 4 Register banks and 8 bit program status word and stack pointer Direct bit and byte addressability Interrupt structure with two priority levels Signed overflow detection and parity computation Integrated boolean processor for control applications Full depth stack for subroutine return linkage and data storage.

Chapter 2 1. Inside the 8051 2. Addressing Modes

1.2.1 Inside the 8051

1.2.1. Inside the 8051(contd.)

1.2.1. Inside the 8051(contd.)

1.2.1. Inside the 8051(contd.)

1.2.1. Inside the 8051(contd.)

1.2.1. Inside the 8051(contd.)

1.2.1. Inside the 8051(contd.)

1.2.2. Addressing Modes

1.2.2. Addressing Modes (Immediate addressing mode)

1.2.2. Addressing Modes (Immediate addressing mode (contd.))

1.2.2. Addressing Modes (Register addressing mode)

1.2.2. Addressing Modes (Accessing Memory Direct addressing mode)

1.2.2. Addressing Modes (Accessing Memory SFR Registers and Their Addresses)

1.2.2. Addressing Modes (Accessing Memory SFR Registers and Their Addresses (contd.))

1.2.2. Addressing Modes (Accessing Memory SFR Registers and Their Addresses (contd.))

1.2.2. Addressing Modes (Accessing Memory SFR Registers and Their Addresses (contd.)) Example:-

1.2.2. Addressing Modes (Accessing Memory Stack & Direct addressing mode)

1.2.2. Addressing Modes (Accessing Memory Register Indirect addressing mode)

1.2.2. Addressing Modes (Accessing Memory Register Indirect addressing mode (contd.)) Advantage of register indirect addressing mode:-

1.2.2. Addressing Modes (Accessing Memory Register Indirect addressing mode (contd.))

1.2.2. Addressing Modes (Accessing Memory Register Indirect addressing mode (contd.))

1.2.2. Addressing Modes (Accessing Memory Register Indirect addressing mode (contd.)) Limitation of register indirect addressing mode:-

1.2.2. Addressing Modes (Accessing Memory Indexed addressing mode and on chip ROM access)

1.2.2. Addressing Modes (Accessing Memory Indexed addressing mode and on chip ROM access (contd.))

1.2.2. Addressing Modes (Accessing Memory Indexed addressing mode and on chip ROM access (contd.))

Unit - II Introduction to 8051 assembly programming Assembling and running an 8051 program The program counter and ROM space in the 8051 8051 data types and directives 8051 flag bits and the PSW register 8051 register banks and stack Bit addressability Jump loop and call instructions 8051 I/O programming I/O bit manipulation programming

Chapter - 1 1. Introduction to 8051 assembly programming 2. Assembling and running an 8051 program 3. The program counter and ROM space in the 8051

2.1.1. Introduction to 8051 assembly programming

2.1.1. Introduction to 8051 assembly programming (contd.)

2.1.1. Introduction to 8051 assembly programming (contd.)

2.1.2. Assembling and running an 8051 program

2.1.2. Assembling and running an 8051 program (contd.)

2.1.2. Assembling and running an 8051 program (contd.)

2.1.2 Assembling and running an 8051 program (contd.) (Steps to create a program)

2.1.2. Assembling and running an 8051 program (contd.)

2.1.3. The program counter and ROM space in the 8051

2.1.3. The program counter and ROM space in the 8051 (contd.) Power Up : -

2.1.3. The program counter and ROM space in the 8051 (contd.) Placing code in ROM

2.1.3. The program counter and ROM space in the 8051 (contd.) Placing code in ROM (contd.)

2.1.3. The program counter and ROM space in the 8051 (contd.) Executing Program

2.1.3. The program counter and ROM space in the 8051 (contd.) Executing Program (contd.)

2.1.3. The program counter and ROM space in the 8051 (contd.) ROM memory map in 8051 family

Chapter - 2 1. 8051 data types and directives 2. 8051 flag bits and the PSW register 3. 8051 register banks and stack

2.2.1. 8051 data types and directives

2.2.1. 8051 data types and directives (contd.)

2.2.1. 8051 data types and directives (contd.)

2.2.1. 8051 data types and directives (contd.)

2.2.1. 8051 data types and directives (contd.)

2.2.2. 8051 flag bits and the PSW register

2.2.2. 8051 flag bits and the PSW register (contd.)

2.2.2. 8051 flag bits and the PSW register (contd.)

2.2.2. 8051 flag bits and the PSW register (contd.)

2.2.2. 8051 flag bits and the PSW register (contd.)

2.2.2. 8051 flag bits and the PSW register (contd.)

2.2.3. 8051 register banks and stack

2.2.3. 8051 register banks and stack (contd.)

2.2.3. 8051 register banks and stack (contd.)

2.2.3. 8051 register banks and stack (contd.)

2.2.3. 8051 register banks and stack (contd.)

2.2.3. 8051 register banks and stack (contd.)

2.2.3. 8051 register banks and stack (contd.) Stack

2.2.3. 8051 register banks and stack (contd.) Stack

2.2.3. 8051 register banks and stack (contd.) Stack

2.2.3. 8051 register banks and stack (contd.) Stack

2.2.3. 8051 register banks and stack (contd.) Stack

2.2.3. 8051 register banks and stack (contd.) Stack

2.2.3. 8051 register banks and stack (contd.) Stack

2.2.3. 8051 register banks and stack (contd.) Stack

Addressing Modes (contd.) Accessing Memory Indexed addressing mode and on chip ROM access Continued from Unit 1

Addressing Modes (contd.) Accessing Memory Indexed addressing mode and on chip ROM access Continued from Unit 1

Addressing Modes (contd.) Accessing Memory Indexed addressing mode and on chip ROM access Continued from Unit 1

Chapter - 3 1) Bit addressability 2) Jump loop and call Instruction 3) 8051 I/O programming 4) I/O bit manipulation programming

2.3.1. Bit Addressability

2.3.1. Bit Addressability

2.3.1. Bit Addressability (contd.)

2.3.1. Bit Addressability (contd.)

2.3.1. Bit Addressability (contd.)

2.3.1. Bit Addressability (contd.)

2.3.1. Bit Addressability (contd.)

2.3.1. Bit Addressability (contd.)

2.3.1. Bit Addressability (contd.)

2.3.1. Bit Addressability (contd.)

2.3.1. Bit Addressability (contd.)

2.3.1. Bit Addressability (contd.)

2.3.1. Bit Addressability (contd.)

2.3.2. Jump, Loop and Call Instructions

Loop:- 2.3.2. Jump, Loop and Call Instructions

2.3.2. Jump, Loop and Call Instructions (contd.) Nested Loop:-

2.3.2. Jump, Loop and Call Instructions (contd.) Conditional Jump:-

2.3.2. Jump, Loop and Call Instructions (contd.) Conditional Jump (contd.):-

2.3.2. Jump, Loop and Call Instructions (contd.) Conditional Jump (contd.):-

2.3.2. Jump, Loop and Call Instructions (contd.) Unconditional Jump:-

2.3.2. Jump, Loop and Call Instructions (contd.) Unconditional Jump (contd.):- [Calculating Short Jump Address]

2.3.2. Jump, Loop and Call Instructions (contd.) Unconditional Jump (contd.):- [Calculating Short Jump Address]

2.3.2. Jump, Loop and Call Instructions (contd.) Call Instruction:-

2.3.2. Jump, Loop and Call Instructions (contd.) Call Instruction (LCALL):-

2.3.2. Jump, Loop and Call Instructions (contd.) Call Instruction-LCALL (contd.):-

2.3.2. Jump, Loop and Call Instructions (contd.) Call Instruction and Stack:-

2.3.2. Jump, Loop and Call Instructions (contd.) Call Instruction and Stack Use PUSH/POP in subroutine:-

2.3.2. Jump, Loop and Call Instructions (contd.) Call Instruction and Stack calling subroutine:-

2.3.2. Jump, Loop and Call Instructions (contd.) Call Instruction ACALL:-

2.3.2. Jump, Loop and Call Instructions (contd.) Call Instruction ACALL (contd.):-

2.3.2. Jump, Loop and Call Instructions (contd.) Time Delay:-

Time Delay (contd.):- 2.3.2. Jump, Loop and Call Instructions (contd.)

2.3.2. Jump, Loop and Call Instructions (contd.) Time Delay Calculation:-

2.3.2. Jump, Loop and Call Instructions (contd.) Time Delay Calculation increase delay using NOP:-

2.3.2. Jump, Loop and Call Instructions (contd.) Time Delay Calculation Large delay using nested loop:-

2.3.2. Jump, Loop and Call Instructions (contd.) Time Delay Calculation For other 8051 chips:-

2.3.2. Jump, Loop and Call Instructions (contd.) Time Delay Calculation For other 8051 chips (contd.):-

2.3.2. Jump, Loop and Call Instructions (contd.) Time Delay Calculation For other 8051 chips (contd.):-

2.3.3. 8051 I/O Programming

2.3.3. 8051 I/O Programming (contd.): 8051 Foot Print 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P1.0 P1.1 P1.2 P1.3 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (T0)P3.4 (T1)P3.5 XTAL2 XTAL1 GND (INT0)P3.2 (INT1)P3.3 (RD)P3.7 (WR)P3.6 Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8) 8051 (8031) (8751) (8951)

2.3.3. 8051 I/O Programming (contd.):

2.3.3. 8051 I/O Programming (contd.):

2.3.3. 8051 I/O Programming (contd.):

2.3.3. 8051 I/O Programming (contd.):

2.3.3. 8051 I/O Programming (contd.):

2.3.3. 8051 I/O Programming (contd.):

2.3.3. 8051 I/O Programming (contd.):

2.3.4. 8051 I/O Bit Manipulation Programming

2.3.4. 8051 I/O Bit Manipulation Programming