VERILOG QUICKSTART
VERILOG QUICKSTART by James M. Lee Cadence Design Systems, Inc. ~. " SPRINGER SCIENCE+BUSINESS MEDIA, LLC
ISBN 978-1-4613-7801-3 ISBN 978-1-4615-6113-2 (ebook) DOI 10.1007/978-1-4615-6113-2 Additional material to this book can be downloaded from http://extras.springer.com Library of Congress Cataloging-in-Publication Data A C.I.P. Catalogue record for this book is available from the Library of Congress. Copyright 1997 by Springer Science+Business Media New York Originally published by Kluwer Academic Publishers in 1995 Softcover reprint of the hardcover 1st edition 1995 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission of the publisher, Springer Science+Business Media, LLC. Printed on acid-free paper.
TABLE OF CONTENTS LIST OF FIGURES LIST OF EXAMPLES LIST OF TABLES xii xiv xix 1 INTRODUCTION 1 Framing Verilog Concepts 3 The Design Abstraction Hierarchy 3 Types of Simulation 4 Types of Languages 4 Simulation versus Programming 5 HDL Learning Paradigms 5 Where To Get More Information 7 Reference Manuals 8 Usenet 8 Talk Verilog 8 2 INTRODUCTION TO THE VERI LOG LANGUAGE 9 Identifiers 9 Escaped Identifiers 10 White Space 11 Comments 12 Numbers 12 Text Macros 13 Modules 14 Semicolons 14 Value Set 15 Strengths 15 Numbers, Values, and Unknowns 16
vi 3 STRUCTURAL MODEUNG Primitives Ports Ports in Primitives Ports in Modules Instances Hierarchy Hierarchical Names Top-Level Modules You Are Now Ready To Run Your First Simulations Exercise 1 The Hello Simulation Exercise 2 The 8-Bit Hierarchical Adder Verilog Quickstart 19 19 20 20 21 21 22 24 26 26 26 27 4 BEHAVIORAL MODEUNG Starting Places for Places for Blocks of Behavioral Code The initial Keyword The always Keyword Delays begin-end Blocks fork-join Blocks System Tasks for Printing Out Results What Is a System Task? $display and Its Relatives Other Commands To Print Results Writing to Files 48 Setting the Default Radix 50 Exercise 3 Printing Out Results from Wires Buried in the Hierarchy 51 Special Characters 51 Suppressing Spaces in Your Output 52 Data Objects in Verilog 55 Nets 55 Ranges 56 Implicit Nets 57 Registers 58 Memories 58 Integers and Reals 59 Time 60 Parameters 60 Events 61 Strings 61 Procedural Assignments 62 Ports and Registers 66 31 32 32 32 33 34 37 45 45 45 47
vii 5 OPERATORS Binary Operators Unary Operators Reduction Operators Ternary Operator Equality Operators Concatenations Logical versus Bit-wise Operations Operations That Are Not Legal on Reals Working with Strings Combining Operators Sizing Expressions 6 WORKING WITH BEHAVIORAL MODELING Continuous Assignment Event Control The if Statement The case Statement Exercise 4 Using Expressions and case Loops The forever Loop The repeat Loop The while Loop The for Loop Procedural Continuous Assignments tasks functions Exercise 5 Functions and Continuous Assignments A Reminder about Ports and Registers Modeling with inout Ports Named Blocks The disable Statement When is a Simulation Done? 7 USER-DEFINED PRIMITIVES Combinatorial UDPs Optimistic Mux Pessimistic Mux The Gritty Details Sequential UDPs UDP Instances The Final Details Exercise 6 Using UDPs 69 69 71 72 73 74 77 78 80 80 81 81 83 83 87 92 93 96 102 102 103 104 105 106 111 117 120 120 120 121 122 124 127 128 128 128 129 130 133 133 134
viii Verilog Quickstart 8 PARAMETERIZED MODULES 137 n-bit Mux 138 n-bit Adder 138 nbymmux 139 nbymram 140 Using Parameterized Modules 141 9 STATE MACHINES 143 State Machine Types 143 State Machine Modeling Style 145 State Encoding Methods 153 Default Conditions 155 Implicit State Machines 156 Registered and Unregistered Outputs 157 Factors in Choosing a State Machine Modeling Style 158 10 MODELING TIPS 159 Modeling Combinatorial Logic 159 Combinatorial Models Using Continuous Assignments 160 Combinatorial Models Using the always Block and regs 161 Combinatorial Models Using Functions 164 Modeling Sequential Logic 165 Sequential Models Using always 165 Sequential Models Using initial 165 Sequential Models Using tasks 168 Modeling Asynchronous Circuits 170 Modeling a One-Shot 170 Modeling Asynchronous Systems 171 Special-Purpose Models 177 Two-Dimensional Arrays 177 Z-Detectors 178 Multiplier Examples 179 A Proven, Successful Approach to Modeling 189 11 MODELING STYLE TRADE-OFFS 191 Forces That Influence Modeling Style 191 Evolution of a Model 192 Modeling Style and Synthesis 193 Is It Synthesizable? 194 Learning From Other People's Mistakes 195 When To Use UDPs 202
ix 12 TEST BENCHES AND TEST MANAGEMENT Introduction to Testing Model Size versus Test Volume Functional Testing Regression Testing Self-Checking Test Benches Sign-Off System Test versus Unit Tests Response-Driven Stimulus Test Benches for Inouts Loading Files into Verilog Memories Test Benches with No Test Vectors Using a Script To Run Test Cases Modeling BIST The Surround and Capture Method 13 COMMON ERRORS Mismatched Ports Missing or Incorrect Declarations Missing Registers Missing Widths Reversed Ranges Improper Use of Procedural Continuous Assignments Missing initial or always Blocks Zero-Delay always Loops initial Instead of always Missing Initialization Overly Complex Code Unintended Storage Timing Errors Negative Setup Time Zero-Delay Races 14 DEBUGGING A DESIGN Overview of Functional Debugging Where Are the Errors? Universal Techniques Printing Out Messages "I am here." Values The Log File Using Wavefonns Interactive Debugging Going Interactive 203 203 204 205 205 205 210 210 211 214 215 219 219 220 222 227 227 228 228 229 230 230 231 231 232 232 233 233 233 234 234 237 237 238 238 238 238 239 240 240 241 241
x Verilog Quickstart The Prompts 242 Special Keys in Interactive Mode 244 Command History 249 The Key File 252 Traversing and Observing 257 Back-Tracing Fan-In 261 Usingforce and release 262 Waveforms, Graphic User Interfaces, and Other Conveniences 263 Catching Problems Later in a Simulation 263 Isolating Differences in Models 265 Summary of Debugging 266 Appendix A GATE LEVEL DETAILS 269 Primitive Descriptions 269 Logic Gates 269 AJNIT) 269 NAJNIT) 270 OR 271 NOR 271 XOR 272 XNOR 272 Buffe~ 273 BUF 273 NOT 273 BUFIFO 274 BUFIFI 274 NOTIFO 275 NOTIFI 276 PULLDOWN 276 PULLUP 277 Switches 277 NMOS and RNMOS 278 PMOS and RPMOS 279 CMOS and RCMOS 280 TRAN and RTRAN 281 TRANIFO and RTRANIFO 281 TRANIFI and RTRANIFI 282 Instance Details 282 Delays 282 Delay Units 283 Printing Out Time and the Timescale 284 Strengths 284 Displaying strengths with %v 285 Strength reduction of switch primitives 286
xi Appendix B EXAMPLE SUMMARY INDEX 287 299
xii Verilog Quickstart LIST OF FIGURES Figure 1-1 Design Abstraction Hierarchy Figure 1-2 Gate-Level Model Mux Schematic Figure 2-1 Number Format Figure 2-2 The Mux Example Figure 2-3 Three-State Buffer Figure 2-4 Two Three-State Buffers Figure 3-1 AND Gate Primitives Figure 3-2 Gate-Level Model Mux Schematic Figure 3-3 Connecting Two Muxes Figure 3-4 Hierarchical4-Bit Mux Figure 3-5 Mux4 Hierarchy Expanded Figure 3-6 Adder Schematic Figure 3-7 Adder2 Schematic Figure 3-8 Adder4 Schematic Figure 3-9 Adder8 Schematic Figure 6-1 Connecting 4 Registers to a Wire Figure 6-2 Rotate Left Figure 6-3 Logical Shift Left with 0 Fill Figure 6-4 Rotate Right Figure 6-5 Logical Shift Right with 0 Fill Figure 6-6 ALU Test Vector File alu _test. vee Figure 7-1 Adder Using Five Built-In Primitives Figure 7-2 Adder Using Two UDPs Figure 9-1 Moore State Machine Figure 9-2 Mealy State Machine Figure 10-1 State Diagram for Alarm System Figure 11-1 Forces That Act on Modeling Style Figure 11-2 Synthesizablility Flowchart Figure 12-1 Test Bench for an inout Figure 12-2 Logic Surrounded by BIST Figure 12-3 Surround and Capture Method Figure A-I AND Gate Figure A-2 NAND Gate Figure A-3 OR Gate Figure A-4 NOR Gate Figure A-5 XOR Gate Figure A-6 XNOR Gate Figure A-7 BUF Gate Figure A-8 NOT Gate Figure A-9 BUFIFO Gate Figure A-1O BUFIFI Gate Figure A-II NOTIFO Gate 3 7 12 14 15 16 21 22 23 24 25 27 28 28 28 85 98 99 99 99 102 135 135 144 144 172 192 195 214 220 223 269 270 271 271 272 272 273 273 274 274 275
xiii Figure A-12 NOTIFI Gate Figure A-13 Pulldown Figure A-14 Pullup Figure A-IS NMOS orrnmos Transistor Figure A-16 PMOS orrpmos Transistor Figure A-17 CMOS or RCMOS Transistor 276 276 277 278 279 280
xiv Verilog Quickstart LIST OF EXAMPLES Example 1-1 Abstract Model of a Phone Example 1-2 Verilog for Gate-Level Mux Example 2-1 Simple Hello Module Example 2-2 Hello Module without White Space Example 2-3 Hello Module with Extra White Space Example 2-4 Illegal Use of White Space Example 2-5 Comments Example 2-6 Numbers Example 2-7 Specifying a Text Macro Example 2-8 Using a Text Macro Example 2-9 Gate-Level Mux Verilog Code Example 3-1 Verilog Code for the 2-Input and 4-Input AND Gates Example 3-2 Verilog for Gate-Level Mux Example 3-3 Hierarchical 2-Bit Mux Example 3-4 Hierarchical 4-Bit Mux Example 3-5 Hierarchical Names Example 3-6 Hello Verilog Example 3-7 Adder Test Module Example 4-1 An initial Block Example 4-2 An always Block Example 4-3 Three initial Statements Example 4-4 Three initial Statements with Delay Example 4-5 Simple begin-end Block Example 4-6 begin-end Block with Delay Example 4-7 Multiple begin-end Blocks Example 4-8 fork-join Blocks Example 4-9 Combining begin-end andfork-join Blocks Example 4-10 Displaying a String Example 4-11 Displaying a Single Value Example 4-12 Displaying Multiple Values Example 4-13 Using Format Specifiers with $display Example 4-14 Two $display Statements Example 4-15 Combining $write and $display Example 4-16 Writing to a File Example 4-17 Writing to Multiple Files Example 4-18 $display with $time Example 4-19 Leading Spaces in $monitor with $time Example 4-20 Spaces used to print an 8-Bit value Example 4-21 Suppressing Leading Spaces and Zeroes Example 4-22 Net Declarations Example 4-23 Incorrect Net Declaration Example 4-24 Setting Default Net Type 5 7 11 11 11 11 12 13 13 13 14 21 22 23 24 26 26 29 32 33 33 34 34 35 35 37 39 45 45 46 46 47 47 48 49 52 53 53 54 57 57 58
xv Example 4-25 Register Declarations Example 4-26 Selecting Bits and Parts of a Register Example 4-27 Memory and Register Declarations Example 4-28 Selecting Bits in Registers and Words in Memories Example 4-29 Declaring Integers and Reals Example 4-30 Declaring Variables of Type time Example 4-31 Parameters Example 4-32 Events Example 4-33 Strings Example 4-34 Simple Procedural Assignments Example 4-35 Procedural Assignments withfork-join Example 4-36 fork-join with Intra-assignment Delays Example 4-37 fork-join with Multiple Delays Example 4-38 fork-join with Simplified Delays Example 4-39 Effect of Intra-assignment Delays on Time Flow Example 4-40 Nonblocking Assignments Example 4-41 Output as a Register Example 5-1 Using Operators Example 5-2 Distinguishing between Bit-wise and Logical Operators Example 5-3 Using Reduction Operators Example 5-4 Ternary Operator Example 5-5 Using the Ternary Operator for a Three-State Buffer Example 5-6 Module To Test an Operator Example 5-7 Concatenations Example 5-8 Bit-wise and Logical operations Example 5-9 Operators and Strings Example 5-10 Combinations of operators for Exclusive-OR Example 6-1 Three-State Buffer Using a Continuous Assignment Example 6-2 A 128-Bit Adder in a Continuous Assignment Example 6-3 Continuous Assignment Multiplier Example 6-4 Connecting Four Registers to a Wire Example 6-5 Alternate Form of Continuous Assignment Example 6-6 Many Forms of Continuous Assignments Example 6-7 Waiting for an Event Example 6-8 Mux Using Continuous Assignment Example 6-9 Mux Using always Block Example 6-10 Incorrect Mux Example 6-11 Using the event Data Type Example 6-12 Using Events To Simplify Modeling Example 6-13 always Explained Example 6-14 Using wait Example 6-15 Using wait To Detect an Unknown Example 6-16 Using always To Detect an Unknown Example 6-17 Simple if Example 6-18 if with else 58 58 59 59 60 60 61 61 61 62 63 63 64 64 65 66 67 71 72 73 73 74 77 78 79 80 81 84 84 85 86 86 86 87 88 88 88 89 90 91 91 92 92 93 93
xvi Verilog Quickstart Example 6-19 Nested if with else 93 Example 6-20 The case Statement 94 Example 6-21 case Matching x and z 95 Example 6-22 Using casez 95 Example 6-23 Test Bench for the ALU 100 Example 6-24 Oscillator Using always 103 Example 6-25 Oscillator Using forever 103 Example 6-26 Repeating "Hello Veri log" 104 Example 6-27 Using repeat in a State Machine 104 Example 6-28 A while Loop 105 Example 6-29 A Simple for Loop 106 Example 6-30 Afor Loop with Expressions Not Referencing the Same Variable 106 Example 6-31 A Simple Flip-Flop 107 Example 6-32 A Flip-Flop with a Bad Reset 107 Example 6-33 A Flip-Flop with Reset 108 Example 6-34 A Flip-Flop with Incorrect Set and Reset 108 Example 6-35 A Flip-Flop with Correct Set and Reset 109 Example 6-36 Incorrect Mux 110 Example 6-37 Mux with PCA 110 Example 6-38 Hello Verilog Tasks 112 Example 6-39 task with Inputs, Outputs, and External References 113 Example 6-40 Effect of task Port Size 114 Example 6-41 Accessing a task Local Variable from Outside the task 114 Example 6-42 Task Local and Module Items with the Same Name 115 Example 6-43 Read Cycle task 116 Example 6-44 Count Bits Function 117 Example 6-45 Mux with Function and Continuous Assignment 118 Example 6-46 Divide Function Returning Two 8-Bit Values 119 Example 6-47 inout Port Connected to a Register 120 Example 6-48 Register with Controllable Connection to inout Port 121 Example 6-49 Named Blocks 122 Example 6-50 The disable Statement 122 Example 6-51 disable Used To Model Reset 123 Example 6-52 Controlling When a Simulation Finishes 125 Example 7-1 Optimistic Mux UDP 128 Example 7-2 Pessimistic Mux UDP 129 Example 7-3 One-Line UDP 130 Example 7-4 Level-Sensitive D Latch 130 Example 7-5 Edge-Sensitive D Flip-Flop 131 Example 7-6 Flip-Flop Using Explicit Edge Definitions 132 Example 7-7 initial Block in a UDP 133 Example 8-1 parameter Statements 138 Example 8-2 n-bit Wide 4-to-1 Mux 138 Example 8-3 Parameterized Width Adder 139 Example 8-4 Mux with Parameterized Width and Number of Inputs 139
xvii Example 8-5 Parameterized RAM Example 8-6 The defparam Statement Example 8-7 Using Parameterized Modules Example 9-1 Style 1 Moore State Machine Example 9-2 Style 1 Mealy State Machine Example 9-3 Style 2 Moore Machine Example 9-4 Style 2 Mealy Machine Example 9-5 Style 3 Mealy Machine Example 9-6 Style 4 Moore Machine Example 9-7 Style 5 Moore Machine Example 9-8 Implicit State Machine Style Example 9-9 Combinatorial Outputs Example 9-10 Registered Outputs Example 10-1 A 2-to-1 Mux Using Continuous Assignment Example 10-2 A 4-to-1 Mux Using Continuous Assignment Example 10-3 Alternate 4-to-1 Mux Using Continuous Assignment Example 10-4 An 8-Bit Adder Using Continuous Assignment Example 10-5 Latch Using Continuous Assignment Example 10-6 The 2-to-1 Mux Using always Example 10-7 The 4-to-1 Mux Using always Example 10-8 The 8-Bit Adder Using always Example 10-9 Simplified 8-Bit Adder Using always Example 10-10 Mux with Continuous Assignment and Function Example 10-11 Simple Counter Example 10-12 A Counter without always Example 10-13 Sequential Stimulus Block Example 10-14 Clock Source Example 10-15 Memory Exerciser Example 10-16 Tasks for Sequential Code Example 10-17 Basic One-Shot Example 10-18 Retriggerable One-Shot Example 10-19 Behavioral Description of the Alarm Example 10-20 Alarm Test Bench Example 10-21 Partial Implementation of Alarm Example 10-22 Two-Dimensional Array Example 10-23 Behavioral Z-detector Example 10-24 Structural Z-Detector Example 10-25 An 8-by-8 Booth Multiplier Example 10-26 Wallace 8-by-8 Multiplier Example 10-27 A 16-by-16 Multiplier Example 10-28 A 16-by-16 Wallace Multiplier for Signed Numbers Example 11-1 Normal D Flip-Flop Example 11-2 Modified D-Flip-Flop Example 11-3 Bad Register Example 11-4 Improved Register 140 141 141 147 148 148 149 150 151 152 156 157 157 160 160 161 161 161 162 163 163 164 164 165 166 166 166 167 168 170 171 172 174 176 178 178 179 179 181 183 186 193 193 196 197
xviii Verilog Quickstart Example 11-5 Tweaked Register 198 Example 11-6 Bad Adder 198 Example 11-7 Improved Adder 199 Example 11-8 Adder Reduced to a Continuous Assignment 199 Example 11-9 Bad Mux 200 Example 11-10 Improved Mux 200 Example 11-11 Bad Barrel Shifter 201 Example 11-12 Improved Barrel Shifter 202 Example 12-1 Adder Test Module Repeated 206 Example 12-2 Using Verilog To Calculate Responses 207 Example 12-3 Simplifying the Test Bench with a task 208 Example 12-4 Using a Second Module To Check the Results 209 Example 12-5 Printer Abstraction 211 Example 12-6 Printer Test Bench with Guessed Timing 212 Example 12-7 Response-Driven Printer Test Bench 213 Example 12-8 Test Bench for a RAM 215 Example 12-9 Memory Declaration 215 Example 12-10 Reversed Memory Declaration 216 Example 12-11 Memory File adder8.vee 216 Example 12-12 Adder Test Bench Reading from a File 217 Example 12-13 PROM Data File prom.dat 218 Example 12-14 Simple PROM 218 Example 12-15 Test Bench with No Vectors 219 Example 12-16 LFSR 221 Example 12-17 Testing the ALU with a LFSR and MISR 222 Example 12-18 ALU Modified Capture of Inputs and Outputs 224 Example 12-19 ALU Test Bench Repeated 224 Example 13-1 Missing Initialization 232 Example 13-2 Negative Setup Time 234 Example 13-3 Corrected Register 234 Example 14-1 Interactive Verilog Module 242 Example 14-2 Single-Stepping 244 Example 14-3 always Loop Module 248 Example 14-4 my.key Command File 255 Example 14-5 Hierarchical8-Bit Adder 258 Example A-I Delays in Primitive Instances 282 Example A-2 Time Scales 284 Example A-3 Strength Declarations 285
xix LIST OF TABLES Table 2-1 Radix Specifiers Table 2-2 Numbers and Their Values Table 3-1 Verilog Primitives Table 4-1 Format Specifiers Table 4-2 Screen and File Output Commands Table 4-3 Enumeration of All Output Commands Table 4-4 Format Specifiers Table 4-5 Net Types Table 5-1 Arithmetic Operators Table 5-2 Bit-wise Operators Table 5-3 Logical Operators Table 5-4 Negation Operators Table 5-5 Reduction Operators Table 5-6 Truth Table for Ternary Operator Table 5-7 Equality Operators Table 5-8 Truth Table for a = = b Table 5-9 Truth Table for a === b Table 5-10 Truth Table for a!= b Table 5-11 Truth Table for a!== b Table 5-12 Truth Table for a < b Table 5-13 Truth Table for a <= b Table 5-14 Truth Table for a > b Table 5-15 Truth Table for a >= b Table 5-16 Operator Order of Precedence Table 5-17 Operators Not Legal on Reals Table 6-1 Comparison of Procedural and Continuous Assignments Table 6-2 Summary of Case Values and Match per Case Type Table 6-3 ALU Exercise: Explanation of Opcodes Table 6-4 Summary of Assignment Types Table 7-1 Basic UDP Table Symbols Table 7-2 Symbols for Sequential UDP Tables Table 7-3 Summary of Instance Types Table 7-4 Complete List of UDP Table Symbols Table 9-1 State Machine Styles Table 9-2 Sequential State Encoding Table 9-3 Mapping State Code To Simplify Outputs Table 9-4 Gray State Encoding Table 9-5 States Compared with Outputs Table 9-6 Outputs as State Code Table 9-7 One-Hot State Encoding Table 14-1 Log File Options Table 14-2 Special Keys for Interactive Simulation 13 17 20 46 49 51 52 55 70 70 70 71 72 74 74 75 75 75 75 76 76 76 76 78 80 85 96 98 111 129 131 133 134 145 153 153 154 154 155 155 240 249
xx Verilog Quickstart Table 14-3 Keystroke-Related Commands 257 Table 14-4 Commands for Traversing and Observing 258 Table 14-5 The trace, save, and restart Commands 265 Table 14-6 Debugging Commands, Keystrokes, and Command-Line Options 266 Table A-I Logic Table for and Primitive 270 Table A-2 Logic Table for nand Primitive 270 Table A-3 Logic Table for or Primitive 271 Table A-4 Logic Table for nor Primitive 271 Table A-5 Logic Table for xor Primitive 272 Table A-6 Logic Table for xnor Primitive 272 Table A-7 Logic Table for bufprimitive 273 Table A-8 Logic Table for not Primitive 273 Table A-9 Logic Table for bufijd Primitive 274 Table A-lO Logic Table for bufifl Primitive 275 Table A-l1 Logic Tablefor notijd Primitive 275 Table A-12 Logic Table for notifl Primitive 276 Table A-13 Logic Table for nmos Primitive 278 Table A-14 Logic Table for rnmos Primitive 278 Table A-15 Logic Table for pmos Primitive 279 Table A-16 Logic Table for rpmos Primitive 279 Table A-17 Logic Table for cmos Primitive 280 Table A-18 Logic Table for rcmos Primitive 281 Table A-19 Delay and Precision Units 283 Table A-20 Strengths 285 Table A-21 Switch Strength Reduction 286