Chair for Network Architectures and Services Prof. Carle Department of Computer Science Technische Universität München.

Similar documents
Lecture 5: Performance Analysis I

EECS 122: Introduction to Computer Networks Switch and Router Architectures. Today s Lecture

Basic Switch Organization

QUALITY of SERVICE. Introduction

Master Course Computer Networks IN2097

Generic Architecture. EECS 122: Introduction to Computer Networks Switch and Router Architectures. Shared Memory (1 st Generation) Today s Lecture

Master Course Computer Networks IN2097

Network layer (addendum) Slides adapted from material by Nick McKeown and Kevin Lai

Computer Networks. Routing

Quality of Service (QoS)

ECEN Final Exam Fall Instructor: Srinivas Shakkottai

Congestion Control for High Bandwidth-delay Product Networks

CMPE 150/L : Introduction to Computer Networks. Chen Qian Computer Engineering UCSC Baskin Engineering Lecture 11

Master Course Computer Networks IN2097

Master Course Computer Networks IN2097

Master Course Computer Networks IN2097

EE 122: Router Design

CS321: Computer Networks Congestion Control in TCP

COE 431 Computer Networks. Welcome to Exam I Thursday April 02, Instructor: Wissam F. Fawaz

Overview. TCP & router queuing Computer Networking. TCP details. Workloads. TCP Performance. TCP Performance. Lecture 10 TCP & Routers

Master Course Computer Networks IN2097

Resource allocation in networks. Resource Allocation in Networks. Resource allocation

Congestion Control in TCP

CSE 3214: Computer Network Protocols and Applications Network Layer

The Network Layer and Routers

Homework 1 50 points. Quantitative Comparison of Packet Switching and Circuit Switching 20 points Consider the two scenarios below:

Overview. Implementing Gigabit Routers with NetFPGA. Basic Architectural Components of an IP Router. Per-packet processing in an IP Router

LS Example 5 3 C 5 A 1 D

EP2210 Scheduling. Lecture material:

Master Course Computer Networks IN2097

Introduction to Real-Time Communications. Real-Time and Embedded Systems (M) Lecture 15

Routing, Routers, Switching Fabrics

Master Course Computer Networks IN2097

Investigating the Use of Synchronized Clocks in TCP Congestion Control

Convergence of communication services

Chapter 4. Computer Networking: A Top Down Approach 5 th edition. Jim Kurose, Keith Ross Addison-Wesley, sl April 2009.

Congestion Control for High Bandwidth-delay Product Networks. Dina Katabi, Mark Handley, Charlie Rohrs

Chapter 4. Routers with Tiny Buffers: Experiments. 4.1 Testbed experiments Setup

CSCI Computer Networks

CMSC 332 Computer Networks Network Layer

Priority Traffic CSCD 433/533. Advanced Networks Spring Lecture 21 Congestion Control and Queuing Strategies

15-744: Computer Networking. Overview. Queuing Disciplines. TCP & Routers. L-6 TCP & Routers

Resource Allocation and Queuing Theory

Black Box Multicast Video-over-IP Solution

b. Suppose the two packets are to be forwarded to two different output ports. Is it

EECS 122: Introduction to Communication Networks Final Exam Solutions

Quality of Service in the Internet

Latency on a Switched Ethernet Network

Congestion Control in TCP

CS 268: Computer Networking

Scalable Concurrent Hash Tables via Relativistic Programming

===================================================================== Exercises =====================================================================

CPSC 441 Tutorial-1. Department of Computer Science University of Calgary

Linux Traffic Control

Congestion Control in TCP

Distributed Queue Dual Bus

Lecture 22: Buffering & Scheduling. CSE 123: Computer Networks Alex C. Snoeren

Overview Computer Networking What is QoS? Queuing discipline and scheduling. Traffic Enforcement. Integrated services

Computer Networks. Instructor: Niklas Carlsson

Cover sheet for Assignment 3

Latency on a Switched Ethernet Network

Master Course Computer Networks IN2097

Router Architectures

MUD: Send me your top 1 3 questions on this lecture

Multicast and Quality of Service. Internet Technologies and Applications

QoS on Low Bandwidth High Delay Links. Prakash Shende Planning & Engg. Team Data Network Reliance Infocomm

Router s Queue Management

6.033 Spring 2015 Lecture #11: Transport Layer Congestion Control Hari Balakrishnan Scribed by Qian Long

Scalability of Routing Protocols

MWC 2015 End to End NFV Architecture demo_

Small verse Large. The Performance Tester Paradox. Copyright 1202Performance

Impact of Traffic Aggregation on Network Capacity and Quality of Service

The Network Layer. Antonio Carzaniga. April 22, Faculty of Informatics University of Lugano Antonio Carzaniga

IV. PACKET SWITCH ARCHITECTURES

Affects of Queuing Mechanisms on RTP Traffic Comparative Analysis of Jitter, End-to- End Delay and Packet Loss

Introduction to Protocols

Congestion Control in Datacenters. Ahmed Saeed

A DiffServ transport network to bring 3G access to villages in the Amazon forest: a case study

CMSC 417. Computer Networks Prof. Ashok K Agrawala Ashok Agrawala. October 11, 2018

Precision and Accuracy of Packet Generators Who tests the testers?

Read Chapter 4 of Kurose-Ross

CSCI-1680 Link Layer Wrap-Up Rodrigo Fonseca

TCP Congestion Control : Computer Networking. Introduction to TCP. Key Things You Should Know Already. Congestion Control RED

Quality of Service in the Internet

CSCI-1680 Link Layer Wrap-Up Rodrigo Fonseca

ENSC 427 Communication Networks

Interface The exit interface a packet will take when destined for a specific network.

ECE453 Introduction to Computer Networks. Broadcast vs. PPP. Delay. Lecture 7 Multiple Access Control (I)

Network Superhighway CSCD 330. Network Programming Winter Lecture 13 Network Layer. Reading: Chapter 4

MoonGen. A Scriptable High-Speed Packet Generator. Paul Emmerich. January 31st, 2016 FOSDEM Chair for Network Architectures and Services

TCP in Asymmetric Environments

Chair for Network Architectures and Services Prof. Carle Department of Computer Science TU München. Übungsblatt 2

FIFO Service with Differentiated Queueing

Chapter 6 Connecting Device

ECE 650 Systems Programming & Engineering. Spring 2018

Next Steps Spring 2011 Lecture #18. Multi-hop Networks. Network Reliability. Have: digital point-to-point. Want: many interconnected points

Message Passing Models and Multicomputer distributed system LECTURE 7

Numerical approach estimate

Switched Ethernet Virtual LANs

COM-208: Computer Networks - Homework 1

Transcription:

Chair for Network Architectures and Services Prof. Carle Department of Computer Science Technische Universität München Network Analysis 2b) Deterministic Modelling beyond Formal Logic

A simple network model data / fragment link completed arrival queue processing When deterministic? Both arrival process and processing process deterministic. E.g. 1 arrival per 10 ms, processing takes 3 ms. Deterministic!= simple E.g. 3 arrivals at the same time every 100 ms is also deterministic. Can be more complex, processing can depend on size. Essential for being deterministic: events are known in advance (can be calculated) 2

Terminology Job completed Cycle time CycleTime Time from arrival till completion. Job Jobs arrive and will be processed by the system. We may often call them packets or other names in the context of networking. Queue Can be of limited or infinite size Has a queuing discipline: a way to order jobs (e.g. FIFO first in first out) 3

How realistic is that? Circuit Switching Link / network shared, yet the bits on the line belong to certain circuits so that they can be forwared immediately (e.g. classic telephony) Deterministic processing time Arrival deterministic unless user-side load is considered. Analysis like in chapter 1 (circuit switching, medium access in switches full-duplex networks, ) The network card puts a packet of a given size on the line. Serialization delay and propagation delay determine exactly the time T from A to D for a fixed packet size. Note, no matter when, the packet will always succeed to reach D after time T. A B t latency put bits on circuit D 4

Deterministic Modelling Now, is this anywhere near reality? Lets look at software router performance. Now, is this anywhere near reality? 5

Software Router Throughput Measurement Setup Goal: Measure the maximum throughput of a Software-Router Load Generator produces traffic with a constant bitrate Packet size 64 1518 Bytes Packet rate up to 14,88 million packets/s (= 10Gbit/s @ 64B packets) 1 4 concurrent flows (= 1 4 cores for packet processing) 6

SW-Router Input / Output Rates (64B Packets) Linear growth (input = output) of the output rate until the CPU is fully utilized Constant output rate at full CPU utilization (even more input does not affect the output rate) Roughly linear growth of maximum output with number of utilized cores Mpps = Million packets per second 7

SW-Router Maximum Packet Rates vs. Packet Size Each data point is an own measurement (as on the last slide) For small packet sizes the CPU is the bottleneck Constant packet rate Packet rate independent from packet size For large packet sizes the link speed (10 Gigabit/s) becomes the bottleneck Again, linear growth of packet rate with number of utilized cores 8

SW-Router Maximum Throughput vs. Packet Size Similar to the last slide, but with throughput (Gbit/s) instead of packet rate Linear growth with the packet size until hitting the link bottleneck at 10 Gbit/s 9

SW-Router Conclusions For the aggregate of the measurements Linear relationships have been found. Throughput directly related to situation-specific bottleneck. Seemingly deterministric behaviour. For individual packets the situation may be different. 10

Other forms of deterministic models It is common that algorithms and analysis ignore stochastic aspects. Situation, however: System is most likely not determinstic. Changes can occur. Chances for deterministic modelling Changing or random aspects are small and can be neglected for some kinds of analysis or in algorithms. System is assumed static for a certain amount of time. Change usually slower than actual problem. Random aspects less relevant for average case behaviour Significant change will trigger new analysis. 11

Other forms of deterministic Modelling Example: Routing / Link-state Routing Routers broadcast information about their links. All routers use this information to calculate a graph. The graph is seen as model for the network and algorithms operate in the graph. This graph is seen as fixed for some (unknown) time. Routing tables are calculated in the graph according to optimization goals. Usually based on a shortest path tree. So, forwarding tables in the routers assume that the entries are valid for a some period of time so that paths do not have to be searched for for every arriving packet. 12