Computer Systems and Networks. ECPE 170 Jeff Shafer University of the Pacific. Introduc>on to MARIE

Similar documents
Notes: The Marie Simulator

Computer Architecture. CSE 1019Y Week 16. Introduc>on to MARIE

Computer Organization II CMSC 3833 Lecture 33

Department of Computer and Mathematical Sciences. Lab 4: Introduction to MARIE

CC312: Computer Organization

Chapter 4. MARIE: An Introduction to a Simple Computer. Chapter 4 Objectives. 4.1 Introduction. 4.2 CPU Basics

Chapter 4. MARIE: An Introduction to a Simple Computer

The MARIE Architecture

Problem Points Your Points Total 80

MARIE: An Introduction to a Simple Computer

Chapter 4. Chapter 4 Objectives. MARIE: An Introduction to a Simple Computer

MARIE: An Introduction to a Simple Computer

Computer Systems and Networks. ECPE 170 Jeff Shafer University of the Pacific. MARIE Simulator

CSE100 Lecture03 Machines, Instructions, and Programs Introduction to Computer Systems

Chapter 4. Chapter 4 Objectives

2.2 THE MARIE Instruction Set Architecture

CS311 Lecture: The Architecture of a Simple Computer

CMSC 3833 Lecture 37

CDA 3103 Computer Organization Homework #7 Solution Set

Instruc=on Set Architecture

Instruc=on Set Architecture

CHAPTER 4 MARIE: An Introduction to a Simple Computer

a number of pencil-and-paper(-and-calculator) questions two Intel assembly programming questions

SCRAM Introduction. Philipp Koehn. 19 February 2018

Computer Systems and Networks. ECPE 170 Jeff Shafer University of the Pacific. Exam Review

Outcomes. Lecture 13 - Introduction to the Central Processing Unit (CPU) Central Processing UNIT (CPU) or Processor

Fundamentals of Computer Architecture. 8. Bringing It All Together The Hardware Engineer s Perspective

CPU ARCHITECTURE. QUESTION 1 Explain how the width of the data bus and system clock speed affect the performance of a computer system.

MARIE: An Introduction to a Simple Computer

Macro Assembler. Defini3on from h6p://

Chapter 4. MARIE: An Introduction to a Simple Computer 4.8 MARIE 4.8 MARIE A Discussion on Decoding

COMARCH. COMPUTER ARCHITECTURE TERM 3 SY COMPUTER ENGINEERING DE LA SALLE UNIVERSITY Quiz 1

UNIT V: CENTRAL PROCESSING UNIT

Floa=ng- Point Numbers

Computer Organization and Technology Processor and System Structures

CHAPTER 5 A Closer Look at Instruction Set Architectures

William Stallings Computer Organization and Architecture

ECE 375 Computer Organization and Assembly Language Programming Winter 2018 Solution Set #2

A3 Computer Architecture

Assembly Language Programming of 8085

Machine code. Nils Jansen December 12, 2017

10/31/2016. The LC-3 ISA Has Three Kinds of Opcodes. ECE 120: Introduction to Computing. ADD and AND Have Two Addressing Modes

Machine Language and Assembly Language

Computer architecture Assignment 3

Processor Architecture

Module 5 - CPU Design

CPU Structure and Function

Teaching London Computing

Micro-Operations. execution of a sequence of steps, i.e., cycles

CHAPTER 5 A Closer Look at Instruction Set Architectures

Lecture 4: MIPS Instruction Set

LC-3 Instruction Set Architecture

Computer Architecture 2/26/01 Lecture #

Chapter 5. Computer Architecture Organization and Design. Computer System Architecture Database Lab, SANGJI University

Chapter 2 Instruction Set Architecture

Programming Level A.R. Hurson Department of Computer Science Missouri University of Science & Technology Rolla, Missouri

Hardware Level Organization

General purpose registers These are memory units within the CPU designed to hold temporary data.

CHAPTER 5 A Closer Look at Instruction Set Architectures

William Stallings Computer Organization and Architecture

Understand the factors involved in instruction set

Wednesday, February 4, Chapter 4

Instruction Set Architecture

Högnivåspråk och översättning

Instruc=on Set Architecture

Processing Unit CS206T

Chapter 16. Control Unit Operation. Yonsei University

Register Are Two Names For The Same Place

MIPS Instruc,ons CS 64: Computer Organiza,on and Design Logic Lecture #8

Reading assignment. Chapter 3.1, 3.2 Chapter 4.1, 4.3

William Stallings Computer Organization and Architecture. Chapter 11 CPU Structure and Function

Instruction Set II. COMP 212 Computer Organization & Architecture. COMP 212 Fall Lecture 7. Instruction Set. Quiz. What is an Instruction Set?

The Institution of Engineers - Sri Lanka

Wednesday, September 13, Chapter 4

CPU Structure and Function. Chapter 12, William Stallings Computer Organization and Architecture 7 th Edition

Example of A Microprogrammed Computer

Introduction to CPU architecture using the M6800 microprocessor

EC 413 Computer Organization

Instructor: Randy H. Katz hap://inst.eecs.berkeley.edu/~cs61c/fa13. Fall Lecture #7. Warehouse Scale Computer

OSIAC Read OSIAC 5362 posted on the course website

Unit II Basic Computer Organization

LC-3 Instruction Set Architecture. Textbook Chapter 5

CPU Structure and Function

Assembly Language Programming of 8085

DC57 COMPUTER ORGANIZATION JUNE 2013

ISA and RISCV. CASS 2018 Lavanya Ramapantulu

William Stallings Computer Organization and Architecture 8 th Edition. Chapter 11 Instruction Sets: Addressing Modes and Formats

Programming the 8051/8052

CS 61C: Great Ideas in Computer Architecture. MIPS Instruc,on Representa,on II. Dan Garcia

Author : Dalbir Singh, Computer Science Deptt. CPU Structure and Functions. 1. Processor Organization

CHAPTER 5 Basic Organization and Design Outline Instruction Codes Computer Registers Computer Instructions Timing and Control Instruction Cycle

Computer Organization CS 206 T Lec# 2: Instruction Sets

Class Notes. Dr.C.N.Zhang. Department of Computer Science. University of Regina. Regina, SK, Canada, S4S 0A2

Course Schedule. CS 221 Computer Architecture. Week 3: Plan. I. Hexadecimals and Character Representations. Hexadecimal Representation

The Assembly Language of the Boz 5

Faculty of Engineering Systems & Biomedical Dept. First Year Cairo University Sheet 6 Computer I

CPU: SOFTWARE ARCHITECTURE INSTRUCTION SET (PART

Lecture-12 INTERNAL ARCHITECTURE OF INTEL 8085: The Functional Block Diagram Of 8085 Is Shown In Fig 16.

IA-32 architecture. PDP8/e architecture Arithmetic. IA-32 architecture (cont)

Microcontroller Systems

Transcription:

ECPE 170 Jeff Shafer University of the Pacific Introduc>on to MARIE

2 Schedule Today Introduce MARIE Wed 15 th and Fri 17 th Assembly programming tutorial

3 Recap MARIE Overview How does the MARIE architecture represent posieve/negaeve numbers? Binary, two s complement data representa>on How is MARIE s main memory configured? (# of words, size of each word) 4K words, 16 bits wide, word- addressable

4 Recap MARIE Overview MARIE has seven registers for control and data movement AC? MAR? MBR? PC? IR? InReg? OutReg?

5 Recap MARIE Data Path Common data bus Links main memory and registers Each device iden>fied by unique number Bus has control lines that iden>fy device used in opera>on Dedicated data paths Permits data transfer between accumulator (AC), memory buffer register (MBR), and ALU without using main data bus

6 Recap MARIE ISA What is an InstrucEon Set Architecture (ISA)? Interface between hardware and sotware Specifies the format of processor instruc>ons Specifies the primi>ve opera>ons the processor can perform

7 Recap MARIE Instructions (Full) Binary Hex InstrucEon Meaning 0001 1 LOAD X Load contents of address X into AC 0010 2 STORE X Store contents of AC at address X 0011 3 ADD X Add contents of address X to AC 0100 4 SUBT X Subtract contents of address X from AC 0101 5 INPUT Input value from keyboard into AC 0110 6 OUTPUT Output value in AC to display 0111 7 HALT Terminate program 1000 8 SKIPCOND Skip next instruc>on on condi>on based on AC value 1001 9 JUMP X Load value of X into PC 1010 A CLEAR Set AC to 0 1011 B ADDI X Add contents of address Mem[X] to AC 1100 C JUMPI X Load contents of address Mem[X] into PC 1101 D LOADI X Load contents of address Mem[X] into AC 1110 E STOREI X Store contents of AC at address Mem[X] See table 4.7 in book!

8 Recap MARIE Instructions How does MARIE format instruceons in computer memory? Two fields Opcode (4 bits) Opera>on code Address (12 bits) Address to operate to/from

9 MARIE Programming

10 A Simple Program Consider this simple MARIE program

11 A Simple Program What happens inside the computer when our program runs? Instruc>on 1: LOAD 104

12 A Simple Program Instruc>on 2: ADD 105

13 Assembler

14 Role of Assembler Mnemonic instruc>ons: LOAD 104 Easy for humans to write and understand Impossible for computers to understand Role of assembler Translate instruc>ons from assembly language (for humans) into machine language (for computers)

15 Assembler versus Compiler What s the difference between an assembler and a compiler? Which has the harder job? Assembly language è machine language One- to- one correspondence Assembler is simple! High- level language è machine language Many- to- one correspondence Compiler is complicated!

16 Assembler Operation Assemblers create an object file (containing machine code) from mnemonic assembly source code in two passes Pass 1 Assemble as much of the program as possible Builds a symbol table (contains memory references for all symbols in the program) Pass 2 Complete instruc>ons. Fill in addresses stored in the symbol table

17 Assembler Operation Example program HEX and DEC direc>ves to specify radix of constants Assembler Pass #1 Create symbol table Create par>ally- assembled instruc>ons Symbol Table: Name, Address ParEally- Assembled Program:

18 Assembler Operation Assembler Pass #2 Fill in details from symbol table Program Symbol Table Machine Code

19 Assembler Operation Program: Machine Code: Symbol Table:

20 More MARIE Instructions

21 New Addressing Modes! Direct addressing mode All the instruc8ons covered to date The address of the operand is explicitly stated in the instruc>on New: Indirect addressing mode The address of the address of the operand is given in the instruc>on Just like pointers in COMP 51/53

22 Indirect Addressing Mode Instructions Four new instruc>ons use indirect addressing mode: Load / store / add / jump indirect LOADI X and STOREI X specified the address of the address of the operand to be loaded or stored In RTL : LOADI X STOREI X MAR X MBR M[MAR] MAR MBR MBR M[MAR] AC MBR MAR X MBR M[MAR] MAR MBR MBR AC M[MAR] MBR

23 Indirect Addressing Mode Instructions ADDI X - Combina>on of LOADI X and ADD X: In RTL: ADDI X MAR X MBR M[MAR] MAR MBR MBR M[MAR] AC AC + MBR

24 Subroutine Instructions Remember subrou>nes? (i.e. func>ons) Machine instruc>ons can make subrou>nes easier to implement Jump- and- store instruc>on (JNS X) provides limited subrou>ne func>onality Does JNS permit recursive calls? RTL: MBR PC MAR X M[MAR] MBR MBR X AC 1 AC AC + MBR PC AC No, PC is stored at address X, and we jump to address X+1. You can t do this repeatedly!

25 Clear Instruction CLEAR instruc>on Set the contents of the accumulator to all zeroes. RTL for CLEAR: AC 0

26 MARIE Instructions (Full) Binary Hex InstrucEon Meaning 0001 1 LOAD X Load contents of address X into AC 0010 2 STORE X Store contents of AC at address X 0011 3 ADD X Add contents of address X to AC 0100 4 SUBT X Subtract contents of address X from AC 0101 5 INPUT Input value from keyboard into AC 0110 6 OUTPUT Output value in AC to display 0111 7 HALT Terminate program 1000 8 SKIPCOND Skip next instruc>on on condi>on based on AC value 1001 9 JUMP X Load value of X into PC 1010 10 CLEAR Set AC to 0 1011 11 ADDI X Add contents of address Mem[X] to AC 1100 12 JUMPI X Load contents of address Mem[X] into PC 1101 13 LOADI X Load contents of address Mem[X] into AC 1110 14 STOREI X Store contents of AC at address Mem[X] See table 4.7 in book!