Axilog: Language Support for Approximate Hardware Design

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Axilog: Language Support for Approximate Hardware Design Amir Yazdanbakhsh Divya Mahajan Bradley Thwaites Jongse Park Anandhavel Nagendrakumar Sindhuja Sethuraman Kar,k Ramkrishnan Nishanthi Ravindran Rudra Jariwala Abbas Rahimi Hadi Esmaeilzadeh Kia Bazargan Georgia Ins,tute of Technology University of Minnesota UC San Diego Georgia Ins,tute of Technology Alterna,ve Compu,ng Technologies (ACT) Lab DATE 2015

Approximate compu,ng Embracing error Relax the abstrac,on of near- perfect accuracy in general- purpose compu,ng/communica,on/storage Allow errors to happen during computa,on/ communica,on/storage Improve resource u,liza,on efficiency Energy, bandwidth, capacity, Improve performance Build acceptable systems from inten2onally- made unreliable souware and hardware components Avoid overkill and worst- case design 2

Avoiding Worst- Case Design Approximate Compu,ng Generality Applica,on Efficiency Performance Programming Language Compiler Architecutre Microarchitecture Cost Precision Reliability Determinism Cost Circuit Physical Device 3

Goals Criteria Design the first HDL for: 1) Approximate HW Design 2) Approximate HW Reuse 3) Approximate Synthesis Approximate HDL: 1) High- level 2) Automated 3) Backward compakble 4) Safety 4

Safety in Hardware Approximate Precise Precise Controller Clock Datapath 5

Axilog Annota,ons Design Annota,ons relax (relax_local) restrict (restrict_global) Reuse Annota,ons approximate crikcal bridge 6

Design AnnotaKons 7

Relaxing Accuracy Requirements module ripple_carry_adder(a, b, c_in, c_out, s) full_adder f0(a[0], b[0], c_in, w0, s[0]) full_adder f1(a[1], b[1], w0, c_out, s[1]) relax (s); b[1] a[1] b[0] a[0] c_in c_out s[1] w0 s[0] 8

Relaxing Accuracy Requirements module ripple_carry_adder(a, b, c_in, c_out, s) full_adder f0(a[0], b[0], c_in, w0, s[0]) full_adder f1(a[1], b[1], w0, c_out, s[1]) relax (s); b[1] a[1] b[0] a[0] c_in c_out s[1] w0 s[0] 9

Scoping Approxima,on (relax_local) module full_adder (a, b, c_in, c_out, s) relax_local (s); b[1] a[1] full_adder f0 () full_adder f1() relax (s[0]); b[0] a[0] c_in c_out s[1] w0 s[0] 10

Scoping Approxima,on (relax_local) module full_adder (a, b, c_in, c_out, s) relax_local (s); b[1] a[1] full_adder f0 () full_adder f1() relax (s[0]); b[0] a[0] c_in c_out s[1] w0 s[0] 11

Restric,ng Approxima,on clk rst x d0 d1 d2 d3 b0 b1 b2 b3 m0 m1 m2 m3 * * * * + + + a1 a2 a3 relax(y) y 12

Restric,ng Approxima,on clk rst x d0 d1 d2 d3 b0 b1 b2 b3 m0 m1 m2 m3 * * * * + a1 a2 a3 + restrict (w3) + relax(y) y 13

Restricting Approximation clk rst x d0 d1 d2 d3 b0 b1 b2 b3 m0 m1 m2 m3 * * * * restrict (w1) + restrict (w2) a1 a2 a3 + restrict (w3) + relax(y) y 14

Restric,ng Approxima,on Globally module full_adder(a, b, c_in, c_out, s); approximate output s; relax (s); endmodule restrict_global(s[31:0]); b[31] a[31] b[2] a[2] b[1] a[1] c_out a b c_in s b[0] a[0] c_in c_out s[31] s[2] s[1] s[0] 15

Restric,ng Approxima,on Globally module full_adder(a, b, c_in, c_out, s); approximate output s; relax (s); endmodule restrict_global(s[31:0]); b[31] a[31] b[2] a[2] b[1] a[1] c_out a b c_in s b[0] a[0] c_in c_out s[31] s[2] s[1] s[0] 16

Reuse AnnotaKons 17

Outputs Carrying Approximate Seman,cs p0 [7:0] p1 [7:0] p2 [7:0] p3 [7:0] p4 [7:0] p5 [7:0] p6 [7:0] p7 [7:0] sobel_filter approximate output r [4:0] r [7:5] 18

Cri,cal Inputs critical input reset; critical input clock; Next State Logic reset clock State Register Output Logic 19

Bridging Approximate Wires to Cri,cal Inputs and a1(s, a0, a1); relax (s); bridge (s); multiplexer m0(s, a0, a1, out); x0 critical input s a0 a1 a1 relax(s) bridge(s) x1 mux out m0 out 20

Bridging Approximate Wires to Cri,cal Inputs and a1(s, a0, a1); relax (s); bridge (s); multiplexer m0(s, a0, a1, out); x0 critical input s a0 a1 a1 relax(s) bridge(s) x1 mux out m0 out 21

Baseline Synthesis Flow Verilog Code Strict Timing Constraints yes Design Compiler Synthesized Netlist PrimeTime VX Timing Violation Baseline Netlist Highest frequency with minimum power and area 22

Relaxability Inference Analysis Circuit under analysis with Axilog annotakons IdenKfy the wires which are driving unannotated wires or annotated with restrict within the module under analysis IdenKfy the relaxed outputs of the instankated submodules Marks any wire that affects a globally restricted wire as precise Safe to approximate gates 23

Approximate Synthesis Flow Axilog Code Axilog Compiler Safe to Approximate Gates Strict & Relaxed Timing Constraints Design Compiler Synthesized Approximate Netlist SDF File Timing Simulation Input Data Set Quality Measurement Quality Requirement Satisfied yes no Final Approximate Netlist Synthesis Phase Quality Observation Phase 24

Measurements Tools for Synthesis and Energy Analysis Synopsys Design Compiler Synopsys Prime,me Timing SimulaKon with SDF back annotakons Cadence NC- Verilog Standard Cell Library TSMC 45- nm mul,- V t Slowest PVT corner (SS, 0.81V, 0C) for baseline results 25

Benchmarks Arithme,c Computa,on, Signal Processing, Robo,cs, Machine Learning, Image Processing FIR # lines: 113 Signal Processing # Annota,ons Design: 6 Reuse: 5 Sobel # lines: 143 Image Processing # Annota,ons Design: 6 Reuse: 3 Brent- Kung # lines: 352 Arithme,c Computa,on # Annota,ons Design: 1 Reuse: 1 Kogge- Stone # lines: 353 Arithme,c Computa,on # Annota,ons Design: 1 Reuse: 1 K- means # lines: 10,985 Machine Learning # Annota,ons Design: 7 Reuse: 3 Wallace Tree # lines: 13,928 Arithme,c Computa,on # Annota,ons Design: 5 Reuse: 3 ForwardK # lines: 18,282 Robo,cs # Annota,ons Design: 5 Reuse: 4 Neural Network # lines: 21,053 Machine Learning # Annota,ons Design: 4 Reuse: 3 InverseK # lines: 22,407 Robo,cs # Annota,ons Design: 8 Reuse: 4 26

Energy Reduc,on Energy Reduction 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 Error 5% Error 10% 27

Area Reduc,on 2.6 2.4 Error 5% Error 10% Area Reduction 2.2 2.0 1.8 1.6 1.4 1.2 1.0 28

Output Quality Degrada,on in Sobel 0% Quality Loss 5% Quality Loss 10% Quality Loss 10% Quality loss is nearly indiscernible to the eye yet provides 57% energy savings 29

Energy Reduc,on for Different PVT Corners 100% 90% 80% (SS, 0.81V, 0 C) (SS, 0.81V, 125 C) Energy Reduction 70% 60% 50% 40% 30% 20% 10% 0% 30

Axilog First HDL for Approxima,on Design Reuse Automa,on High- level Backward- compa,bility Safety Energy Savings 54% Area ReducKon 1.9 Code AnnotaKons 2-12 hpp://www.act- lab.org/ar,facts/axilog 31

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