ENCM 369 Winter 2013: Reference Material for Midterm #2 page 1 of 5 MIPS/SPIM General Purpose Registers Powers of Two 0 $zero all bits are zero 16 $s0 local variable 1 $at assembler temporary 17 $s1 local variable 2 $v0 return value 18 $s2 local variable 3 $v1 return value 19 $s3 local variable 4 $a0 argument 20 $s4 local variable 5 $a1 argument 21 $s5 local variable 6 $a2 argument 22 $s6 local variable 7 $a3 argument 23 $s7 local variable 8 $t0 temporary 24 $t8 temporary 9 $t1 temporary 25 $t9 temporary 10 $t2 temporary 26 $k0 used by O/S kernel 11 $t3 temporary 27 $k1 used by O/S kernel 12 $t4 temporary 28 $gp global pointer 13 $t5 temporary 29 $sp stack pointer 14 $t6 temporary 30 $fp frame pointer 15 $t7 temporary $ra return address n 2 n n 2 n n 2 n n 2 n 0 1 8 256 16 65,536 24 16,777,216 1 2 9 512 17 1,072 25 33,554,4 2 4 10 1,024 18 262,144 26 67,108,864 3 8 11 2,048 19 524,288 27 134,217,728 4 16 12 4,096 20 1,048,576 28 268,435,456 5 13 8,192 21 2,097,152 29 536,870,912 6 64 14 16,384 22 4,194,304 30 1,073,741,824 7 128 15,768 23 8,388,608 2,147,483,648 4,294,967,296 Midterm #2 Instruction Subset Zero-extending a 16-bit constant means generating a -bit value by copying the 16-bit constant to bits 15 0 of the -bit value and making bits 16 equal to 0. Sign-extending a 16-bit constant means generating a -bit value by copying the 16-bit constant to bits 15 0 of the -bit value and making bits 16 equal to bit 15 of the 16-bit constant. Real MIPS/MARS instructions add rdest, rsrc1, rsrc2 add register rsrc1 and register rsrc2 ; cause an exception on signed overflow, otherwise put result in register addu rdest, rsrc1, rsrc2 add register rsrc1 and register rsrc2, put result in register addi rdest, rsrc1, imm add register rsrc1 and sign-extended constant imm; cause an exception on signed overflow, otherwise put result in register
ENCM 369 Winter 2013: Reference Material for Midterm #2 page 2 of 5 addiu rdest, rsrc1, imm add register rsrc1 and sign-extended constant imm, put result in register sub rdest, rsrc1, rsrc2 subtract register rsrc2 from register rsrc1 ; cause an exception on signed overflow, otherwise put result in register subu rdest, rsrc1, rsrc2 subtract register rsrc2 from register rsrc1, put result in register slt rdest, rsrc1, rsrc2 put 1 in register rdest if register rsrc1 is less than rsrc2 using signed arithmetic, otherwise put 0 in register sltu rdest, rsrc1, rsrc2 put 1 in register rdest if register rsrc1 is less than rsrc2 using unsigned arithmetic, otherwise put 0 in register slti rdest, rsrc1, imm put 1 in register rdest if register rsrc1 is less than sign-extended constant imm using signed arithmetic, otherwise put 0 in register sltiu rdest, rsrc1, imm put 1 in register rdest if register rsrc1 is less than sign-extended constant imm using unsigned arithmetic, otherwise put 0 in register (It s a bit weird that the constant is sign-extended even though an unsigned comparison is done.) lw rdest, address copy word from memory at address to register sw rsrc, address copy word from register rsrc to memory at address. lb rdest, address copy byte from memory at address to bits 7 0 of register rdest, make bits 8 of rdest equal to bit 7 of that byte. lbu rdest, address copy byte from memory at address to bits 7 0 of register rdest, make bits 8 of rdest equal to 0. sb rsrc, address copy byte from bits 7 0 of register rsrc to memory at address. sll rdest, rsrc1, count shift value of register rsrc1 left by count bits, filling with 0 s from the right; put result in register srl rdest, rsrc1, count shift value of register rsrc1 right by count bits, filling with 0 s from the left; put result in register and rdest, rsrc1, rsrc2 do a bitwise and of register rsrc1 and register rsrc2, put result in register andi rdest, rsrc1, imm do a bitwise and of register rsrc1 and zero-extended constant imm, put result in register or rdest, rsrc1, rsrc2 do a bitwise or of register rsrc1 and register rsrc2, put result in register ori rdest, rsrc1, imm do a bitwise or of register rsrc1 and zero-extended constant imm, put result in register lui rdest, imm copy constant imm to bits 16 of register rdest, make bits 15 0 of rdest 0. nor rdest, rsrc1, rsrc2 do a bitwise nor of register rsrc1 and register rsrc2, put result in register
ENCM 369 Winter 2013: Reference Material for Midterm #2 page 3 of 5 beq rsrc1, rsrc2, label branch to instruction at label if value of register rsrc1 equals value of register rsrc2. bne rsrc1, rsrc2, label branch to instruction at label if value of register rsrc1 does not equal value of register rsrc2. j label jump to instruction at label. jal label copy the address of the instruction following the jal instruction to $ra, and jump to the instruction at label. jr reg jump to the instruction at the address in register reg. Two Pseudoinstructions la rdest, label copy address corresponding to label to register li rdest, imm copy constant imm to register Instruction formats for Chapter 4 MIPS subset R-type (ADD, SUB, AND, OR, SLT) 26 25 21 20 16 15 11 10 6 5 0 source source dest. 0 0 0 0 0 0 0 0 0 0 0 1 2 funct field LW and SW LW 1 0 0 0 1 1 pointer dest. SW 1 0 1 0 1 1 pointer source Note: lb and lbu are like lw, but have opcodes 100000 for lb and 100100 for lbu; sb is like sw, but has opcode 101000. BEQ source source 0 0 0 1 0 0 1 2 J 26 25 0 0 0 0 0 1 0 bits 27 2 of jump target address
ENCM 369 Winter 2013: Reference Material for Midterm #2 page 4 of 5 ALU specification for Chapter 4 computers A B operation 4 ALU Zero Overflow Result operation Result ( bits) Overflow (1 bit) 0000 bitwise AND of A and B always 0 0001 bitwise OR of A and B always 0 0010 -bit sum of A and B 1 on signed overflow, 0 otherwise 0110 -bit subtraction result for A B 1 on signed overflow, 0 otherwise 0111 SLT result for signed comparison always 0 A < B 1100 bitwise NOR of A and B always 0 The 1-bit signal called Zero is 1 if all bits of Result are 0, and is 0 if one or more bits of Result are 1.
ENCM 369 Winter 2013: Reference Material for Midterm #2 page 5 of 5 Figure 4.51 from the course textbook [Figure deleted from Web posting of this Reference Material booklet.] Names for some pipeline register fields in Figure 4.51 register field width description IF/ID IF/ID.PCPlus4 bits output of adder in IF stage IF/ID.Instruction bits instruction obtained in IF stage ID/EX ID/EX.PCPlus4 bits copied from IF/ID.PCPlus4 ID/EX.A bits output of Read data 1 from Registers ID/EX.B bits output of Read data 2 from Registers ID/EX.Immed bits output of Sign-extend unit ID/EX.RegisterRt 5 bits bits 20 16 copied from IF/ID.Instruction ID/EX.RegisterRd 5 bits bits 15 11 copied from IF/ID.Instruction EX/MEM EX/MEM.BranchTarget bits branch target from adder in EX stage EX/MEM.Zero 1 bit Zero output from ALU EX/MEM.Result bits Result output from ALU EX/MEM.B bits copied from ID/EX.B EX/MEM.RegisterRd 5 bits output of mux controlled by RegDst MEM/WB MEM/WB.MemData bits output of Read data from Data Memory MEM/WB.Result bits copied from EX/MEM.Result MEM/WB.RegisterRd 5 bits copied from EX/MEM.RegisterRd