The block diagram representation is given below: The output equation of a 2x1 multiplexer is given below:

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Experiment-3: Write VHDL programs for the following circuits, check the wave forms and the hardware generated a. multiplexer b. De-Multiplexer Objective: i. To learn the VHDL coding for Multiplexer and Demultiplexer ii. To understand the behavior of Multiplexer and Demultiplexer iii. To synthesize and simulate Multiplexer and Demultiplexer Theory: A multiplexer is a combinational circuit which has 2 N :1 input output ports with N and control ports. The control port is used to select one of the 2 N input and connect it to the output. A multiplexer is also called a switcher as it switches one of several input lines through to a single common output line. The block diagram representation is given below: The output equation of a 2x1 multiplexer is given below: Y = I 0. S + I 1. S The VHDL code for synthesizing the 2x1 multiplexer is given below in all the three style of modelling. VHDL CODING library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity MUX2x1 is Port ( I : in STD_LOGIC_VECTOR (1 downto 0 s : in STD_LOGIC; y : out STD_LOGIC end MUX2x1; architecture Behavioral of MUX2x1 is Y <= (I(0) and (not s)) or (I(1) and s end Behavioral; Behavioural Modelling of 2x1 multiplexer in VHDL library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux2x1_behave is Port ( i : in STD_LOGIC_VECTOR (1 downto 0 s : in STD_LOGIC; y : out STD_LOGIC end mux2x1_behave; architecture Behavioral of mux2x1_behave is mux2x1: process (i,s) if ( s='0') then

Y <= i(0 elsif( s='1') then Y <= i(1 else y <= 'Z'; end if; end process; end Behavioral; Designing a 4x1 multiplexer using 2x1 multiplexers in structural modelling A 4x1 multiplexer can be implemented in structural modelling using VHDL by using three 2x1 multiplexers. The block diagram and the VHDL code is shown below. VHDL CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity MUX4x1 is Port ( i : in STD_LOGIC_VECTOR (3 downto 0 s : in STD_LOGIC_VECTOR (1 downto 0 y : out STD_LOGIC

end MUX4x1; architecture Behavioral of MUX4x1 is signal w1,w2: std_logic; X1: entity work.mux2x1 port map X2: entity work.mux2x1 port map X3: entity work.mux2x1 port map end Behavioral; (I(0)=>I(0), I(1)=>I(1),s=>s(0), y=>w1 (I(0)=>I(2), I(1)=>I(3),s=>s(0), y=>w2 (I(0)=> w1, I(1)=>w2,s=>s(1), y=> Y Test Bench for MUX 4x1: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mux_4x1_tb IS

END mux_4x1_tb; ARCHITECTURE behavior OF mux_4x1_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT MUX4x1 PORT( i : IN std_logic_vector(3 downto 0 s : IN std_logic_vector(1 downto 0 y : OUT std_logic END COMPONENT; --Inputs signali : std_logic_vector(3 downto 0) := (others => '0' signal s : std_logic_vector(1 downto 0) := (others => '0' --Outputs signal y : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: MUX4x1 PORT MAP ( i =>i, s => s, y => y -- Stimulus process stim_proc: process

-- hold reset state for 100 ns. wait for 1000 ns; -- insert stimulus here i<= "0001"; s<= "00"; wait for 1000 ns; i<= "0001"; s<= "00"; wait for 1000 ns; i<= "0010"; s<= "01"; wait for 1000 ns; i<= "0100"; s<= "10"; wait for 1000 ns; i<= "1000"; s<= "11"; wait for 100 ns; wait; end process; END; Special Type of Mux: Now we move a step further in defining a multi-bit output multiplexer. Here we illustrate a mux2x1_4bit that accepts two four bit input number on its two input ports A and B. The sel input is used to select one of the two four bit input and passes it on the four bit output shared bus.

The general bloc for a MUX2x1_4bit is shown below followed by the VHDL concurrent style of modelling. VHDL CODE: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mux2_1_nbit_wide IS Generic ( N: integer :=4 PORT(in_a : IN STD_LOGIC_VECTOR(N DOWNTO 0 --input a in_b : IN STD_LOGIC_VECTOR(N DOWNTO 0 --input b sel : IN STD_LOGIC; --select input output : OUT STD_LOGIC_VECTOR(N DOWNTO 0) --data output END mux2_1_nbit_wide; ARCHITECTURE dataflow OF mux2_1_nbit_wide IS BEGIN WITH sel SELECT output<= in_a WHEN 0, in_b WHEN 1, (OTHERS => X ) WHEN OTHERS; END dataflow; OTHERS again Here we see OTHERS used to match cases where sel is not 1 or 0 in the WHEN OTHERS clause. i.e.: (OTHERS => X ) WHEN OTHERS; OTHERS is also used to provide a shorthand method of saying, make all the bits of the target signal X for however many bits are in target signal. (OTHERS => X ) WHEN OTHERS;

De-multiplexer: A de-multiplexer is a combinational circuit that behavior opposite to a multiplexer. It has a single input, S control inputs and 2S as output lines. Only one of the output will be activated by the control / selection lines and the input I will be transferred on the selected output line. Figure below shows the block diagram of the demultiplexer Output equations: Y0 = I.S1.S0 Y1 = I.S1.S0 Y2 = I.S1.S0 Y3 = I.S1.S0 VHDL Code: entitydemux is Port ( I : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0 Y : out STD_LOGIC_VECTOR (3 downto 0) enddemux; architecture Behavioral of DeMux is Y(0) <= I and (not S(1) ) and (not s(0) Y(1) <= I and (not S(1) ) and (s(0) Y(2) <= I and (S(1) ) and (not s(0) Y(3) <= I and (S(1) ) and (s(0) end Behavioral; TEST BENCH

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY DeMux_tb IS END DeMux_tb; ARCHITECTURE behavior OF DeMux_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT DeMux PORT( I : IN std_logic; S : IN std_logic_vector(1 downto 0 Y : OUT std_logic_vector(3 downto 0) END COMPONENT; --Inputs signal I : std_logic := '0'; signal S : std_logic_vector(1 downto 0) := (others => '0' --Outputs signal Y : std_logic_vector(3 downto 0 BEGIN -- Instantiate the Unit Under Test (UUT) uut: DeMux PORT MAP ( I => I, S => S, Y => Y -- Stimulus process stim_proc: process -- insert stimulus here wait for 100 ns; I <= '0'; S<= "00";

wait for 100 ns; I <= '1'; S<= "01"; wait for 100 ns; I <= '0'; S<= "10"; wait for 100 ns; I <= '1'; S<= "11"; wait; end process; END; Behavioural Modelling of De-Mux VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; entitydemux is Port ( I : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0 Y : out STD_LOGIC_VECTOR (3 downto 0) enddemux; architecture Behavioral of DeMux is

process(s,i) if (S="00") then Y <= "000"&I; elsif(s="01") then Y <= "00"&I&'0'; elsif (S="10") then Y <= '0'&I&"00"; else Y<= I&"000"; end if; end process; end Behavioral; SIMMULATION using ISIM

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