Sequential Statement

Sequential Statement

Sequential Logic Output depends not only on current input values but also on previous input values. Are building blocks of; Counters Shift registers Memories Flip flops are basic sequential logic devices. Sequential logic can be Synchronous or are asynchronous inputs Combinational Circuit Memory outputs

Sequential Logic Synchronous Sequential Logic Change in output due to current input values and current system state (history) to next state only takes place when a clock pulse is applied. Asynchronous Change in output due to current input values and current system state (history) to next state is triggered by completion of previous stage without reference to clock pulse.

VHDL Sequential Statement Statements that are executed one after the other like in software languages. Must be enclosed within PROCESS statement Four types of sequential statements IF statement CASE statement WAIT statement LOOP statement

IF statement Similar to Conditional Signal Assignment Assigns higher priority to statements that are at the top within the if statement Syntax IF conditions THEN assignments; ELSIF conditions THEN assignments; assignments; ELSIF conditions THEN assignments;... ELSE assignments;

IF... Statement Examples: IF (X = '1') THEN Q <= D; -------------------------------IF (k = 0) THEN X1 <= D; ELSE X1 <= Q; IF (a = 1) THEN Q <= D; ELSIF (a = 2) THEN Q <= NOT(D); ELSIF (a = 3) THEN Q <= '1'; ELSE Q <= '0';

IF statement Example:DFF with Asynchronous Reset LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY dff IS PORT ( d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC); END dff; ARCHITECTURE behavior OF dff IS PROCESS (clk, rst) IF (rst='1') THEN q <= '0'; ELSIF (clk'event AND clk='1') THEN q <= d; END PROCESS; END behavior;

Signals and Variables Signal and variable types can be used in Process statement Signal represents actual signal path in circuit Variable is a temporary storage for keeping data Signals are updated only at the end of the Process statement Variable is updated immediately after statement is evaluated ARCHITECTURE rtl OF reg IS SIGNAL a, b : std_logic; PROCESS (clk) IF(clk'event and clk = 1) THEN a <= d; b <= a; q <= b; END PROCESS; ARCHITECTURE rtl OF reg IS PROCESS (clk) VARIABLE a, b : std_logic; IF(clk'event and clk = 1) THEN a <= d; b <= a; q <= b; END PROCESS;

Signals and Variables SIGNALS Declared in declarative of Entity, Package or architecture SIGNAL mysig:datatype := intialvalue Can be local or global VARIABLES Declared only in a piece of sequential logic e.g. PROCESS VARABLE: varname:= initialvalue; Can only be local to the declarative process Cannot be passed of the process directly: assign to a signal first. Uses <= as an assignment operator Uses = as an assignment operator Value of a signal in a PROCESS is not updated at assignment but at the end of process execution. Value of VARABLE in a process is updated immediately after its assignment.

PROCESS Statement (revisited) ARCHITECTURE behavior OF dff IS PROCESS (clk, rst) either clk or rst signal changes, IF (rst='1') THEN IF statement will be executed. q <= '0'; ELSIF (clk'event AND clk='1') THEN q <= d; END PROCESS; END behavior;

PROCESS Statement Using signal attribute as a condition IF(clk'EVENT AND clk = '1') Rising Edge Falling Edge

WAIT Statement Wait statement can be used in PROCESS statement It works similarly to sensitivity list in PROCESS statement Syntax : WAIT UNTIL signal condition Example: ARCHITECTURE behavior OF dff IS PROCESS WAIT UNTIL (rising_edge(clk) OR rst = '1'); IF (rst='1') THEN q <= '0'; ELSIF (clk'event AND clk='1') THEN q <= d; END PROCESS; END behavior; rising_edge( ) and falling_edge( ) functions are implemented in std_logic_1164 library:

FOR...LOOP Statement When pieces of code need to be repeated several times, we put them in a loop Use FOR...LOOP when certain number of repetition is known Syntax: Example: FOR identifier IN range LOOP (sequential statements) END LOOP; FOR j IN 0 TO 3 LOOP qt(j+1) <= qt(j); END LOOP; -- OR -FOR k IN 3 DOWNTO 0 LOOP qt(k+1) <= qt(k); END LOOP

WHILE...LOOP Statement Use when number of repetition depends on certain condition Syntax: WHILE condition LOOP (sequential statements) END LOOP; Example: j = 0; WHILE j <= 3 LOOP qt(j+1) <= qt(j); j = j + 1; END LOOP;

CASE Statement Use for selecting assignment based on value of identifier Syntax: CASE identifier IS WHEN value => assignments; [assignments;] WHEN value => assignments; [assignments;]... END CASE; Example: CASE control IS WHEN "00" => x<=a; y<=b; WHEN "01" => x<=b; y<=c; WHEN OTHERS => x<="0000"; y<="zzzz"; END CASE;

Flip-Flop Modeling D Flip-Flop LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY D_FF IS PORT(d, clk: IN std_logic; q: OUT std_logic); END D_FF; ARCHITECTURE behavior OF D_FF IS PROCESS (clk) IF(clk'EVENT AND clk = '1') THEN q <= d; [Image taken from: Floyd, Digital Fundamentals, 10th Ed.] END PROCESS; END behavior;

Flip-Flop Modeling ENTITY JK_FF IS PORT (J, K, clk,: IN std_logic; Q: OUT std_logic); END JK_FF; ARCHITECTURE behavior OF JK_FF IS SIGNAL T: std_logic; -- Temporary signal PROCESS(clk) IF(clk'EVENT AND clk = '1') THEN IF(J = '0' AND K = '0') THEN T <= T; -- NO CHANGE ELSIF(J = '0' AND K = '1') THEN T <= '0'; -- RESET ELSIF(J = '1' AND K = '0') THEN T <= '1'; -- SET ELSIF(J = '1' AND K = '1') THEN T <= NOT(T); -- TOGGLE END PROCESS; Q <= T; -- Update output signal END behavior; [Image taken from: Floyd, Digital Fundamentals, 10th Ed.]

Flip-Flop Applications ENTITY JKCounter IS PORT(clk : in std_logic; Q0, Q1 : out std_logic); END JKCounter; Asynchronous Counter ARCHITECTURE Counter OF JKCounter IS SIGNAL J0, K0, J1, K1: std_logic := '1'; -- J&K are connected to '1 SIGNAL T0, T1: std_logic; JKFF0: PROCESS(clk) IF(clk'EVENT AND clk = '1') THEN IF(J0 = '0' AND K0 = '0') THEN T0 <= T0; -- NO CHANGE ELSIF(J0 = '0' AND K0 = '1') THEN T0 <= '0'; -- RESET ELSIF(J0 = '1' AND K0 = '0') THEN T0 <= '1'; -- SET ELSIF(J0 = '1' AND K0 = '1') THEN T0 <= NOT(T0); -- TOGGLE END PROCESS JKFF0; Q0 <= T0; (continue next page) [Image taken from: Floyd, Digital Fundamentals, 10th Ed.]

Flip-Flop Applications (cont'd) JKFF1: PROCESS(T0) IF(T0'EVENT and T0 = '1') THEN IF(J1 = '0' AND K1 = '0') THEN T1 <= T1; -- NO CHANGE ELSIF(J1 = '0' AND K1 = '1') THEN T1 <= '0'; -- RESET ELSIF(J1 = '1' AND K1 = '0') THEN T1 <= '1'; -- SET ELSIF(J1 = '1' AND K1 = '1') THEN T1 <= NOT(T1); -- TOGGLE END PROCESS JKFF1; Q1 <= T1; END Counter;

Flip-Flop Applications Counter revisited The previous counter example is not practical way of implementation We can generate circuit from its behavior without knowing what are the actual components that we need to use. For example, we can describe the behavior of counter using pseudo code as follows Counter_Output = 0 DO IF Clock = rising_edge THEN Increment Counter_Output by 1 LOOP forever

Type Conversion VHDL provide a standard package called "Unsigned Logic" This package allows us to do data type conversion i.e., from logic vector to integer Now we are able to do basic arithmetic operation on logic vector Example: We can write VHDL description of our asynchronous counter as follows:

Type Conversion library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity sync_counter is port(clk : in std_logic; output : out std_logic_vector(3 downto 0)); end sync_counter; architecture behavior of sync_counter is signal T: std_logic_vector(3 downto 0) := "0000"; begin process(clk) begin if(clk'event AND clk = '1') then T <= T+1; end if; end process; output <= T; end behavior;