Luxtera PN1000001 Silicon CMOS Photonic Chip Process Review 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com
Process Review Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. Chipworks Inc. 2012 all rights reserved. Chipworks and the Chipworks logo are registered trademarks of Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. PPR-1209-801 23962CYRK Revision 1.0 Published: November 30, 2012
Table of Contents Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Downstream Product 2.2 Luxtera PN1000001 Si CMOS Photonics Chip Package and Die 3 Package Analysis 3.1 Si CMOS Photonic Chip Assembly 3.2 Laser Module 4 PN1000001 Si CMOS Photonics Die General Process Analysis 4.1 General Device Structure 4.2 Bond Pad 4.3 Dielectrics 4.4 Metallization 4.5 Vias and Contacts 4.6 Transistors and Poly 4.7 Poly Resistor 4.8 Poly Capacitor 4.9 SOI, Isolation, and Substrate 5 PN1000001 Si CMOS Photonics Die Optical Devices 5.1 Single Polarization Grating Couplers 5.2 Waveguide 5.3 Optical Terminator, Directional Coupler, and Splitter 5.4 Mach-Zehnder Interferometer 5.5 Ge Photodetector 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions 7 References 8 Statement of Measurement Uncertainty and Scope Variation Appendices About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Molex 106410-1003 AOC 2.1.2 Molex 106410-1003 AOC Markings A 2.1.3 Molex 106410-1003 AOC Markings B 2.1.4 Molex 106410-1003 QSFP Connector Tilt View 2.1.5 Molex 106410-1003 QSFP Connector Front View 2.1.6 Molex 106410-1003 QSFP Connector Back View 2.1.7 Molex 106410-1003 QSFP Connector Side View 2.1.8 Molex 106410-1003 QSFP Connector PCB Front View 2.1.9 Molex 106410-1003 QSFP Connector PCB Back View 2.2.1 Chip Assembly on PCB 2.2.2 Chip Assembly on PCB X-Ray Plan-View 2.2.3 Chip Assembly Extracted from PCB Plan View 2.2.4 Chip Assembly Extracted from PCB Tilt View 2.2.5 Chip Assembly Extracted from PCB X- Ray Side View 2.2.6 Laser Module Photograph Top View 2.2.7 Laser Module X-Ray Plan View 2.2.8 Laser Module X-Ray Side View 2.2.9 Laser Module Corner A 2.2.10 Laser Module Corner C 2.2.11 Si CMOS Photonics Chip Die Photograph 2.2.12 PN1000001 Die Markings 2.2.13 Annotated PN1000001 Die Photograph 2.2.14 PN1000001 Die Corner 1 2.2.15 PN1000001 Die Corner 2 2.2.16 PN1000001 Die Corner 3 2.2.17 PN1000001 Die Corner 4 2.2.18 PN1000001 Minimum Pitch Bond Pads 2.2.19 Si CMOS Photonics Chip Die Delayered to Polysilicon 2.2.20 Annotated Si CMOS Photonics Chip Die Delayered to Polysilicon 2.2.21 Standard Logic Overview 2.2.22 NAND Cell 2.2.23 Die Analysis Locations 2.2.24 Chip Assembly Analysis Locations
Overview 1-2 3 Package Analysis 3.1.1 Chip Assembly Optical Cross Section 3.1.2 Top Portion of the Fiber Holder SEM Tilt View 3.1.3 Top Portion of the Fiber Holder Optical Cross Section 3.1.4 Bottom Portion of the Fiber Holder SEM Tilt View 3.1.5 Bottom Portion of the Fiber Holder Optical Cross Section 3.1.6 Epoxy Between Fiber and PN1000001 Si Die (Optical) Left Edge 3.1.7 Epoxy Between Fiber and PN1000001 Si Die (Optical) Center 3.1.8 Epoxy Between Fiber and PN1000001 Si Die (SEM) Center 3.1.9 Epoxy Between Fiber and PN1000001 Si Die (Optical) Right Edge 3.1.10 Laser Module and PN1000001 Si Die Attach Overview 3.1.11 PN1000001 Si Die Attach in Detail 3.1.12 Laser Module Attach Overview 3.1.13 Laser Module Attach in Detail 3.1.14 Underfill Epoxy Below Half-Wave Plate Left Edge (P5S1) 3.1.15 Underfill Epoxy Below Half-Wave Plate Right Edge (P5S1) 3.1.16 Underfill Epoxy Below Half-Wave Plate Near Isolator (P5S2) 3.1.17 Underfill Epoxy Below Half-Wave Plate Middle (P5S2) 3.1.18 Underfill Epoxy Below Half-Wave Plate Near Laser Diode (P5S2) 3.2.1 Laser Module Overview 3.2.2 Laser Module Left Edge 3.2.3 Laser Module Right Edge 3.2.4 Laser Module Bond Pad 3.2.5 Si Cap Attach SEM 3.2.6 Si Cap Attach Optical 3.2.7 Si Cap Cavity Mirror Near Left Edge of Cavity 3.2.8 Si Cap Cavity Mirror Edge Near Center of Cavity 3.2.9 Details of Si Cap Cavity Mirror on Sidewalls 3.2.10 Laser Diode Overview 3.2.11 Laser Diode Left Edge 3.2.12 Laser Diode Attach in Detail Left Edge 3.2.13 Laser Diode Right Edge 3.2.14 Laser Diode in Detail Right Edge 3.2.15 Ball Lens 3.2.16 Isolator
Overview 1-3 4 PN1000001 Si CMOS Photonics Die General Process Analysis 4.1.1 General Structure of the PN1000001 4.1.2 Die Edge 4.1.3 Die Seal and Cutout 4.1.4 Die Seal 4.2.1 Bond Pad 4.2.2 Right Bond Pad Edge 4.3.1 SEM IMD 6 4.3.2 TEM Passivation and ILD 5 4.3.3 TEM ILD 4 4.3.4 TEM ILD 3 4.3.5 TEM ILD 2 4.3.6 TEM ILD 1 4.3.7 SEM PMD 4.3.8 TEM PMD 4.3.9 TEM CESL and Salicidation Mask 4.4.1 SEM Metal 7 4.4.2 SEM Minimum Pitch Metal 6 4.4.3 SEM Metal 6 Composition and Minimum Pitch Metal 5 4.4.4 SEM Minimum Pitch Metal 4 4.4.5 SEM Minimum Pitch Metal 3 4.4.6 TEM Metal 4 4.4.7 TEM Metal 3 4.4.8 SEM Minimum Pitch Metal 2 4.4.9 SEM Minimum Pitch Metal 1 4.4.10 TEM Metal 1 4.4.11 TEM Metal 1 Trench Liner 4.5.1 SEM of Via 6 4.5.2 SEM of Minimum Pitch Via 5s 4.5.3 SEM of Minimum Pitch Via 4s and Via 3s 4.5.4 SEM of Minimum Pitch Via 2s and Via 1s 4.5.5 SEM Minimum Pitch Contacts to SOI (Diffusion) 4.5.6 SEM Minimum Pitch Contacts to Poly 4.5.7 TEM Bottom of Contact to Diffusion 4.6.1 Minimum Contacted Gate Pitch 4.6.2 Minimum Gate Length Logic MOS Transistor 4.6.3 Minimum Gate Length Logic PMOS Transistor 4.6.4 Minimum Gate Length Logic NMOS Transistor 4.6.5 Logic Transistor Gate Oxide Lattice Image 4.6.6 Logic Transistor Gate Oxide Lattice Image 4.7.1 SEM Poly Resistor Overview Oxide Stain 4.7.2 SEM Poly Resistor and Contact Detail Oxide Stain 4.8.1 SEM of Poly Capacitor Si Stain 4.9.1 Overview of SOI, STI, and BOX over Si Handle 4.9.2 TEM of STI Modulator and Waveguide 4.9.3 Minimum Width STI Gratings
Overview 1-4 5 PN1000001 Si CMOS Photonics Die Optical Devices 5.1.1 Single Polarization Grating Coupler (SPGC) Optical Plan View 5.1.2 TEM SPGC Spacing First Grating At the Edge of the Horn 5.1.3 TEM SPGC Spacing Towards Array Center 1 5.1.4 TEM SPGC Spacing Towards Array Center 2 5.1.5 TEM SPGC Spacing Array Center 5.1.6 TEM SPGC Spacing Towards Grating Array Edge 1 5.1.7 TEM SPGC Spacing Towards Grating Array Edge 2 5.1.8 TEM SPGC Spacing Grating Array Edge 5.1.9 TEM SPGC in Detail Widest Grating 5.1.10 TEM SPGC in Detail Narrowest Grating 5.1.11 Overview of Light Input from Laser into TX 5.1.12 Overview of Light Output from TX to Fiber 5.1.13 Polarization Splitting Grating Coupler (PSGC) Optical Plan View 5.1.14 Polarization Splitting Grating Coupler (PSGC) SEM Plan View 5.1.15 Overview of Light Input from Fiber to RX 5.1.16 Details of Light Input from Fiber to RX 5.1.17 Waveguide Test Structure Optical Plan View 5.2.1 Waveguides Location 1 Optical Plan View 5.2.2 Waveguides Location 2 Optical Plan View 5.2.3 Narrow Waveguide TEM Cross Section 5.2.4 Narrow Waveguide SEM Si Stain Cross Section 5.2.5 Narrow Waveguide Rib TEM Cross Section 5.2.6 Left End of Narrow Waveguide TEM Cross Section 5.2.7 Right End of Narrow Waveguide TEM Cross Section 5.2.8 Wide Waveguides SEM Si Stain Cross Section 5.3.1 Overview of Optical Terminator, Directional Coupler Optical Plan View 5.3.2 Optical Terminator and Monitor Diode Optical Plan View 5.3.3 Optical Terminator Overview SEM Cross Section 5.3.4 Optical Terminator Detail SEM Cross Section 5.3.5 Directional Coupler Optical Plan View 5.3.6 Directional Coupler SEM Plan View 5.3.7 Directional Coupler Overview SEM Cross Section 5.3.8 Directional Coupler Waveguide Ribs SEM Cross Section 5.3.9 Y-Junction Splitter Optical Plan View 5.4.1 MZI Modulator Array in TX Optical Plan View 5.4.2 Connected Neighboring Stages of MZI Modulator at M3 Optical Plan-View 5.4.3 Single Stage of MZI Modulator at M3 Optical Plan-View 5.4.4 Differential Amplifier Stage to MZI Arm Connections at M3 Optical Plan View 5.4.5 Overview of Start of MZI Optical Plan View 5.4.6 Overview of Start of MZI SEM Plan View 5.4.7 MZI Segment in Detail Optical Plan View 5.4.8 MZI Segment in Detail SEM Plan View 5.4.9 End of MZI Optical Plan View 5.4.10 End of MZI SEM Plan View
Overview 1-5 5.4.11 Map of Planes of Cross Section Through MZI 5.4.12 Type 1A MZI Overview TEM (A) 5.4.13 Type 1A MZI Overview SEM Si Stain (A) 5.4.14 Type 1A MZI Overview SCM (A) 5.4.15 Type 1A MZI Overview Topography (A) 5.4.16 Type 1A MZI Rib SEM (A) 5.4.17 Type 1A MZI Rib TEM (A) 5.4.18 Type 1A MZI Rib SCM (A) 5.4.19 Type 1A MZI P-Type Region SEM (A) 5.4.20 Type 1A MZI P-Type Region TEM (A) 5.4.21 Type 1A MZI N-Type Region SEM (A) 5.4.22 Type 1A MZI P-Type Region TEM (A) 5.4.23 Type 1B MZI Overview SEM (B) 5.4.24 Type 1B MZI Rib TEM (B) 5.4.25 Type 2 MZI Overview SEM (C) 5.4.26 Type 2 MZI Rib SEM (C) 5.5.1 Overview of the Receiver Front End at M1 Optical Plan View 5.5.2 Overview of Part of the Receiver Front End at M3 Optical Plan View 5.5.3 Ge Detector at M3 Optical Plan View 5.5.4 Ge Detector at M2 Optical Plan View 5.5.5 Ge Detector at Poly SEM Plan View 5.5.6 Details of Ge Detector at Poly SEM Plan View 5.5.7 SEM Overview of Ge Detector Width Direction 5.5.8 TEM Overview of Ge Detector Width Direction 5.5.9 Detailed SEM of Ge Detector Width Direction 5.5.10 Detailed TEM of Ge Detector Width Direction 5.5.11 SEM of Ge Detector Edge Width Direction 5.5.12 TEM of Ge Detector Edge Width Direction 5.5.13 Detailed TEM of Ge Detector Edge Width Direction 5.5.14 Detailed TEM of Ge Detector Edge Length Direction 5.5.15 Overview of Ge Detector on SOI TEM 5.5.16 Lattice Image of Ge Detector Interface with SOI HRTEM 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Device Summary 1.6.1 Process Summary 2 Device Overview 2.2.1 Die and Bond Pad Sizes 3 Package Analysis 3.1.1 Si CMOS Photonic Chip Assembly Sizes 3.2.1 Laser Module Sizes
Overview 1-6 4 PN1000001 Si CMOS Photonics Die General Process Analysis 4.3.1 Dielectric Thicknesses 4.4.1 Metallization Vertical Dimensions 4.4.2 Metallization Horizontal Dimensions 4.5.1 Via and Contact Dimensions 4.6.1 Transistor Horizontal Dimensions 4.6.2 Transistor and Silicide Vertical Dimensions 4.9.1 SOI, STI, BOX, FOX Measured Dimensions 5 PN1000001 Si CMOS Photonics Die Optical Devices 5.1.1 SPGC and PSGC Dimensions 5.2.1 Waveguide Dimensions 5.3.1 Optical Terminator, Directional Coupler, and Splitter Dimensions 5.4.1 Mach-Zehnder Interferometer Modulator Dimensions 5.5.1 Ge Photodetector Dimensions 6 Critical Dimensions 6.1.1 Die and Bond Pad Horizontal Dimensions 6.1.2 Si CMOS Photonic Chip Assembly Horizontal Dimensions 6.1.3 Laser Module Horizontal Dimensions 6.1.4 Metallization Horizontal Dimensions 6.1.5 Via and Contact Dimensions 6.1.6 Transistor Horizontal Dimensions 6.1.7 STI Measured Horizontal Dimensions 6.1.8 SPGC and PSGC Horizontal Dimensions 6.1.9 Waveguide Horizontal Dimensions 6.1.10 Optical Terminator, Directional Coupler, and Splitter Dimensions 6.1.11 Mach-Zehnder Interferometer Modulator Horizontal Dimensions 6.1.12 Ge Photodetector Horizontal Dimensions 6.2.1 Die and Bond Pad Vertical Dimensions 6.2.2 Si CMOS Photonic Chip Assembly Vertical Dimensions 6.2.3 Laser Module Vertical Dimensions 6.2.4 Dielectric Thicknesses 6.2.5 Metallization Vertical Dimensions 6.2.6 Via and Contact Vertical Dimensions 6.2.7 Transistor and Silicide Vertical Dimensions 6.2.8 STI Measured Vertical Dimensions 6.2.9 Waveguide Horizontal Dimensions 6.2.10 Mach-Zehnder Interferometer Modulator Vertical Dimensions 6.2.11 Ge Photodetector Vertical Dimensions
About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at 1-613-829-0414. Chipworks 1891 Robertson Road, Suite 500 Ottawa, Ontario K2H 5B7 Canada T 1-613-829-0414 F 1-613-829-0515 Web site: www.chipworks.com Email: info@chipworks.com Please send any feedback to feedback@chipworks.com