COMPUTER ORGANIZATION AND DESIGN

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 4 The Processor

Introduction CPU performance factors Instruction count Determined by ISA and compiler CPI and Cycle time Determined by CPU hardware We will examine two MIPS implementations A simplified version A more realistic pipelined version Simple subset, shows most aspects Memory reference: lw, sw Arithmetic/logical: add, sub, and, or, slt Control transfer: beq, j 4.1 Introduction Chapter 4 The Processor 2

Instruction Execution PC instruction memory, fetch instruction Register numbers register file, read registers Depending on instruction class Use ALU to calculate Arithmetic result Memory address for load/store Branch target address Access data memory for load/store PC target address or PC + 4 Chapter 4 The Processor 3

CPU Overview Chapter 4 The Processor 4

Multiplexers Can t just join wires together Use multiplexers Chapter 4 The Processor 5

Control Chapter 4 The Processor 6

Logic Design Basics Information encoded in binary Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses Combinational element Operate on data Output is a function of input State (sequential) elements Store information 4.2 Logic Design Conventions Chapter 4 The Processor 7

Combinational Elements AND-gate Y = A & B Adder Y = A + B A B + Y A B I0 I1 M u x S Y Multiplexer Y = S? I1 : I0 Y Arithmetic/Logic Unit Y = F(A, B) A ALU Y B F Chapter 4 The Processor 8

Sequential Elements Register: stores data in a circuit Uses a clock signal to determine when to update the stored value Edge-triggered: update when Clk changes from 0 to 1 D Clk Q Clk D Q Chapter 4 The Processor 9

Sequential Elements Register with write control Only updates on clock edge when write control input is 1 Used when stored value is required later Clk D Write Clk Q Write D Q Chapter 4 The Processor 10

Clocking Methodology Combinational logic transforms data during clock cycles Between clock edges Input from state elements, output to state element Longest delay determines clock period Chapter 4 The Processor 11

Building a Datapath Datapath Elements that process data and addresses in the CPU Registers, ALUs, mux s, memories, We will build a MIPS datapath incrementally Refining the overview design 4.3 Building a Datapath Chapter 4 The Processor 12

Instruction Fetch 32-bit register Increment by 4 for next instruction Chapter 4 The Processor 13

R-Format Instructions Read two register operands Perform arithmetic/logical operation Write register result Chapter 4 The Processor 14

Load/Store Instructions Read register operands Calculate address using 16-bit offset Use ALU, but sign-extend offset Load: Read memory and update register Store: Write register value to memory Chapter 4 The Processor 15

Branch Instructions Read register operands Compare operands Use ALU, subtract and check Zero output Calculate target address Sign-extend displacement Shift left 2 places (word displacement) Add to PC + 4 Already calculated by instruction fetch Chapter 4 The Processor 16

Branch Instructions Just re-routes wires Sign-bit wire replicated Chapter 4 The Processor 17

Composing the Elements First-cut data path does an instruction in one clock cycle Each datapath element can only do one function at a time Hence, we need separate instruction and data memories Use multiplexers where alternate data sources are used for different instructions Chapter 4 The Processor 18

R-Type/Load/Store Datapath Chapter 4 The Processor 19

Full Datapath Chapter 4 The Processor 20

ALU Control ALU used for Load/Store: F = add Branch: F = subtract R-type: F depends on funct field ALU control Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 set-on-less-than 1100 NOR 4.4 A Simple Implementation Scheme Chapter 4 The Processor 21

ALU Control Assume 2-bit ALUOp derived from opcode Combinational logic derives ALU control opcode ALUOp Operation funct ALU function ALU control lw 00 load word XXXXXX add 0010 sw 00 store word XXXXXX add 0010 beq 01 branch equal XXXXXX subtract 0110 R-type 10 add 100000 add 0010 subtract 100010 subtract 0110 AND 100100 AND 0000 OR 100101 OR 0001 set-on-less-than 101010 set-on-less-than 0111 Chapter 4 The Processor 22

The Main Control Unit Control signals derived from instruction R-type Load/ Store Branch 0 rs rt rd shamt funct 31:26 25:21 20:16 15:11 10:6 5:0 35 or 43 rs rt address 31:26 25:21 20:16 15:0 4 rs rt address 31:26 25:21 20:16 15:0 opcode always read read, except for load write for R-type and load sign-extend and add Chapter 4 The Processor 23

Datapath With Control Chapter 4 The Processor 24

R-Type Instruction Chapter 4 The Processor 25

Load Instruction Chapter 4 The Processor 26

Branch-on-Equal Instruction Chapter 4 The Processor 27

Implementing Jumps Jump 2 address Jump uses word address Update PC with concatenation of Top 4 bits of old PC 26-bit jump address 00 31:26 25:0 Need an extra control signal decoded from opcode Chapter 4 The Processor 28

Datapath With Jumps Added Chapter 4 The Processor 29

Performance Issues Longest delay determines clock period Critical path: load instruction Instruction memory register file ALU data memory register file Not feasible to vary period for different instructions Violates design principle Making the common case fast We will improve performance by pipelining Chapter 4 The Processor 30

Pipelining Analogy Pipelined laundry: overlapping execution Parallelism improves performance Four loads: Speedup = 8/3.5 = 2.3 Non-stop: 4.5 An Overview of Pipelining Speedup = 2n/(0.5n + 1.5) n 4 = number of stages Chapter 4 The Processor 31

MIPS Pipeline Five stages, one step per stage 1. IF: Instruction fetch from memory 2. ID: Instruction decode & register read 3. EX: Execute operation or calculate address 4. MEM: Access memory operand 5. WB: Write result back to register Chapter 4 The Processor 32

Pipeline Performance Assume time for stages is 100ps for register read or write 200ps for other stages Compare pipelined datapath with single-cycle datapath Instr Instr fetch Register read ALU op Memory access Register write Total time lw 200ps 100 ps 200ps 200ps 100 ps 800ps sw 200ps 100 ps 200ps 200ps 700ps R-format 200ps 100 ps 200ps 100 ps 600ps beq 200ps 100 ps 200ps 500ps Chapter 4 The Processor 33

Pipeline Performance Single-cycle (T c = 800ps) Pipelined (T c = 200ps) Chapter 4 The Processor 34

Pipeline Speedup If all stages are balanced i.e., all take the same time Time between instructions pppppppppppppppppp = Time between instructions nnnnnnnnnnnnnnnnnnnnnnnn Number of stages If not balanced, speedup is less Speedup due to increased throughput Latency (time for each instruction) does not decrease Chapter 4 The Processor 35

Pipelining and ISA Design MIPS ISA designed for pipelining All instructions are 32-bits Easier to fetch and decode in one cycle c.f. x86: 1- to 17-byte instructions Few and regular instruction formats Can decode and read registers in one step Load/store addressing Can calculate address in 3 rd stage, access memory in 4 th stage Alignment of memory operands Memory access takes only one cycle Chapter 4 The Processor 36

Hazards Situations that prevent starting the next instruction in the next cycle Structure hazards A required resource is busy Data hazard Need to wait for previous instruction to complete its data read/write Control hazard Deciding on control action depends on previous instruction Chapter 4 The Processor 37

Structure Hazards Conflict for use of a resource In MIPS pipeline with a single memory Load/store requires data access Instruction fetch would have to stall for that cycle Would cause a pipeline bubble Hence, pipelined datapaths require separate instruction/data memories Or separate instruction/data caches Chapter 4 The Processor 38

Data Hazards An instruction depends on completion of data access by a previous instruction add $s0, $t0, $t1 sub $t2, $s0, $t3 Chapter 4 The Processor 39

Forwarding (aka Bypassing) Use result when it is computed Don t wait for it to be stored in a register Requires extra connections in the datapath Chapter 4 The Processor 40

Load-Use Data Hazard Can t always avoid stalls by forwarding If value not computed when needed Can t forward backward in time! Chapter 4 The Processor 42

Code Scheduling to Avoid Stalls Reorder code to avoid use of load result in the next instruction C code for A = B + E; C = B + F; stall stall lw $t1, 0($t0) lw $t2, 4($t0) add $t3, $t1, $t2 sw $t3, 12($t0) lw $t4, 8($t0) add $t5, $t1, $t4 sw $t5, 16($t0) 13 cycles Chapter 4 The Processor 43

Control Hazards Branch determines flow of control Fetching next instruction depends on branch outcome Pipeline can t always fetch correct instruction Still working on ID stage of branch In MIPS pipeline Need to compare registers and compute target early in the pipeline Add hardware to do it in ID stage Chapter 4 The Processor 45

Stall on Branch Wait until branch outcome determined before fetching next instruction Example (branch taken) ID stage performs comparison Chapter 4 The Processor 46

Branch Prediction Longer pipelines can t readily determine branch outcome early Stall penalty becomes unacceptable Predict outcome of branch Only stall if prediction is wrong In MIPS pipeline Can predict branches not taken Fetch instruction after branch, with no delay Chapter 4 The Processor 47

MIPS with Predict Not Taken Prediction correct Prediction incorrect Chapter 4 The Processor 48

More-Realistic Branch Prediction Static branch prediction Based on typical branch behavior Example: loop and if-statement branches Predict backward branches taken Predict forward branches not taken Dynamic branch prediction Hardware measures actual branch behavior e.g., record recent history of each branch Assume future behavior will continue the trend When wrong, stall while re-fetching, and update history Chapter 4 The Processor 49

Pipeline Summary The BIG Picture Pipelining improves performance by increasing instruction throughput Executes multiple instructions in parallel Each instruction has the same latency Subject to hazards Structure, data, control Instruction set design affects complexity of pipeline implementation Chapter 4 The Processor 50

MIPS Pipelined Datapath 4.6 Pipelined Datapath and Control MEM Right-to-left flow leads to hazards WB Chapter 4 The Processor 52

Pipeline registers Need registers between stages To hold information produced in previous cycle Chapter 4 The Processor 53

Pipeline Operation Cycle-by-cycle flow of instructions through the pipelined datapath Single-clock-cycle pipeline diagram Shows pipeline usage in a single cycle Highlight resources used c.f. multi-clock-cycle pipeline diagram Graph of operation over time We ll look at single-clock-cycle diagrams for load & store Chapter 4 The Processor 54

IF for Load, Store, Instruction is read from memory using the address in PC and is placed in the IF/ID pipeline register PC address is incremented by 4 and then written back into PC to be ready for the next clock cycle This incremented address is also saved in IF/ID pipeline register in case it is needed later for an instruction Chapter 4 The Processor 55

ID for Load, Store, Instruction portion of IF/ID pipeline register supplying 16-bit immediate field, which is sign-extended to 32 bits, and the register numbers to read the two registers All three values are stored in the ID/EX pipeline register, along with incremented PC address Everything might be needed by any instruction during a later clock cycle is transferred Chapter 4 The Processor 56

EX for Load Load instruction reads Register 1 and Sign-extended immediate from the ID/EX pipeline register ALU adds them Sum is placed in the EX/MEM pipeline register Chapter 4 The Processor 57

MEM for Load Load instruction reads data memory using address from EX/MEM pipeline register Writes data into MEM/WB pipeline register Chapter 4 The Processor 58

WB for Load Reading data from MEM/WB pipeline register and writing it into register file Chapter 4 The Processor 59

WB for Load Reading data from MEM/WB pipeline register and writing it into register file Load must pass destination register number from ID/EX through EX/MEM to MEM/WB pipeline register for use in WB stage Wrong register number Chapter 4 The Processor 60

Corrected Datapath for Load Load must pass destination register number from ID/EX through EX/MEM to MEM/WB pipeline register for use in WB stage Chapter 4 The Processor 61

EX for Store Chapter 4 The Processor 62

MEM for Store Chapter 4 The Processor 63

WB for Store Chapter 4 The Processor 64

Multi-Cycle Pipeline Diagram Form showing resource usage Chapter 4 The Processor 65

Multi-Cycle Pipeline Diagram Traditional form Chapter 4 The Processor 66

Single-Cycle Pipeline Diagram State of pipeline in a given cycle Chapter 4 The Processor 67

Pipelined Control (Simplified) Chapter 4 The Processor 68

Pipelined Control Control signals are derived from instruction As in single-cycle implementation Use a Main Control unit to generate signals during ID Stage Control signals for EX (ExtOp, ALUSrc, ) used 1 cycle later Control signals for Mem (MemWr, Branch) used 2 cycles later Control signals for WB (MemtoReg, MemWr) used 3 cycles later Chapter 4 The Processor 69

Assumptions for pipelining control signals Initial design motivated by single-cycle datapath control uses the same control signals Observe: No separate write signal for the PC as it is written every cycle No separate write signals for the pipeline registers (IF/ID, ID/EX, EX/MEM, MEM/WB), as they are written every cycle No separate read signal for instruction memory as it is read every clock cycle No separate read signal for register file as it is read every clock cycle Need to set control signals during each pipeline stage Since control signals are associated with components active during a single pipeline stage, can group control lines into five groups according to pipeline stage Will be modified by hazard detection unit!!

Implementing Pipeline Control RF/ID EX MEM WB RegDst RegDst IF/ID Register Main Control ALUSrc ALUOp RegDst MemWr Branch MemtoReg ID/Ex Register ALUSrc ALUOp MemRead MemWr Branch MemtoReg Ex/MEM Register MemRead MemWr Branch MemtoReg MEM/WB Register MemtoReg RegWr RegWr RegWr RegWr

Pipelined Control Chapter 4 The Processor 72

Pipelined Control Chapter 4 The Processor 73

Data Hazards in ALU Instructions Consider this sequence: sub $2, $1,$3 and $12,$2,$5 or $13,$6,$2 add $14,$2,$2 sw $15,100($2) We need 1. Detect the hazard 2. Resolve the hazard Stall Forwarding Mix 4.7 Data Hazards: Forwarding vs. Stalling We can resolve hazards with forwarding How do we detect when to forward? Chapter 4 The Processor 74

Dependencies & Forwarding Chapter 4 The Processor 75

Software Solution Have compiler guarantee never any data hazards! by rearranging instructions to insert independent instructions between instructions that would otherwise have a data hazard between them, or, if such rearrangement is not possible, insert nops sub $2, $1, $3 lw $10, 40($3) slt $5, $6, $7 and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) or sub $2, $1, $3 nop nop and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) Such compiler solutions may not always be possible, and nops slow the machine down MIPS: nop = no operation = 00 0 (32bits) = sll $0, $0, 0

Detecting the Need to Forward Forwarding to EX stage is studied Pass register numbers along pipeline e.g., ID/EX.RegisterRs = register number for Rs sitting in ID/EX pipeline register ALU operand register numbers in EX stage are given by ID/EX.RegisterRs, ID/EX.RegisterRt Data hazards when 1a. EX/MEM.RegisterRd = ID/EX.RegisterRs 1b. EX/MEM.RegisterRd = ID/EX.RegisterRt 2a. MEM/WB.RegisterRd = ID/EX.RegisterRs 2b. MEM/WB.RegisterRd = ID/EX.RegisterRt Fwd from EX/MEM pipeline reg Fwd from MEM/WB pipeline reg Chapter 4 The Processor 77

Detecting the Need to Forward First hazard between sub $2, $1, $3 and and $12, $2, $5 is detected when and is in EX and sub is in MEM because EX/MEM.RegisterRd = ID/EX.RegisterRs = $2 (1a) Similar to above this time dependency between sub and or can be detected as MEM/WB.RegisterRd = ID/EX.RegisterRt = $2 (2b) Two dependencies between sub and add are not hazard Another form of forwarding but it occurs within reg file There is no hazard between sub and sw Chapter 4 The Processor 78

Detecting the Need to Forward But only if forwarding instruction will write to a register! EX/MEM.RegWrite, MEM/WB.RegWrite And only if Rd for that instruction is not $zero EX/MEM.RegisterRd 0, MEM/WB.RegisterRd 0 Chapter 4 The Processor 79

Forwarding Paths Chapter 4 The Processor 80

Forwarding Conditions EX hazard if (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10 MEM hazard if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 Chapter 4 The Processor 81

Forwarding Paths One more 2:1 mux to select signed immediate as ALU input Chapter 4 The Processor 83

Double Data Hazard Consider the sequence: add $1,$1,$2 add $1,$1,$3 add $1,$1,$4 ALU IM Reg DM Reg ALU IM Reg DM Reg Reg $1 is written by both previous instructions (both hazards occur) But only the most recent result (from the second ADD) should be forwarded ALU IM Reg DM Reg Revise MEM hazard condition Only forward if EX hazard condition isn t true Chapter 4 The Processor 84

Revised Forwarding Condition MEM hazard if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) Not forwarding from EX/MEM and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd 0) and not (EX/MEM.RegWrite and (EX/MEM.RegisterRd 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 Chapter 4 The Processor 86

Datapath with Forwarding EX/MEM.RegWrite MEM/WB.RegWrite Chapter 4 The Processor 87

Datapath with Forwarding Called forwarding unit, not hazard detection unit, because once data is forwarded there is no hazard! EX/MEM.RegWrite MEM/WB.RegWrite Chapter 4 The Processor 88

Load-Use Data Hazard Forwarding is not the solution for all data hazard conditions Example: an instruction tries to read a register following a lw, that writes the same register Problem will occur lw $2, 20($1) and $4, $2, $5 or $8, $2, $6 add $9, $4, $2 slt $1, $6, $7 In addition to forwarding unit, we need hazard detection unit (HDU) to work during ID stage HDU will insert stall between the load and its use

Load-Use Data Hazard Need to stall for one cycle Chapter 4 The Processor 90

Load-Use Hazard Detection Unit Check when using instruction is decoded in ID stage ALU operand register numbers in ID stage are given by IF/ID.RegisterRs, IF/ID.RegisterRt Load-use hazard is detected when ID/EX.MemRead and ((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt)) If detected, stall and insert bubble Chapter 4 The Processor 91

How to Stall the Pipeline Force control values in ID/EX register to 0 EX, MEM and WB do nop (no-operation) Prevent update of PC and IF/ID register Using (current) instruction is decoded again Following instruction is fetched again 1-cycle stall allows MEM to read data for lw Can subsequently forward to EX stage

Stall/Bubble in the Pipeline Stall inserted here AND instruction is turned into NOP All instructions beginning with AND instruction are delayed one cycle Prevent update of PC and IF/ID register Hazard forces the AND and OR instructions to repeat in clock cycle 4, what they did in clock cycle 3 (AND reads regs and is decoded again OR is fetched again) Chapter 4 The Processor 93

Stall/Bubble in the Pipeline Or, more accurately Chapter 4 The Processor 94

Stall Hardware As a part of Hazard Unit, we have to implement Stall Hardware Prevent the instructions in the IF and ID stages from progressing down the pipeline Preventing PC and IF/ID pipeline register from changing Hazard Unit controls the writing of the PC (PC.write) and IF/ID (IF/ID.write) registers Insert a bubble between the lw instruction (in the EX stage) and the load-use instruction (in the ID stage) (i.e., insert a nop in the execution stream) Set the control bits in the EX, MEM, and WB control fields of the ID/EX pipeline register to 0 (nop). Hazard Unit controls the mux that chooses between the real control values and the 0 s Let the lw instruction and the instructions after it in the pipeline (before it in the code) proceed normally down the pipeline

Mechanics of Stalling What Stall Hardware does to stall the pipeline 1 cycle: Does not let IF/ID register change (disable write!) Instruction in ID stage repeats, (i.e., Stall) The instruction, just behind (in IF stage) must be stalled as well Hardware does not let PC change (disable write!) Instruction in IF stage repeats (i.e., Stall) Changes all the EX, MEM and WB control fields in ID/EX pipeline register to 0, Instruction just behind lw becomes a nop (a bubble is said to have been inserted into the pipeline) We cannot turn that instruction into nop by turning all bits in the instruction itself to 0 because it has already been decoded and control signals generated Recall nop = 00 0 (32 bits)

Datapath with Hazard Detection IF/ID.RegisterRs IF/ID.RegisterRt Chapter 4 The Processor 97

Stalling Execution example: lw $2, 20($1) and $4, $2, $5 or $4, $4, $2 add $9, $4, $2

Stalling Execution example: lw $2, 20($1) and $4, $2, $5 or $4, $4, $2 add $9, $4, $2 ID/EX.MemRead and ((ID/EX.RegisterRt = IF/ID.RegisterRs) or (ID/EX.RegisterRt = IF/ID.RegisterRt))

Stalling Execution example: lw $2, 20($1) and $4, $2, $5 or $4, $4, $2 add $9, $4, $2

Stalls and Performance The BIG Picture Stalls reduce performance But are required to get correct results Compiler can arrange code to avoid hazards and stalls Requires knowledge of the pipeline structure Chapter 4 The Processor 104

Control Hazards When the flow of instruction addresses is not sequential (i.e., PC = PC + 4); incurred by change of flow instructions Conditional branches (beq, bne) Unconditional branches (j, jal, jr) Exceptions Possible hardware approaches Stall (impacts CPI) Move decision point as early in the pipeline as possible, thereby reducing the number of stall cycles Predict and hope for the best! Possible software approaches Delay decision (requires compiler support) 107

Branch Hazards If branch outcome determined in MEM 1 st solution is to insert 3 stalls 4.8 Control Hazards Flush these instructions (Set control values to 0) PC Chapter 4 The Processor 109

How to Fix Control Hazard 2 nd solution is to put extra hardware in ID stage to Test (compare) registers Calculate branch (target) address, and Update PC That reduces the number of stalls to only 1 3 rd solution is to predict branch outcome For example: always predict branches are not taken When right, pipeline proceeds at full speed (no stall) When wrong, insert 1 stall Make sure nothing completes

Reducing Branch Delay Move hardware to determine outcome to ID stage Target address adder Register comparator Bitwise XOR registers and then NOR all results rather than using a subtractor and then test for zero Example: branch taken 36: sub $10, $4, $8 40: beq $1, $3, 7 44: and $12, $2, $5 48: or $13, $2, $6 52: add $14, $4, $2 56: slt $15, $6, $7... 72: lw $4, 50($7) Branch taken Chapter 4 The Processor 111

Example: Branch Taken 36: sub $10, $4, $8 40: beq $1, $3, 7 44: and $12, $2, $5 48: or $13, $2, $6 52: add $14, $4, $2 56: slt $15, $6, $7... 72: lw $4, 50($7) In Clock 3, stage ID detect beq and selects the top input of the mux feeding PC In Clock 3, stage ID stage sets control signal IF.Flush=1 Chapter 4 The Processor 112

Example: Branch Taken 36: sub $10, $4, $8 40: beq $1, $3, 7 44: and $12, $2, $5 48: or $13, $2, $6 52: add $14, $4, $2 56: slt $15, $6, $7... 72: lw $4, 50($7) In Clock 4, lw (from address 72) is fetched because in Clock 3, stage ID selected the top input of the mux feeding PC In Clock 4, a single bubble acting as a nop instruction (sll $0, $0, 0) is inserted into ID stage because control signal IF.Flush was set 1 in Clock 3 Chapter 4 The Processor 113

Data Hazards for Branches If a comparison register is a destination of 2 nd or 3 rd preceding ALU instruction add $1, $2, $3 IF ID EX MEM WB add $4, $5, $6 IF ID EX MEM WB IF ID EX MEM WB beq $1, $4, target IF ID EX MEM WB Can resolve using forwarding Chapter 4 The Processor 114

Data Hazards for Branches If a comparison register is a destination of preceding ALU instruction or 2 nd preceding load instruction Need 1 stall cycle lw $1, addr IF ID EX MEM WB add $4, $5, $6 IF ID EX MEM WB beq stalled IF ID beq $1, $4, target ID EX MEM WB Chapter 4 The Processor 115

Data Hazards for Branches If a comparison register is a destination of immediately preceding load instruction Need 2 stall cycles lw $1, addr IF ID EX MEM WB beq stalled IF ID beq stalled ID beq $1, $0, target ID EX MEM WB Chapter 4 The Processor 116

Branch Hazard - Prediction Assume branch is not taken If so, pipeline proceeds at full speed Fetch the next instruction in program order When the branch is resolved: If the branch is not taken, keep going, no problem If the branch is taken, we need to flush 3 instructions in the pipeline We use nop s to discard instructions in the IF, ID, EX stage. In the case of branches, we need to flush the instructions from the pipeline, so that they don't have any effect

Branch Hazard - Prediction branch is not taken branch is taken

Dynamic Branch Prediction In deeper and superscalar pipelines, branch penalty is more significant Use dynamic prediction Branch prediction buffer (aka branch history table) Indexed by recent branch instruction addresses Stores outcome (taken/not taken) To execute a branch Check table, expect the same outcome Start fetching from fall-through or target If wrong, flush pipeline and flip prediction Chapter 4 The Processor 119

Dynamic Branch Prediction A branch prediction buffer (aka branch history table or BHT) in the IF stage addressed by the lower bits of the PC, contains a bit passed to the ID stage through the IF/ID pipeline register that tells whether the branch was taken the last time it was execute Prediction bit may predict incorrectly (may be a wrong prediction for this branch this iteration or may be from a different branch with the same low order PC bits) but the doesn t affect correctness, just performance Branch decision occurs in the ID stage after determining that the fetched instruction is a branch and checking the prediction bit

1-Bit Prediction Accuracy A 1-bit predictor will be incorrect twice when not taken Assume predict_bit = 0 to start (indicating branch not taken) and loop control is at the bottom of the loop code 1. First time through the loop, the predictor mispredicts the branch since the branch is taken back to the top of the loop; invert prediction bit (predict_bit = 1) 2. As long as branch is taken (looping), prediction is correct 3. Exiting the loop, the predictor again mispredicts the branch since this time the branch is not taken falling out of the loop; invert prediction bit (predict_bit = 0) Loop: 1 st loop instr 2 nd loop instr... last loop instr bne $1,$2,Loop fall out instr 123

1-Bit Prediction Accuracy A 1-bit predictor will be incorrect twice when not taken Assume predict_bit = 0 to start (indicating branch not taken) and loop control is at the bottom of the loop code 1. First time through the loop, the predictor mispredicts the branch since the branch is taken back to the top of the loop; invert prediction bit (predict_bit = 1) 2. As long as branch is taken (looping), prediction is correct Loop: 1 st loop instr 2 nd loop instr... last loop instr bne $1,$2,Loop fall out instr 3. Exiting the loop, the predictor again mispredicts the branch since this time the branch is not taken falling out of the loop; invert prediction bit (predict_bit = 0) For 10 times through the loop we have a 80% prediction accuracy for a branch that is taken 90% of the time 124

2-Bit Predictor Only change prediction on two successive mispredictions Gives 90% accuracy since a prediction must be wrong twice before the prediction bit is changed Chapter 4 The Processor 126

2-Bit Predictor A 2-bit scheme can give 90% accuracy since a prediction must be wrong twice before the prediction bit is changed 1 T Predict Taken NT T Predict Taken 1 Loop: 1 st loop instr 2 nd loop instr... last loop instr bne $1,$2,Loop fall out instr T NT Predict Not Taken 0 NT T NT 0 Predict Not Taken

2-Bit Predictor A 2-bit scheme can give 90% accuracy since a prediction must be wrong twice before the prediction bit is changed 1 T Predict Taken Predict Not Taken 0 NT NT T right on 1 st iteration T NT Predict Taken T 1 NT 0 Predict Not Taken Loop: 1 st loop instr 2 nd loop instr... last loop instr bne $1,$2,Loop fall out instr

2-Bit Predictor A 2-bit scheme can give 90% accuracy since a prediction must be wrong twice before the prediction bit is changed right 9 times 1 T Predict Taken Predict Not Taken 0 NT NT T right on 1 st iteration T NT Predict Taken T 1 NT 0 Predict Not Taken Loop: 1 st loop instr 2 nd loop instr... last loop instr bne $1,$2,Loop fall out instr

2-Bit Predictor A 2-bit scheme can give 90% accuracy since a prediction must be wrong twice before the prediction bit is changed right 9 times 1 T Predict Taken Predict Not Taken 0 NT wrong on loop fall out NT T right on 1 st iteration T NT Predict Taken T 1 NT 0 Predict Not Taken Loop: 1 st loop instr 2 nd loop instr... last loop instr bne $1,$2,Loop fall out instr

Calculating the Branch Target If we predict the branch as taken, and suppose that is correct, what is the target address? Even with predictor, still need to calculate target address 1-cycle penalty for a taken branch Branch target buffer (BTB) Cache of target addresses The "value" in the cache is the address of the next instruction not the contents of the memory location Indexed by PC when instruction fetched If hit, and instruction is a branch that is predicted taken, MIPS can fetch target immediately from Inst. Memory Chapter 4 The Processor 132

Branch Target Buffer BTB is a cache that contains the predicted PC value for taken branches Is the current instruction a taken branch? BTB can provide the answer before current instruction is decoded and therefore enables fetching to begin after IF-stage What is the branch target? We need to know which address to fetch from ASAP, if we want to reduce stalls even further, ideally to 0 We must do this even before CPU knows the inst. is a branch BTB provides branch target for taken branches For not taken branches the target is simply PC+4 Chapter 4 The Processor 133

Branch Target Buffer Branch PC Predicted PC PC of instruction FETCH =? No: branch not predicted, proceed normally (Next PC = PC+4) Yes: instruction is branch and use predicted PC as next PC Chapter 4 The Processor 134

BTB Basic Operation IF stage sends PC to BTB BTB compares this value with the addresses (tags) in its cache If they match (hit), this means we must have executed the branch before Also we predict that the branch will do the same as the last time (taken) The associated value (target address) is sent from BTB to PC There is a chance that the address is not in BTB (miss) MIPS never executed that branch before (compulsory miss) MIPS did execute the branch before, but it was too long ago and it has been replaced by another branch in the BTB (capacity miss or conflict miss) It is not a branch instruction at all In either case, the branch cannot be predicted and the next value of PC will be PC+4 In ID stage, branch target is calculated anyway It is compared with the predicted PC If the prediction is correct, then there will be no stall If the prediction is wrong (or if the target address was not predicted because of BTB miss), one stall is inserted into the pipeline, PC is updated with correct value and BTB is updated accordingly Chapter 4 The Processor 135

BTB Basic Operation So there are 3 different situations: The branch is not in BTB Update PC with PC+4. When branch gets to ID stage, Stall pipeline if it is a taken branch instruction Calculate target address Update BTB Do not stall pipeline if it is not a taken branch or is a non-branch instruction The branch is in BTB and prediction is correct Update PC with target address When branch gets to ID stage, no action is taken (no stall) The branch is in BTB, but prediction (taken) is wrong Stall pipeline (kill target instruction already fetched) Update PC with PC + 4 Update BTB Chapter 4 The Processor 136

Branch Target Buffer Chapter 4 The Processor 137

Branch Delay Slot If no hardware branch predictor is used, MIPS compiler needs to stall pipeline for 1 cycle after every conditional branch using a nop instruction This nop instruction is always executed no matter the branch is taken or not Compiler may find a useful instruction instead of nop to fill the branch delay slot If it couldn t, nop still is the solution Chapter 4 The Processor 141

Branch Delay Slot branch instruction branch delay slot branch target (next instruction) (if branch taken) To make this approach effective, compiler needs to fill the branch delay slot by selecting an independent instruction from before the branch If no independent instruction is found compiler fills delay slot with a nop Disadvantages Branch delay can increase to multiple cycles in deeper pipelines and superscalar pipelines It is hard to find useful instructions to fill the slots Chapter 4 The Processor 142

Branch Delay Slot Chapter 4 The Processor 143