Switch Costructio CS 00 Workstatio-Based Aggregate badwidth /2 of the I/O bus badwidth capacity shared amog all hosts coected to switch example: Gbps bus ca support 5 x 00Mbps ports (i theory) I/O bus Packets-per-secod CP must be able to switch small packets 00,000 packets-persecod is achievable Mai memory Iterface Iterface 2 Iterface CS 00 2
Switchig Hardware esig Goals Throughput (depeds o traffic model) Scalability (a fuctio of ) Iput Port Cotrol processor Iput Port Iput Port Iput Port Switch Fabric Iput Port Ports Circuit maagemet (e.g., map VCIs, switch datagrams) bufferig (iput ad/or output) Fabric As simple as possible Sometimes do bufferig (iteral) Iput Port CS 00 Bufferig Wherever cotetio is possible Iput port (coted for fabric) Iteral (coted for output port) Output port (coted for lik) Head-of-Lie Blockig Iput bufferig 2 2 Switch Port Port 2 CS 00
Switch esig Crossbar switches Baya Networks Batcher Networks Sushie Switch CS 00 5 Crossbar Switch Every iput port is coected to every output port NxN Output ports Complexity scales as O(N 2 ) CS 00
Crossbar Switch CS 00 7 Kockout Switch Assumptio: It is ulikely that N iputs will have packets destied for the same output port Pick L from N packets at a port Output port maitais L cyclic buffers Shifter places up to L packets i oe cycle Each buffer gets oly oe packet Output port uses roud-robi betwee buffers Arrival order is maitaied Problem Hot spots Output ports scale as O(N) CS 00 8
Kockout Switch Output port desig Packet filters Recogize packets destied for a specific port Cocetrator Selects up to L packets from those destied for this port iscards excess packets Queue Legth L CS 00 9 Kockout Switch 2 R R R 2 R Choose L of N Ex: 2 of R 2x2 radom selector Choice R Choice 2 2 iscard What happes if more tha L arrive? iscard elay uit CS 00 0
Self-Routig Fabrics Idea se source routig o etwork i switch Iput port attaches output port umber as header Fabric routes packet based o output port Types Baya Network Batcher-Baya Network Sushie Switch CS 00 Baya Network A etwork of 2x2 switches Each elemet routes to output 0 or based o packet header A switch at stage i looks at bit i i the header 0000 0 CS 00 2
Baya Network 00 0 00 00 00 00 0 0 0 0 0 0 0 0 0 CS 00 Baya Network Perfect Shuffle N iputs requires log 2 N stages of N/2 switchig elemets Complexity o order of N log 2 N Collisios If two packets arrive at the same switch destied for the same output port, a collisio will occur If all packets are sorted i ascedig order upo arrival to a baya etwork, o collisios will occur! CS 00
Batcher Network Performs merge sort A etwork of 2x2 switches Each elemet routes to output 0 or based o packet header A switch at stage i looks at the whole header Two types of switches p switch Seds higher umber to top output (0) ow switch Seds higher umber to bottom output () CS 00 5 Batcher Network 7 7 Sort 7 7 Merge 7 7 Merge CS 00
Batcher Network CS 00 7 Batcher Network How it really works Merger is preseted with a pair of sorted lists, oe i ascedig order, oe i descedig order First stage of merger seds packets to the correct half of the etwork Secod stage seds them to the correct quarter Size N/2 switches per stage log 2 N x ( + log 2 N)/2 stages Complexity = N log 22 N CS 00 8
Batcher-Baya Network Idea Attach a batcher etwork back-to-back with a baya etwork Arbitrary uique permutatios ca be routed without cotetio Two packets destied for same output port still collide! CS 00 9 Batcher-Baya Switch Architecture 0 5 0 0 0 0 0 Sort Filter Add Coc. Route 2 5 5 5 5 0 5 Simple compoets with o bufferig. filter elimiates duplicates by comparig cosecutive addresses ad returs ack to iputs adder computes ad iserts rak of cells cocetrator uses rak as output address routig etwork delivers to output Adder, cocetrator ad routig etwork all have log 2 stages (coc. is reverse baya, routig et. is baya) CS 00 20
Sushie Switch Sushie Switch Like a kockout switch Ca hadle up to L packets per output port Recirculates overflow packets If more tha L packets arrive for ay output port i oe cycle Elemets Multiple Baya etworks Eables multiple packets per output port elay Box Excess (K) packets are recirculated ad resubmitted to the switch Batcher etwork N ew packets K delayed packets Trap Idetifies packets destied for baya Idetifies excess packets Selector Routes multiple packets for same output o separate bayas CS 00 2 Sushie Switch k elay k Iputs Batcher +k Trap +k Selector L Bayas CS 00 22
Refereces Robi Kravets, Switchig Hardware, IC, CS/ECE- 8. CS 00 2