--- WARNING CS0 and WE0 are screwed up, corected by swapping the asignments..!

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---- TOPLEVEL ---------------------------------------------------------- -- NAME : toplevel.vhd -- -- DESCRIPTION : The Toplevel of the project -- -- NOTES : -- -- REVISION HISTORY : -- -- Date Programmer Description -- ------------------------ -- 11/3/1999 Mustafa Dagtekin Finalized -- --- WARNING ---- --- CS0 and WE0 are screwed up, corected by swapping the asignments..! ------------------------------------------------------------------------ -- Toplevel of the FPGA modules.. -- ------------------------------------------------------------------------ library ieee use ieee.std_logic_1164.all use IEEE.STD_Logic_unsigned.all use IEEE.STD_Logic_arith.all use work.all ------------------------------------------------------------------------ --- Signal Declarations -- ------------------------------------------------------------------------ entity toplevel is port ( clock reset -- input signals for video mode registers pci_data_in : in std_logic_vector(19 downto 0 pci_vmr_select : in std_logic_vector(1 downto 0 -- inputs to address decoder pci_cs pci_write pci_write_backup pci_read pci_read_backup pci_wr la : in std_logic_vector(24 downto 22 -- output signals from controller & address_decoder ff_enable : out std_logic_vector(18 downto 0 cs_mem : out std_logic_vector(3 downto 0 oe_mem : out std_logic_vector(3 downto 0 we_mem : out std_logic_vector(3 downto 0 --freeze ---TEST LINE -- output signals from sync_generator

HSync_Out HBlank VSync_Out VBlank blank sync_out --buffer_no --TEST LINE --output signals from delayed blank d_blank d_sync end toplevel -- output of address generator address : out std_logic_vector(19 downto 0) architecture rtl of toplevel is --------------------------------------------------------------------- ------- Component Declarations -- --------------------------------------------------------------------- component sync_gen port ( clock reset_sync load_vmr HSon : in std_logic_vector (4 downto 0) HSoff : in std_logic_vector (7 downto 0) HBoff : in std_logic_vector (8 downto 0) LineLength : in std_logic_vector (10 downto 0 VBon : in std_logic_vector (9 downto 0) VSon : in std_logic_vector (9 downto 0) VSoff : in std_logic_vector (9 downto 0) FrameSize : in std_logic_vector (9 downto 0) HSync HBlank VSync VBlank blank sync buffer_no reset_address : out std_logic end component component controller port ( clock reset blank buffer_no pci_cs pci_write pci_read pci_wr

pci_on freeze_on la : in std_logic_vector (24 downto 22 reset_sync ff_enable : out std_logic_vector(18 downto 0 cs_mem : out std_logic_vector(3 downto 0 oe_mem : out std_logic_vector(3 downto 0 we_mem : out std_logic_vector(3 downto 0 load_vmr_out : out std_logic -- freeze : out std_logic ---test line!! end component component address_counter port ( clock reset_address disable_address address : out std_logic_vector(19 downto 0) end component component vmr port ( clock reset load_vmr pci_data_in : in std_logic_vector(19 downto 0 pci_vmr_select : in std_logic_vector(1 downto 0 HSon : out std_logic_vector (4 downto 0 HSoff : out std_logic_vector (7 downto 0 HBoff : out std_logic_vector (8 downto 0 LineLength : out std_logic_vector (10 downto 0 VBon : out std_logic_vector (9 downto 0 VSon : out std_logic_vector (9 downto 0 VSoff : out std_logic_vector (9 downto 0 FrameSize : out std_logic_vector (9 downto 0 pci_on freeze_on : out std_logic end component component delayed_blank port ( clock reset blank sync d_blank d_sync end component : out std_logic signal reset_sync signal buffer_no_sig signal reset_address signal blank_int signal sync_int signal VBlank_int signal VSync signal HSync signal load_vmr signal HSon : std_logic_vector (4 downto 0 signal HSoff : std_logic_vector (7 downto 0 signal HBoff : std_logic_vector (8 downto 0 signal LineLength : std_logic_vector (10 downto 0

signal VBon : std_logic_vector (9 downto 0 signal VSon : std_logic_vector (9 downto 0 signal VSoff : std_logic_vector (9 downto 0 signal FrameSize : std_logic_vector (9 downto 0 signal interlaced_bit signal pci_on signal freeze_on blank <= VBlank_int VBlank <= blank_int -- sync <= sync_int sync_out <= not sync_int VSync_Out <= not VSync HSync_Out <= not HSync -- address(0) <= interlaced_bit -- buffer_no <= buffer_no_sig --------------------------------------------------------------- --- Component Instantiations -- --------------------------------------------------------------- sync_i: sync_gen port map ( clock => clock, reset_sync => reset_sync, load_vmr => load_vmr, HSon => HSon, HSoff => HSoff, HBoff => HBoff, LineLength => LineLength, VBon => VBon, VSon => VSon, VSoff => VSoff, FrameSize => FrameSize, HSync => HSync, HBlank => HBlank, VSync => VSync, VBlank => VBlank_int, blank => blank_int, sync => sync_int, buffer_no => buffer_no_sig, reset_address => reset_address ctrl_i: controller port map ( clock => clock, reset => reset, blank => blank_int, buffer_no => buffer_no_sig, pci_cs => pci_cs, pci_write => pci_write, pci_read => pci_read, pci_wr => pci_wr, pci_on => pci_on, freeze_on => freeze_on, la => la, reset_sync => reset_sync, ff_enable => ff_enable, cs_mem => cs_mem, oe_mem => oe_mem, we_mem => we_mem, load_vmr_out => load_vmr -- freeze => freeze addr_i: address_counter port map ( clock => clock,

reset_address => reset_address, disable_address => blank_int, address => address(19 downto 0) vmr_i : vmr port map ( clock, reset, load_vmr, pci_data_in, pci_vmr_select, HSon, HSoff, HBoff, LineLength, VBon, VSon, VSoff, FrameSize, pci_on, freeze_on delayed_blank_i: delayed_blank port map ( clock, reset, blank_int, sync_int, d_blank, d_sync end rtl

---- CONTROLLER--------------------------------------------------------- -- NAME : controller.vhd -- -- DESCRIPTION : The controller and the address decoder -- -- NOTES : -- -- REVISION HISTORY : -- -- Date Programmer Description -- ------------------------ -- 11/3/1999 Mustafa Dagtekin Finalized -- library ieee use ieee.std_logic_1164.all use IEEE.STD_Logic_unsigned.all use IEEE.STD_Logic_arith.all use work.all ------------------------------------------ --- Signal Declarations -- ------------------------------------------ entity controller is! ---! --- port ( clock reset blank buffer_no pci_cs pci_write pci_read -- read/write signals seperate!! -- read/write signals seperate!! pci_wr pci_on freeze_on --to set the freeze frame mode! la : in std_logic_vector (24 downto 22 reset_sync ff_enable : out std_logic_vector(18 downto 0 cs_mem : out std_logic_vector(3 downto 0 oe_mem : out std_logic_vector(3 downto 0 we_mem : out std_logic_vector(3 downto 0 load_vmr_out : out std_logic -- freeze : out std_logic --TEST!!!! end controller architecture behaviour of controller is type states is (reset_state, mode2, blank_state, mode3, freeze_frame signal CurrentState, NextState : states --signal rw_mem : std_logic_vector(3 downto 0 signal merged : std_logic_vector(30 downto 0 signal cont_ffen: std_logic_vector(8 downto 0

signal cont_cs : std_logic_vector(3 downto 0 signal cont_oe : std_logic_vector(3 downto 0 signal cont_we_int : std_logic_vector(3 downto 0 signal cont_we : std_logic_vector(3 downto 0 signal ad_ffen : std_logic_vector(9 downto 0 signal ad_cs : std_logic_vector(3 downto 0 signal ad_oe : std_logic_vector(3 downto 0 signal ad_we : std_logic_vector(3 downto 0 signal ad_out : std_logic_vector(3 downto 0 signal load_vmr cont: process ( CurrentState, blank, buffer_no, freeze_on) case CurrentState is when reset_state => reset_sync <= 0 cont_ffen <= "111111111" cont_cs <= "1111" cont_oe <= "1111" cont_we_int <= "1111" NextState <= blank_state when mode2 => reset_sync <= 1 cont_ffen <= "100111000" --0,3,9,12,15 cont_cs <= "0000" cont_oe <= "0001" cont_we_int <= "1110" when mode3 => if (freeze_on = 1 ) then Nextstate <= freeze_frame elsif (blank= 1 ) then NextState <= blank_state NextState <= mode2 reset_sync <= 1 cont_ffen <= "010000111" --2,5,8,12,14 cont_cs <= "0000" cont_oe <= "0010" cont_we_int <= "1101" if (freeze_on = 1 ) then Nextstate <= freeze_frame elsif (blank= 1 ) then NextState <= blank_state NextState <= mode3

when blank_state => reset_sync <= 1 cont_ffen <= "111111111" cont_cs <= "1111" cont_oe <= "1111" cont_we_int <= "1111" if (blank= 1 ) then NextState <= blank_state elsif (freeze_on = 1 ) then Nextstate <= freeze_frame elsif (buffer_no = 1 ) then NextState <= mode3 NextState <= mode2 when freeze_frame => reset_sync <= 1 cont_ffen <= "010101111" cont_cs <= "0010" cont_oe <= "0010" cont_we_int <= "1111" if (blank= 1 ) then NextState <= blank_state NextState <= freeze_frame when others => end case end process cont reset_sync <= 0 cont_ffen <= "111111111" cont_cs <= "1111" cont_oe <= "1111" cont_we_int <= "1111" NextState <= reset_state st: process (clock,reset) if (reset= 0 ) then CurrentState <= reset_state if clock EVENT and clock= 1 then CurrentState <= NextState end process st -- cont_oe <= not rw_mem cont_we(3 downto 2) <= cont_we_int(3 downto 2 -- write enable! cont_we(1) <= cont_we_int(1) or clock cont_we(0) <= cont_we_int(0) or clock

addr: process (la) case la is -- video mode registers when "101" => ad_out <= "1111" load_vmr <= 1 -- lookup table when "001" => ad_out <= "0111" -- 13, 16! load_vmr <= 0 -- pointer memory when "010" => ad_out <= "1011" -- 10, 11! load_vmr <= 0 -- VR1 when "011" => ad_out <= "1101" --1,4 load_vmr <= 0 -- VR2 -- lw/r must be HIGH! when "100" => ad_out <= "1110" --8,17 load_vmr <= 0 end case when others => ad_out <= "1111" load_vmr <= 0 end process addr -- the write enable for chips are "active low" but PLX9050 -- generates "active high" for writes.. -- pci_wr <= not pci_wr_in --freeze <= freeze_on -- TEST LINE!!!! --ad_cs <= ad_out -- there is an error in this order, the numbers -- are not in actual order.. ad_cs(3) <= ad_out(3) or pci_cs ad_cs(2) <= ad_out(2) or pci_cs ad_cs(0) <= ad_out(1) or pci_cs ad_cs(1) <= ad_out(0) or pci_cs --ad_we <= ad_ffen(7 downto 4 ad_we(3) <= ad_ffen(7) ad_we(2) <= ad_ffen(6)

ad_we(0) <= ad_ffen(5) ad_we(1) <= ad_ffen(4) --ad_oe <= not ad_ffen(7 downto 4 --ad_oe <= ad_out(3 downto 0) or (pci_wr_in & pci_wr_in & pci_wr_in & pci_wr_in ad_oe(3) ad_oe(2) ad_oe(0) ad_oe(1) <= ad_out(3) or pci_read <= ad_out(2) or pci_read <= ad_out(1) or pci_read <= ad_out(0) or pci_read ad_ffen(3 downto 0) <= ad_out ad_ffen(7) <= ad_out(3) or pci_write ad_ffen(6) <= ad_out(2) or pci_write ad_ffen(5) <= ad_out(1) or pci_write ad_ffen(4) <= ad_out(0) or pci_write --ad_ffen(9 downto 8) <= not ad_ffen(5 downto 4 ad_ffen(9) <=ad_out(1) or pci_read ad_ffen(8) <=ad_out(0) or pci_read with pci_cs select merged <= cont_ffen & "1111111111" & cont_cs & cont_oe & cont_we when 1, "111111111" & ad_ffen & ad_cs & ad_oe & ad_we when 0, (others => 1 ) when others --with pci_on select -- merged <= cont_ffen & "1111111111" & cont_cs & cont_oe & cont_we when 0, -- "111111111" & ad_ffen & ad_cs & ad_oe & ad_we when 1, -- (others => 1 ) when others end behaviour -- to load the video mode registers we need a combinational logic -- that checks PCI_CS and PCI_WR_IN load_vmr_out <= (not pci_cs) and (not pci_write) and load_vmr ff_enable <= merged (30 downto 12 cs_mem <= merged (11 downto 8 oe_mem <= merged (7 downto 4 we_mem <= merged (3 downto 0

---- ADDRESS_COUNTER --------------------------------------------------- -- NAME : address_counter.vhd -- -- DESCRIPTION : The address counter -- -- NOTES : -- -- REVISION HISTORY : -- -- Date Programmer Description -- ------------------------ -- 11/3/1999 Mustafa Dagtekin Finalized -- library ieee use ieee.std_logic_1164.all use IEEE.STD_Logic_unsigned.all use IEEE.STD_Logic_arith.all use work.all entity address_counter is port ( clock reset_address disable_address address : out std_logic_vector(19 downto 0) end address_counter architecture behaviour of address_counter is signal address_int : std_logic_vector(19 downto 0 process(clock, reset_address) if reset_address= 0 then address_int <= "00000000000000000000" if clock EVENT and clock= 1 then end process end behaviour if disable_address = 0 then address_int <= address_int + 1 address_int <= address_int address <= address_int

---- VMR --------------------------------------------------------------- -- NAME : vmr.vhd -- -- DESCRIPTION : The video mode registers -- -- NOTES : -- -- REVISION HISTORY : -- -- Date Programmer Description -- ------------------------ -- 11/3/1999 Mustafa Dagtekin Finalized -- library ieee use ieee.std_logic_1164.all use IEEE.STD_Logic_unsigned.all use IEEE.STD_Logic_arith.all use work.all entity vmr is end vmr port ( clock reset load_vmr pci_data_in : in std_logic_vector(19 downto 0 pci_vmr_select : in std_logic_vector(1 downto 0 HSon : out std_logic_vector (4 downto 0 HSoff : out std_logic_vector (7 downto 0 HBoff : out std_logic_vector (8 downto 0 LineLength : out std_logic_vector (10 downto 0 VBon : out std_logic_vector (9 downto 0 VSon : out std_logic_vector (9 downto 0 VSoff : out std_logic_vector (9 downto 0 FrameSize : out std_logic_vector (9 downto 0 -- this register is set when pci takes over pci_on -- freeze frame mode support! freeze_on : out std_logic architecture rtl of vmr is signal video_mode_regs : std_logic_vector(72 downto 0 signal pci_on_reg signal freeze_on_reg process(clock,reset) if (reset= 0 ) then video_mode_regs <= (others => 0 pci_on_reg <= 0 freeze_on_reg <= 0 --video_mode_regs(4 downto 0) <= "00010" --video_mode_regs(12 downto 5) <= "00000100" --video_mode_regs(21 downto 13) <= "000000110"

--video_mode_regs(32 downto 22) <= "00000001100" --video_mode_regs(42 downto 33) <= "0000001010" --video_mode_regs(52 downto 43) <= "0000001100" --video_mode_regs(62 downto 53) <= "0000001110" --video_mode_regs(72 downto 63) <= "0000010000" if clock EVENT and clock= 1 then if (load_vmr= 1 ) then case (pci_vmr_select) is when "00" => video_mode_regs(19 downto 0) <= pci_data_in when "01" => video_mode_regs(39 downto 20) <= pci_data_in when "10" => video_mode_regs(59 downto 40) <= pci_data_in when "11" => video_mode_regs(72 downto 60) <= pci_data_in(12 downto 0 pci_on_reg <= pci_data_in(13 freeze_on_reg <= pci_data_in(14 when others => video_mode_regs <= video_mode_regs pci_on_reg <= pci_on_reg freeze_on_reg <= freeze_on_reg end case video_mode_regs <= video_mode_regs pci_on_reg <= pci_on_reg freeze_on_reg <= freeze_on_reg end process HSon <= video_mode_regs(4 downto 0 HSoff <= video_mode_regs(12 downto 5 HBoff <= video_mode_regs(21 downto 13 LineLength <= video_mode_regs(32 downto 22 VBon <= video_mode_regs(42 downto 33 VSon <= video_mode_regs(52 downto 43 VSoff <= video_mode_regs(62 downto 53 FrameSize <= video_mode_regs(72 downto 63 pci_on <= pci_on_reg freeze_on <= freeze_on_reg end rtl

---- SYNC_GEN ---------------------------------------------------------- -- NAME : sync_gen.vhd -- -- DESCRIPTION : The sync generator -- -- NOTES : -- -- REVISION HISTORY : -- -- Date Programmer Description -- ------------------------ -- 11/3/1999 Mustafa Dagtekin Finalized -- library ieee use ieee.std_logic_1164.all use IEEE.STD_Logic_unsigned.all use IEEE.STD_Logic_arith.all library lpm use lpm.lpm_components.all entity sync_gen is end sync_gen port ( clock reset_sync load_vmr HSon : in std_logic_vector (4 downto 0 HSoff : in std_logic_vector (7 downto 0 HBoff : in std_logic_vector (8 downto 0 LineLength : in std_logic_vector (10 downto 0 VBon : in std_logic_vector (9 downto 0 VSon : in std_logic_vector (9 downto 0 VSoff : in std_logic_vector (9 downto 0 FrameSize : in std_logic_vector (9 downto 0 HSync HBlank VSync VBlank blank sync buffer_no -- line : out std_logic_vector(9 downto 0) -- pixel : out std_logic_vector(10 downto 0 reset_address : out std_logic architecture behaviour of sync_gen is signal line_counter : std_logic_vector (9 downto 0) signal pixel_counter : std_logic_vector (10 downto 0) signal HSync_sig signal HBlank_sig signal VSync_sig signal VBlank_sig signal buffer_no_sig signal reset_address_sig signal comp_framesize signal comp_framesize_reg signal field

process(clock) if((reset_sync or load_vmr) = 0 ) then reset_address_sig <= 0 buffer_no_sig <= 0 pixel_counter <="00000000000" line_counter <="0000000000" HBlank_sig <= 1 HSync_sig <= 0 VBlank_sig <= 0 VSync_sig <= 0 comp_framesize_reg <= 0 field <= 0 elsif clock EVENT and clock= 1 then if (pixel_counter = LineLength) then HBlank_sig <= 1 pixel_counter <= (others => 0 sig xor field n en if(comp_framesize_reg = 1 ) then Vblank_sig <= 0 line_counter <= (others => 0 field <= not field reset_address_sig <= field buffer_no_sig <= not (buffer_no_ line_counter <= line_counter + 1 reset_address_sig <= 1 if (line_counter = VBon) then VBlank_sig <= 1 elsif (line_counter = VSon) the VSync_sig <= 1 elsif (line_counter = VSoff) th VSync_sig <= 0 VBlank_sig <= VBlank_sig VSync_sig <= VSync_sig pixel_counter <= pixel_counter + 1 if (pixel_counter = "000000"&HSon) then HSync_sig <= 1 elsif (pixel_counter = "000"&Hsoff) then HSync_sig <= 0 elsif (pixel_counter = "00"&HBoff) then HBlank_sig <= 0 HBlank_sig <= HBlank_sig HSync_sig <= HSync_sig

comp_framesize_reg <= comp_framesize end process --process (line_counter) -- -- if (line_counter = FrameSize) then -- comp_framesize <= 1 -- -- comp_framesize <= 0 -- --end process lpm_comp_i: lpm_compare generic map (lpm_width => 10, lpm_pipeline => 1, lpm_type => l_compare ) port map ( dataa => line_counter(9 downto 0), datab => FrameSize(9 downto 0), aeb => comp_framesize, clock => clock blank <= HBlank_sig or VBlank_sig sync <= HSync_sig or VSync_sig VBlank <= VBlank_sig VSync <= VSync_sig HBlank <= HBlank_sig HSync <= HSync_sig buffer_no <= buffer_no_sig reset_address <= reset_address_sig line <= line_counter pixel <= pixel_counter end behaviour

---- DELAYED_BLANK ----------------------------------------------------- -- NAME : delayed_blank.vhd -- -- DESCRIPTION : This module creates the synchronization signals -- -- the DAC module -- -- NOTES : -- -- REVISION HISTORY : -- -- Date Programmer Description -- ------------------------ -- 11/3/1999 Mustafa Dagtekin Finalized -- library ieee use ieee.std_logic_1164.all use IEEE.STD_Logic_unsigned.all use IEEE.STD_Logic_arith.all use work.all entity delayed_blank is port (clock reset blank sync d_blank d_sync : out std_logic end delayed_blank architecture rtl of delayed_blank is signal int1_blank signal int1_sync process (clock, reset) if reset= 0 then int1_blank <= 0 int1_sync <= 0 --int3_blank <= 0 --int4_blank <= 0 end rtl elsif clock EVENT and clock= 1 then end process int1_blank <= not blank d_blank <= int1_blank int1_sync <= not sync d_sync <= int1_sync

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