Digital System Construction
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1 Digital System Construction FYSIKUM Lecture 4: More VHDL, memory, PRNG Arithmetic Memories Pipelines and buffers Pseudorandom numbers IP core generation in Vivado Introduction to Lab 3 Digital Systemkonstruktion - 1 1
2 Arithmetic with vectors ieee.std_logic_unsigned.all Simple arithmetic with vectors representing unisigned numbers Easy to use, but not an official standard ieee.numeric_std.all Standard library supporting unsigned and signed vector arithmetic Adds signed and unsigned vector types Slightly higher learning curve Recommended for new designs Digital Systemkonstruktion - 1 2
3 Example: unsigned adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all ; ENTITY adder16 IS PORT (X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout : OUT STD_LOGIC ) ; END adder16 ;
4 Unsigned adder: architecture ARCHITECTURE Behavior OF adder16 IS SIGNAL ux : UNSIGNED(15 DOWNTO 0); bits SIGNAL uy : UNSIGNED(15 DOWNTO 0); SIGNAL Sum : UNSIGNED(16 DOWNTO 0); bits BEGIN ux <= unsigned(x); uy <= unsigned(y); Sum <= ('0' & ux) + ('0' & uy); S <= std_logic_vector(sum(15 DOWNTO 0)) ; Cout <= Sum(16) ; -- Top bit is overflow/carry END Behavior ;
5 Signed numbers A vector can represent a signed or unsigned value 8 bits unsigned: 0 to bits signed: -128 to +127 For signed numbers: Top bit (MSB) is the sign (0=positive, 1=negative) Positive numbers: simple binary representation Decimal +53 = Negative numbers: twos complement Invert the bits of the positive value, then add one Decimal -53 = = Digital Systemkonstruktion - 1 5
6 Example: signed adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.numeric_std.all ; ENTITY adder16 IS PORT (X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END adder16 ;
7 Signed adder: architecture ARCHITECTURE Behavior OF adder16 IS SIGNAL Xs : SIGNED(15 DOWNTO 0); SIGNAL Ys : SIGNED(15 DOWNTO 0); SIGNAL Sum : SIGNED(16 DOWNTO 0) ; BEGIN Xs <= signed(x); Ys <= signed(y); Sum <= resize(xs,sum LENGTH) + Ys; S <= std_logic_vector(resize(sum,16)) ; END Behavior ;
8 ieee.numeric_std has overloaded operators Digital Systemkonstruktion - 1 8
9 Memory basics Memory is essentially a data storage array One or more bits of data at each address Different memory types include: ROM (Read-Only Memory) No write capability during normal operations Modern versions allow erase/overwrite by applying higher voltages RAM (Random Access Memory) Individual bit access, read and write capabilities Volatility Volatile memories lose data when power is off Most RAM is volatile, ROM is non-volatile Digital Systemkonstruktion - 1 9
10 Random Access Memory (RAM) Addressable data storage array Directly access contents of each address Read and write operations supported Normally, ~equal access time to any address not quite true for modern DRAM Can be synchronous (clocked) or asynchronous RAM on Xilinx FPGA is synchronous Digital Systemkonstruktion
11 Static vs. Dynamic RAM DRAM stores charge in quantum wells (analogous to capacitors) Small, inexpensive (good!) Data disappears after short time if not refreshed (not so good ) SRAM stores data stably in latches Stable, no need to refresh (good!) More transistors per data bit Larger, more expensive Less memory/area Most FPGAs have blocks of SRAM DRAM SRAM Digital Systemkonstruktion
12 Single-port RAM block Word size: n bits Capacity: 2 k words Some RAM is clocked, some not k n Address Data_in Wr_en Rd_en Data_out n Clock Digital Systemkonstruktion
13 Writing to memory Sequence of steps: Set address and data (input ports) Assert write Synchronous RAM needs a clock edge Data contents are now stored at the specified address Digital Systemkonstruktion
14 Reading from memory Steps: Set address (input port) Assert read Data available after a certain delay Or with clock edge for a synchronous RAM Digital Systemkonstruktion
15 Xilinx 7-series RAM 36Kb and 18Kb block memories Two independent ports ( dual port RAM ) Distributed RAM also available Can balance address, data widths for same # of total bits 36Kb: 32Kx1bit to 512x72bit 64Kx1b if cascaded with an adjacent 36Kb RAM 18Kb: 16Kx1bit to 512x36bit Synchronous read/write Need a clock Digital Systemkonstruktion
16 Common RAM applications Local memory for embedded CPUs (advanced) Fast, flexible implementation of complex algorithms Memory look-up tables Content-addressable memory (advanced) Diagnostics and testing Capture data and read it out ( spy memory ) Feed test patterns through logic ( playback memory ) Data buffering for temporary storage and readout Synchronous memory buffer ( pipeline ) Asynchronous buffer ( FIFO ) Digital Systemkonstruktion
17 Memory lookup table (LUT) Common application: Use LUT to correct raw data calibration, linearity, etc. Can also do geometric and other calculations quickly ADC 12b A LUT B 10b count count E E 17
18 ATLAS L1Calo example EEM EHad 9 9 Thr Thr Σ Apply thresholds (LUT) and sum (logic) 10 Ex = Et sin ϕ Ey = Et cos ϕ ET Ex Ey To Summation logic LUTs for geometric calculations 18
19 Spy/playback memories Play test data to processing logic Capture output data Data in Data out Capture input data Input mem Processing logic Output mem Play test data (to next board) Computer interface Digital Systemkonstruktion
20 Asynchronous data buffer Port A DPR Port B Counter Address Counter n_write Data in Data n_read Data out Simplified diagram. Write to port A and read from port B. Address of each port incremented during read/write Digital Systemkonstruktion
21 Synchronous delay buffer Offset Adder A B Sum DPR Address Counter Clock Data in CLK Port A Data Port B Data out Digital Systemkonstruktion
22 Other topics for Lab 3 Pseudorandom number generation You will use this to test a synchronous data pipeline with adjustable length Implementing device-specific features CoreGen in Xilinx ISE IP Catalog in Vivado You will use this to implement a dual-port RAM Digital Systemkonstruktion
23 Pseudorandom number generator Useful to test designs with many possible inputs Basic concept: Start with a random sequence of bits circulating in a shift register ( seed ) Continuously change the contents of the seed use XOR of other bits (to maintain 1/0 balance) Digital Systemkonstruktion
24 Single-bit PNRG: entity Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; need a different seed for each PNRG entity prng is generic(init_seed : std_logic_vector (15 downto 0) := " "); port( clk : in std_logic; random : out std_logic); end prng; Digital Systemkonstruktion
25 Single-bit PNRG: architecture architecture prng_arch of prng is signal seed : std_logic_vector (15 downto 0) := init_seed; begin gen_number: process(clk) begin if rising_edge(clk) then seed <= seed(14 downto 0) & (seed(15) xor seed(13) xor seed(12) xor seed(10)); end if; end process; random <= seed(15); end architecture; Maximum-length LFSR linear feedback shift register Digital Systemkonstruktion
26 Generating IP cores in Vivado Many design elements well-described with pure VHDL But device-specific features often need to be declared more precisely: Block memories, dedicated multipliers, digital clock managers, embedded CPUs, fast transceivers, etc. Vendors provide tools to generate code that takes full advantage of these features Xilinx examples: CoreGen (ISE) IP Catalog (Vivado) Digital Systemkonstruktion
27 Launch IP catalog Digital Systemkonstruktion
28 Select the core you want Right click: Customize IP Digital Systemkonstruktion
29 Customize the component Component name Basic configuration Digital Systemkonstruktion
30 Customize the component Configure the ports Digital Systemkonstruktion
31 Generated component Digital Systemkonstruktion
32 Lab 3: Design a 4-bit PRNG Design a programmable-delay pipeline buffer with a block RAM Connect the PRNG output to the buffer input and look at the delayed buffer output Simulation and oscilloscope! Digital Systemkonstruktion
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