PSoC 4 BLE TRM. PSoC 4 BLE Architecture Technical Reference Manual (TRM) PSoC 41XX_BLE/42XX_BLE Family. Document No Rev.

PSoC 4 BLE TRM PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture Technical Reference Manual (TRM) Document No. 001-92738 Rev. *D May 31, 2017 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 www.cypress.com

Copyrights Copyrights Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PUR- POSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. 2 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

Contents Overview Section A: Overview 17 1. Introduction... 19 2. Getting Started... 29 3. Document Construction... 31 Section B: CPU System 35 4. Cortex-M0 CPU... 37 5. DMA Controller Modes... 43 6. Interrupts... 57 Section C: System Resources Subsystem (SRSS) 67 7. I/O System... 69 8. Clocking System... 83 9. Power Supply and Monitoring... 95 10. Chip Operational Modes... 99 11. Power Modes... 101 12. Watchdog Timer... 107 13. Reset System... 111 14. Device Security... 115 Section D: Digital System 117 15. Serial Communications Block (SCB)... 119 16. Universal Digital Blocks (UDB)... 161 17. Timer, Counter, and PWM... 203 18. Bluetooth Low Energy Subsystem (BLESS)... 227 Section E: Analog System 245 18. Precision Reference... 247 19. SAR ADC... 251 20. Low-Power Comparator... 283 21. Continuous Time Block mini (CTBm)... 289 22. LCD Direct Drive... 299 23. CapSense... 311 24. Temperature Sensor... 321 Section F: Program and Debug 325 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 3

Contents 26. Program and Debug Interface... 327 27. Nonvolatile Memory Programming... 335 Glossary 349 Index 365 4 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

Contents Section A: Overview 17 Document Revision History...17 1. Introduction 19 1.1 Top Level Architecture...19 1.2 Features...25 1.3 CPU System...25 1.3.1 Processor...25 1.3.2 Interrupt Controller...26 1.3.3 Direct Memory Access...26 1.4 Memory...26 1.4.1 Flash...26 1.4.2 SRAM...26 1.5 System-Wide Resources...26 1.5.1 Clocking System...26 1.5.2 Power System...26 1.5.3 GPIO...26 1.6 Bluetooth Low-Energy Subsystem...27 1.6.1 RF Transceiver...27 1.6.2 Digital PHY Modem...27 1.6.3 Link Layer Controller...27 1.7 Programmable Digital...27 1.8 Fixed-Function Digital...27 1.8.1 Timer/Counter/PWM Block...27 1.8.2 Serial Communication Blocks...27 1.9 Analog System...27 1.9.1 SAR ADC...27 1.9.2 Continuous Time Block mini...27 1.9.3 Low-Power Comparators...27 1.10 Special Function Peripherals...28 1.10.1 LCD Segment Drive...28 1.10.2 CapSense...28 1.10.2.1 IDACs and Comparator...28 1.11 Program and Debug...28 1.12 Device Feature Summary...28 2. Getting Started 29 2.1 Support...29 2.2 Product Upgrades...29 2.3 Development Kits...29 2.4 Application Notes...29 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 5

Contents 3. Document Construction 31 3.1 Major Sections...31 3.2 Documentation Conventions...31 3.2.1 Register Conventions...31 3.2.2 Numeric Naming...31 3.2.3 Units of Measure...32 3.2.4 Acronyms...32 Section B: CPU System 35 Top Level Architecture...35 4. Cortex-M0 CPU 37 4.1 Features...37 4.2 Block Diagram...38 4.3 How It Works...38 4.4 Address Map...38 4.5 Registers...39 4.6 Operating Modes...40 4.7 Instruction Set...40 4.7.1 Address Alignment...41 4.7.2 Memory Endianness...41 4.8 Systick Timer...41 4.9 Debug...41 5. DMA Controller Modes 43 5.1 Block Diagram Description...43 5.1.1 Trigger Sources and Multiplexing...44 5.1.1.1 Trigger Multiplexer...44 5.1.1.2 Creating Software Triggers...46 5.1.2 Pending Triggers...46 5.1.3 Output Triggers...46 5.1.4 Channel Prioritization...46 5.1.5 Data Transfer Engine...46 5.2 Descriptors...47 5.2.1 Address Configuration...47 5.2.2 Transfer Size...48 5.2.3 Descriptor Chaining...49 5.2.4 Transfer Mode...49 5.2.4.1 Single Data Element Per Trigger (OPCODE 0)...49 5.2.4.2 Entire Descriptor Per Trigger (OPCODE 1)...51 5.2.4.3 Entire Descriptor Chain Per Trigger (OPCODE 2)...52 5.3 Operation and Timing...53 5.4 Arbitration...54 5.5 Register List...56 6. Interrupts 57 6.1 Features...57 6.2 How It Works...57 6.3 Interrupts and Exceptions - Operation...58 6.3.1 Interrupt/Exception Handling...58 6.3.2 Level and Pulse Interrupts...58 6.3.3 Exception Vector Table...59 6.4 Exception Sources...59 6 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

Contents 6.4.1 Reset Exception...59 6.4.2 Non-Maskable Interrupt (NMI) Exception...60 6.4.3 HardFault Exception...60 6.4.4 Supervisor Call (SVCall) Exception...60 6.4.5 PendSV Exception...60 6.4.6 SysTick Exception...61 6.5 Interrupt Sources...61 6.6 Exception Priority...62 6.7 Enabling and Disabling Interrupts...63 6.8 Exception States...63 6.8.1 Pending Exceptions...63 6.9 Stack Usage for Exceptions...64 6.10 Interrupts and Low-Power Modes...64 6.11 Exceptions Initialization and Configuration...65 6.12 Registers...65 6.13 Associated Documents...65 Section C: System Resources Subsystem (SRSS) 67 Top Level Architecture...67 7. I/O System 69 7.1 Features...69 7.2 GPIO Interface Overview...69 7.3 I/O Cell Architecture...70 7.3.1 Digital Input Buffer...72 7.3.2 Digital Output Driver...72 7.3.2.1 Drive Modes...72 7.3.2.2 Slew Rate Control...74 7.4 GPIO-OVT Pin...74 7.5 High-Speed I/O Matrix...77 7.6 I/O State on Power Up...77 7.7 Behavior in Low-Power Modes...78 7.8 Input and Output Synchronization...78 7.9 Interrupt...78 7.10 Peripheral Connections...80 7.10.1 Firmware Controlled GPIO...80 7.10.2 Analog I/O...80 7.10.2.1 AMUXBUS Connection and DSI...80 7.10.3 LCD Drive...80 7.10.4 CapSense...80 7.10.5 Bluetooth Low Energy Sub-System (BLESS)...81 7.10.6 Serial Communication Block (SCB)...82 7.11 Port Restrictions...82 7.12 Registers...82 8. Clocking System 83 8.1 Block Diagram...83 8.2 Clock Sources...84 8.2.1 Internal Main Oscillator...84 8.2.1.1 Startup Behavior...85 8.2.1.2 IMO Frequency Spread...86 8.2.1.3 Programming Clock (36-MHz)...86 8.2.2 Internal Low-speed Oscillator...86 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 7

Contents 8.2.3 External Clock (EXTCLK)...86 8.2.4 External Crystal Oscillator (ECO)...87 8.2.4.1 ECO Load Capacitor Tuning...87 8.2.5 Watch Crystal Oscillator (WCO)...87 8.3 Clock Distribution...88 8.3.1 HFCLK Input Selection...88 8.3.2 LFCLK Input Selection...88 8.3.3 ECO Divider Configuration...88 8.3.4 SYSCLK Prescaler Configuration...89 8.3.5 Peripheral Clock Divider Configuration...89 8.3.6 Peripheral Clock Configuration...91 8.3.6.1 Clock Generation...91 8.4 Low-Power Mode Operation...92 8.5 Register List...93 9. Power Supply and Monitoring 95 9.1 Block Diagram...95 9.2 How It Works...96 9.2.1 Regulator Summary...96 9.2.1.1 Core Regulators...96 9.2.1.2 RF Transceiver Regulators...96 9.3 Voltage Monitoring...97 9.3.1 Power-On-Reset (POR)...97 9.3.1.1 Brownout-Detect (BOD)...97 9.3.1.2 Low-Voltage-Detect (LVD)...97 9.4 Register List...98 10. Chip Operational Modes 99 10.1 Boot...99 10.2 User...99 10.3 Privileged...99 10.4 Debug...99 11. Power Modes 101 11.1 Active Mode...102 11.2 Sleep Mode...102 11.3 Deep-Sleep Mode...103 11.4 Hibernate Mode...103 11.5 Stop Mode...103 11.6 Power Mode Summary...104 11.7 Low-Power Mode Entry and Exit...105 11.8 Register List...106 12. Watchdog Timer 107 12.1 Features...107 12.2 Block Diagram...107 12.3 How It Works...108 12.3.1 Enabling and Disabling WDT...109 12.3.2 WDT Operating Modes...109 12.3.3 WDT Interrupts and Low-Power Modes... 110 12.3.4 WDT Reset Mode... 110 12.4 Register List...110 8 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

Contents 13. Reset System 111 13.1 Reset Sources...111 13.1.1 Power-on Reset... 111 13.1.2 Brownout Reset... 111 13.1.3 Watchdog Reset... 111 13.1.4 Software Initiated Reset...112 13.1.5 External Reset...112 13.1.6 Protection Fault Reset...112 13.1.7 Hibernate Wakeup Reset...112 13.1.8 Stop Wakeup Reset...112 13.2 Identifying Reset Sources...112 13.3 Register List...113 14. Device Security 115 14.1 Features...115 14.2 How It Works...115 14.2.1 Device Security...115 14.2.2 Flash Security...116 Section D: Digital System 117 Top Level Architecture...117 15. Serial Communications Block (SCB) 119 15.1 Features...119 15.2 Serial Peripheral Interface (SPI)...119 15.2.1 Features...119 15.2.2 General Description...120 15.2.3 SPI Modes of Operation...121 15.2.3.1 Motorola SPI...121 15.2.3.2 Texas Instruments SPI...122 15.2.3.3 National Semiconductors SPI...124 15.2.4 Using SPI Master to Clock Slave...125 15.2.5 Easy SPI Protocol...125 15.2.5.1 EZ Address Write...125 15.2.5.2 Memory Array Write...125 15.2.5.3 Memory Array Read...125 15.2.5.4 Configuring SCB for EZSPI Mode...126 15.2.6 SPI Registers...127 15.2.7 SPI Interrupts...128 15.2.8 Enabling and Initializing SPI...128 15.2.9 Internally and Externally Clocked SPI Operations...130 15.2.9.1 Non-EZ Mode of Operation...131 15.2.9.2 EZ Mode of Operation...131 15.3 UART...133 15.3.1 Features...133 15.3.2 General Description...133 15.3.3 UART Modes of Operation...133 15.3.3.1 Standard Protocol...133 15.3.3.2 SmartCard (ISO7816)...138 15.3.3.3 IrDA...139 15.3.4 UART Registers...140 15.3.5 UART Interrupts...141 15.3.6 Enabling and Initializing UART...141 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 9

Contents 15.4 Inter Integrated Circuit (I2C)...143 15.4.1 Features...143 15.4.2 General Description...143 15.4.3 Terms and Definitions...144 15.4.3.1 Clock Stretching...144 15.4.3.2 Bus Arbitration...144 15.4.4 I2C Modes of Operation...144 15.4.4.1 Write Transfer...145 15.4.4.2 Read Transfer...145 15.4.5 Easy I2C (EZI2C) Protocol...146 15.4.5.1 Memory Array Write...146 15.4.5.2 Memory Array Read...146 15.4.6 I2C Registers...147 15.4.7 I2C Interrupts...148 15.4.8 Enabling and Initializing the I2C...148 15.4.8.1 Configuring for I2C Standard (Non-EZ) Mode...148 15.4.8.2 Configuring for EZI2C Mode...149 15.4.9 Internal and External Clock Operation in I2C...149 15.4.9.1 I2C Non-EZ Mode of Operation...150 15.4.9.2 I2C EZ Operation Mode...150 15.4.10 Wake up from Sleep...151 15.4.11 Master Mode Transfer Examples...152 15.4.11.1 Master Transmit...152 15.4.11.2 Master Receive...153 15.4.12 Slave Mode Transfer Examples...154 15.4.12.1 Slave Transmit...154 15.4.12.2 Slave Receive...155 15.4.13 EZ Slave Mode Transfer Example...156 15.4.13.1 EZ Slave Transmit...156 15.4.13.2 EZ Slave Receive...157 15.4.14 Multi-Master Mode Transfer Example...158 15.4.14.1 Multi-Master - Slave Not Enabled...158 15.4.14.2 Multi-Master - Slave Enabled...159 16. Universal Digital Blocks (UDB) 161 16.1 Features...161 16.2 How It Works...162 16.2.1 PLDs...162 16.2.1.1 PLD Macrocells...163 16.2.1.2 PLD Carry Chain...164 16.2.1.3 PLD Configuration...164 16.2.2 Datapath...164 16.2.2.1 Overview...165 16.2.2.2 Datapath FIFOs...166 16.2.2.3 FIFO Status...173 16.2.2.4 Datapath ALU...173 16.2.2.5 Datapath Inputs and Multiplexing...176 16.2.2.6 CRC/PRS Support...177 16.2.2.7 Datapath Outputs and Multiplexing...179 16.2.2.8 Datapath Parallel Inputs and Outputs...181 16.2.2.9 Datapath Chaining...181 16.2.2.10 Dynamic Configuration RAM...182 16.2.3 Status and Control Module...183 10 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

Contents 16.2.3.1 Status and Control Mode...185 16.2.3.2 Control Register Operation...186 16.2.3.3 Parallel Input/Output Mode...187 16.2.3.4 Counter Mode...188 16.2.3.5 Sync Mode...189 16.2.3.6 Status and Control Clocking...189 16.2.3.7 Auxiliary Control Register...189 16.2.3.8 Status and Control Register Summary...190 16.2.4 Reset and Clock Control Module...190 16.2.4.1 Clock Control...191 16.2.4.2 Reset Control...192 16.2.4.3 UDB POR Initialization...197 16.2.5 UDB Addressing...198 16.2.6 System Bus Access Coherency...198 16.2.6.1 Simultaneous System Bus Access...198 16.2.6.2 Coherent Accumulator Access (Atomic Reads and Writes)...198 16.3 Port Adapter Block...199 16.3.1 PA Data Input Logic...199 16.3.2 PA Port Pin Clock Multiplexer Logic...200 16.3.3 PA Data Output Logic...200 16.3.4 PA Output Enable Logic...201 16.3.5 PA Clock Multiplexer...202 16.3.6 PA Reset Multiplexer...202 17. Timer, Counter, and PWM 203 17.1 Features...203 17.2 Block Diagram...204 17.2.1 Enabling and Disabling Counter in TCPWM Block...204 17.2.2 Clocking...204 17.2.3 Events Based on Trigger Inputs...206 17.2.4 Output Signals...207 17.2.4.1 Signals upon Trigger Conditions...207 17.2.4.2 Interrupts...207 17.2.4.3 Outputs...208 17.2.5 Power Modes...208 17.3 Modes of Operation...209 17.3.1 Timer Mode...210 17.3.1.1 Block Diagram...210 17.3.1.2 How It Works...210 17.3.1.3 Configuring Counter for Timer Mode...212 17.3.2 Capture Mode...213 17.3.2.1 Block Diagram...213 17.3.2.2 How it Works...213 17.3.2.3 Configuring Counter for Capture Mode...214 17.3.3 Quadrature Decoder Mode...215 17.3.3.1 Block Diagram...215 17.3.3.2 How It Works...215 17.3.3.3 Configuring Counter for Quadrature Mode...217 17.3.4 Pulse Width Modulation Mode...218 17.3.4.1 Block Diagram...218 17.3.4.2 How It Works...218 17.3.4.3 Other Configurations...220 17.3.4.4 Kill Feature...220 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 11

Contents 17.3.4.5 Configuring Counter for PWM Mode...221 17.3.5 Pulse Width Modulation with Dead Time Mode...222 17.3.5.1 Block Diagram...222 17.3.5.2 How It Works...222 17.3.5.3 Configuring Counter for PWM with Dead Time Mode...223 17.3.6 Pulse Width Modulation Pseudo-Random Mode...224 17.3.6.1 Block Diagram...224 17.3.6.2 How It Works...224 17.3.6.3 Configuring Counter for Pseudo-Random PWM Mode...225 17.4 TCPWM Registers...226 18. Bluetooth Low Energy Subsystem (BLESS) 227 18.1 Features...227 18.2 Block Diagram...227 18.3 How it Works...228 18.3.1 LFCLK Initialization...228 18.3.2 Radio-PHY Block...228 18.3.2.1 Power Supply...228 18.3.2.2 RF Initialization...229 18.3.3 Link Layer Controller...230 18.3.3.1 Clocking...230 18.3.3.2 Firmware Reset...231 18.3.3.3 BLE Functional Modes and Configuration...231 18.3.4 Power Modes...232 18.3.4.1 Deep Sleep Mode...233 18.3.4.2 Sleep Mode...233 18.3.4.3 Idle Mode...233 18.3.4.4 Transmit Mode...233 18.3.4.5 Receive Mode...233 18.3.5 Mode Transitions...233 18.3.5.1 LL Sleep Mode Entry with Auto Wakeup...233 18.3.5.2 LL Sleep Mode Entry with No Auto Wakeup...234 18.3.5.3 Manual Exit from Sleep Mode...234 18.3.5.4 LL Deep Sleep Mode Entry with Auto Wakeup...234 18.3.5.5 LL Extended Deep Sleep Mode Entry...235 18.3.5.6 LL Deep Sleep Mode Manual and Auto Exit...236 18.3.5.7 LL Extended Deep Sleep Mode Manual Exit...237 18.3.6 Bluetooth LE 4.2 Feature Data Length Extension238 18.3.7 Bluetooth LE 4.2 Feature Privacy 1.2238 18.3.7.1 Resolving List...238 18.3.7.2 Resolving List Functions...239 18.3.7.3 Handling Peer Devices that Do Not Use RPA...240 18.3.7.4 Handling Unresolved Self RPA...240 18.4 Register Details...241 Section E: Analog System 245 Top Level Architecture...245 18. Precision Reference 247 18.1 Features...247 18.2 Block Diagram...247 12 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

Contents 18.3 How it Works...248 18.3.1 Precision Bandgap...248 18.3.2 Trim Buffer...248 18.3.3 Low-Power Buffers...248 18.3.4 Current Mirrors...249 18.3.5 Temperature-Controlled Voltage Generator...249 18.3.6 Temperature-Controlled Current Generator...249 18.4 Configuration...249 19. SAR ADC 251 19.1 Features...251 19.2 Block Diagram...252 19.3 How it Works...253 19.3.1 SAR ADC Core...253 19.3.1.1 Single-ended and Differential Mode...253 19.3.1.2 Input Range...253 19.3.1.3 Result Data Format...253 19.3.1.4 Negative Input Selection...254 19.3.1.5 Resolution...255 19.3.1.6 Acquisition Time...255 19.3.1.7 SAR ADC Clock...255 19.3.1.8 SAR ADC Timing...256 19.3.2 SARMUX...256 19.3.2.1 Analog Routing...256 19.3.2.2 Analog Interconnection...257 19.3.3 SARREF...264 19.3.3.1 Reference Options...264 19.3.3.2 Bypass Capacitors...264 19.3.3.3 Input Range versus Reference...265 19.3.4 SARSEQ...265 19.3.4.1 Averaging...266 19.3.4.2 Range Detection...266 19.3.4.3 Double Buffer...267 19.3.4.4 Injection Channel...267 19.3.5 Interrupt...267 19.3.5.1 End-of-Scan Interrupt (EOS_INTR)...267 19.3.5.2 Overflow Interrupt...268 19.3.5.3 Collision Interrupt...268 19.3.5.4 Injection End-of-Conversion Interrupt (INJ_EOC_INTR)...268 19.3.5.5 Range Detection Interrupts...268 19.3.5.6 Saturate Detection Interrupts...268 19.3.5.7 Interrupt Cause Overview...269 19.3.6 Trigger...269 19.3.6.1 DSI Trigger Configuration...269 19.3.7 SAR ADC Status...270 19.3.8 Low-Power Mode...270 19.3.9 System Operation...270 19.3.10 Register Mode...272 19.3.10.1 SARMUX Analog Routing...272 19.3.10.2 Global SARSEQ Configuration...273 19.3.10.3 Channel Configurations...273 19.3.10.4 Channel Enables...274 19.3.10.5 Interrupt Masks...274 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 13

Contents 19.3.10.6 Trigger...274 19.3.10.7 Retrieve Data after Each Interrupt...274 19.3.10.8 Injection Conversions...274 19.3.11 DSI Mode...275 19.3.11.1 Firmware Analog Routing...276 19.3.11.2 DSI Analog Routing...276 19.3.11.3 Global SARSEQ Configuration...277 19.3.11.4 DSI Channel Configuration...277 19.3.11.5 Interrupt...277 19.3.11.6 Trigger...277 19.3.11.7 Retrieve Data...278 19.3.11.8 DSI Output Enable...278 19.3.12 Analog Routing Configuration Example...278 19.3.13 Temperature Sensor Configuration...281 19.4 Registers...282 20. Low-Power Comparator 283 20.1 Features...283 20.2 Block Diagram...284 20.3 How It Works...284 20.3.1 Input Configuration...284 20.3.2 Output and Interrupt Configuration...285 20.3.3 Power Mode and Speed Configuration...286 20.3.4 Hysteresis...287 20.3.5 Wakeup from Low-Power Modes...287 20.3.6 Comparator Clock...287 20.3.7 Offset Trim...287 20.4 Register Summary...288 21. Continuous Time Block mini (CTBm) 289 21.1 Features...289 21.2 Block Diagram...290 21.3 How It Works...290 21.3.1 Power Mode Configuration...291 21.3.2 Output Strength Configuration...291 21.3.3 Compensation...292 21.3.4 Switch Control...292 21.3.4.1 Input Configuration...293 21.3.4.2 Output Configuration...294 21.3.4.3 Comparator Mode...295 21.3.4.4 Comparator Configuration...295 21.3.4.5 Comparator Interrupt...296 21.3.4.6 Deep-Sleep Mode Operation...296 21.4 Register Summary...298 22. LCD Direct Drive 299 22.1 Features...299 22.2 LCD Segment Drive Overview...299 22.2.1 Drive Modes...300 22.2.1.1 PWM Drive...300 22.2.1.2 Digital Correlation...305 22.2.2 Recommended Usage of Drive Modes...308 22.2.3 Digital Contrast Control...308 14 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

Contents 22.3 Block Diagram...309 22.3.1 How it Works...309 22.3.2 High-Speed and Low-Speed Master Generators...309 22.3.3 Multiplexer and LCD Pin Logic...310 22.3.4 Display Data Registers...310 22.4 Register List...310 23. CapSense 311 23.1 Features...311 23.2 Block Diagram...311 23.3 How It Works...312 23.4 CapSense CSD Sensing...313 23.4.1 GPIO Cell Capacitance to Current Converter...313 23.4.2 CapSense Clock Generator...315 23.4.3 Sigma Delta Converter...315 23.5 CapSense CSD Shielding...317 23.5.1 CMOD Precharge...318 23.6 General-Purpose Resources: IDACs and Comparator...319 23.7 Register List...319 24. Temperature Sensor 321 24.1 Features...321 24.2 How it Works...321 24.3 Temperature Sensor Configuration...322 24.4 Algorithm...324 24.5 Registers...324 Section F: Program and Debug 325 Top Level Architecture...325 26. Program and Debug Interface 327 26.1 Features...327 26.2 Functional Description...327 26.3 Serial Wire Debug (SWD) Interface...328 26.3.1 SWD Timing Details...329 26.3.2 ACK Details...329 26.3.3 Turnaround (Trn) Period Details...329 26.4 Cortex-M0 Debug and Access Port (DAP)...330 26.4.1 Debug Port (DP) Registers...330 26.4.2 Access Port (AP) Registers...330 26.5 Programming the PSoC 4 Device...331 26.5.1 SWD Port Acquisition...331 26.5.1.1 Primary and Secondary SWD Pin Pairs...331 26.5.1.2 SWD Port Acquire Sequence...331 26.5.2 SWD Programming Mode Entry...331 26.5.3 SWD Programming Routines Executions...331 26.6 PSoC 4 SWD Debug Interface...332 26.6.1 Debug Control and Configuration Registers...332 26.6.2 Breakpoint Unit (BPU)...332 26.6.3 Data Watchpoint (DWT)...332 26.6.4 Debugging the PSoC 4 Device...332 26.7 Registers...333 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 15

Contents 27. Nonvolatile Memory Programming 335 27.1 Features...335 27.2 Functional Description...335 27.3 System Call Implementation...336 27.4 Blocking and Non-Blocking System Calls...336 27.4.1 Performing a System Call...336 27.5 System Calls...337 27.5.1 Silicon ID...337 27.5.2 Configure Clock...338 27.5.3 Load Flash Bytes...339 27.5.4 Write Row...340 27.5.5 Program Row...340 27.5.6 Erase All...341 27.5.7 Checksum...342 27.5.8 Write Protection...342 27.5.9 Non-Blocking Write Row...343 27.5.10 Non-Blocking Program Row...344 27.5.11 Resume Non-Blocking...345 27.6 System Call Status...346 27.7 Non-Blocking System Call Pseudo Code...347 Glossary 349 Index 365 16 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

Section A: Overview This section encompasses the following chapters: Introduction chapter on page 19 Getting Started chapter on page 29 Document Construction chapter on page 31 Document Revision History Revision Issue Date Origin of Change ** June 27, 2014 PMAD New PSoC 4 BLE TRM *A December 19, 2014 UDYG *B June 29, 2015 UDYG Description of Change In the SCB chapter, updated the SCB_RX_CTRL register description and added MEDIAN bit in the SCB_RX_CTRL register. Removed the ENABLE bit of the SCB_TX_CTRL and SCB_RX_CTRL registers. Updated the procedure to configure SCB as UART IrDA interface. In the Introduction chapter, updated Figure 1-1 and Figure 1-2. Updated the CTBm section of the chapter to say that PSoC 42x7-BL has two CTBm blocks while PSoC 41x7-BL has one CTBm block. Corrected general grammatical errors. In the TCPWM chapter, added STOP power mode description to the Power Modes section. Corrected the GENERIC bit field in TCPWM_CNT_CTRL register to [15:8] in various places. In the LPCOMP chapter, updated the pin numbers for input pins of Comparator 1 to P0[4] and P0[5]. Added support for the PSoC 4 BLE 256KB flash family. Updated the device family name in the title. *C February 12, 2016 UDYG Added information on DMA support in the Introduction chapter and added the DMA chapter. Updated the BLESS chapter with information on support for Bluetooth 4.2-capable devices. *D May 30, 2017 SHEA Updated logo and copyright information PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 17

18 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

1. Introduction PSoC 4 is a programmable embedded system controller with an ARM Cortex -M0 CPU. It combines programmable analog, programmable interconnect, user-programmable digital logic, and commonly used fixed-function peripherals with a highperformance ARM Cortex-M0 subsystem. The PSoC 4xxx-BL family is based on the PSoC 4 architecture which supports Bluetooth. This is upward-compatible with larger members of PSoC 4. PSoC 4 devices have these characteristics: High-performance, 32-bit single-cycle Cortex-M0 CPU core BLE radio and subsystem On-chip BLE transceiver Link layer controller compliant with Bluetooth 4.2 Fixed-function and configurable digital blocks Programmable digital logic High-performance analog system Flexible and programmable interconnect Capacitive touch sensing (CapSense ) Low-power operating modes Sleep, Deep-Sleep, Hibernate, and Stop modes Direct memory access (DMA) This document describes each functional block of the PSoC device in detail. This information will help designers to create system-level designs. 1.1 Top Level Architecture Figure 1-1 shows the major components of the PSoC 41x7-BL4xx architecture and Figure 1-2 shows the major components of the PSoC 42x7-BL4xx architecture. Figure 1-3 shows the major components of the PSoC 41x8-BL4xx architecture and Figure 1-4 shows the major components of the PSoC 42x8-BL4xx architecture. Figure 1-5 shows the major components of the PSoC 41x8-BL5xx architecture and Figure 1-6 shows the same for PSoC 42x8-BL5xx architecture. PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 19

Introduction Figure 1-1. PSoC 41x7-BL4xx Family Block Diagram PSoC 41x7-BL 32-bit AHB-Lite System Resources Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches CPU & Memory Peripherals PCLK SWD/TC Cortex M0 24 MHz FAST MUL NVIC, IRQMX SPCIF FLASH 128 kb Read Accelerator SRAM 16 kb SRAM Controller System Interconnect (Single Layer AHB) ROM 8 kb ROM Controller Peripheral Interconnect (MMIO) Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test DFT Logic DFT Analog IOSS GPIO (5x ports) Programmable Analog SMX x1 SAR ADC (12-bit) CTBm x1 2x OpAmp 4x TCPWM CapSense 2x SCB-I2C/SPI/UART LCD 2x LP Comparator Port Interface & Digital System Interconnect (DSI) Bluetooth Low Energy Subsystem BLE Baseband Peripheral 1KB SRAM GFSK Modem 2.4 GHz GFSK Radio 24MHz XO 32kHz XO LDO IO: Antenna/Power/Crystal Active/Sleep Deep Sleep Hibernate High Speed I/O Matrix 36x GPIOs IO Subsystem 20 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

Introduction Figure 1-2. PSoC 42x7-BL4xx Family Block Diagram PSoC 42x7-BL 32-bit AHB-Lite System Resources Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches CPU & Memory Peripherals PCLK SWD/TC Cortex M0 48 MHz FAST MUL NVIC, IRQMX SPCIF FLASH 128 kb Read Accelerator SRAM 16 kb SRAM Controller System Interconnect (Single Layer AHB) ROM 8 kb ROM Controller Peripheral Interconnect (MMIO) Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test DFT Logic DFT Analog IOSS GPIO (5x ports) Programmable Analog SMX x1 SAR ADC (12-bit) CTBm x2 2x OpAmp Programmable Digital UDB... x4 UDB 4x TCPWM CapSense 2x SCB-I2C/SPI/UART LCD Port Interface & Digital System Interconnect (DSI) 2x LP Comparator Bluetooth Low Energy Subsystem BLE Baseband Peripheral 1KB SRAM GFSK Modem 2.4 GHz GFSK Radio 24MHz XO 32kHz XO LDO IO: Antenna/Power/Crystal Active/Sleep Deep Sleep Hibernate High Speed I/O Matrix 36x GPIOs IO Subsystem PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 21

Introduction Figure 1-3. PSoC 41x8-BL4xx Family Block Diagram PSoC 41x8-BL 32-bit AHB-Lite System Resources Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches CPU & Memory Peripherals PCLK SWD/TC Cortex M0 24 MHz FAST MUL NVIC, IRQMX SPCIF FLASH 256 kb Read Accelerator SRAM 32 kb SRAM Controller System Interconnect (Single Layer AHB) ROM 8 kb ROM Controller Peripheral Interconnect (MMIO) Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test DFT Logic DFT Analog IOSS GPIO (5x ports) Programmable Analog SMX x1 SAR ADC (12-bit) CTBm x1 2x OpAmp 4x TCPWM CapSense 2x SCB-I2C/SPI/UART LCD 2x LP Comparator Port Interface & Digital System Interconnect (DSI) Bluetooth Low Energy Subsystem BLE Baseband Peripheral 1KB SRAM GFSK Modem 2.4 GHz GFSK Radio 24MHz XO 32kHz XO LDO IO: Antenna/Power/Crystal Active/Sleep Deep Sleep Hibernate High Speed I/O Matrix 36x GPIOs IO Subsystem 22 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

Introduction Figure 1-4. PSoC 42x8-BL4xx Family Block Diagram PSoC 42x8-BL 32-bit AHB-Lite System Resources Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches CPU & Memory Peripherals PCLK SWD/TC Cortex M0 48 MHz FAST MUL NVIC, IRQMX SPCIF FLASH 256 kb Read Accelerator SRAM 32 kb SRAM Controller System Interconnect (Single Layer AHB) ROM 8 kb ROM Controller Peripheral Interconnect (MMIO) Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test DFT Logic DFT Analog IOSS GPIO (5x ports) Programmable Analog SMX x1 SAR ADC (12-bit) CTBm x2 2x OpAmp Programmable Digital UDB... x4 UDB 4x TCPWM CapSense 2x SCB-I2C/SPI/UART LCD Port Interface & Digital System Interconnect (DSI) 2x LP Comparator Bluetooth Low Energy Subsystem BLE Baseband Peripheral 1KB SRAM GFSK Modem 2.4 GHz GFSK Radio 24MHz XO 32kHz XO LDO IO: Antenna/Power/Crystal Active/Sleep Deep Sleep Hibernate High Speed I/O Matrix 36x GPIOs IO Subsystem PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 23

Introduction Figure 1-5. PSoC 41x8-BL5xx Family Block Diagram CPU Subsystem PSoC 41x8-BL5xx 32-bit AHB-Lite SWD/TC FAST MUL NVIC, IRQMUX SPCIF Read Accelerator SRAM Controller ROM Controller Initiator/MMIO System Resources Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches PCLK System Interconnect (Multi Layer AHB) Peripheral Interconnect (MMIO) Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test Digital DFT Analog DFT Programmable Analog SAR ADC (12-bit) SARMUX x1 CTBm x1 2x OpAmp Port Interface & Digital System Interconnect (DSI) Bluetooth Low Energy Subsystem BLE Baseband Peripheral 1KB SRAM GFSK Modem 2.4 GHz GFSK Radio 24MHz XO 32kHz XO LDO I/O: Antenna/Power/Crystal Power Modes Active/Sleep DeepSleep Hibernate IO Subsystem 24 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

Introduction Figure 1-6. PSoC 42x8-BL5xx Family Block Diagram CPU Subsystem PSoC 42x8-BL5xx 32-bit AHB-Lite SWD/TC FAST MUL NVIC, IRQMUX SPCIF Read Accelerator SRAM Controller ROM Controller Initiator/MMIO System Resources Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches System Interconnect (Multi Layer AHB) PCLK Peripheral Interconnect (MMIO) Clock Clock Control WDT IMO ILO Reset Reset Control XRES Test Digital DFT Analog DFT Programmable Analog SAR ADC (12-bit) SARMUX x1 CTBm x2 2x OpAmp Programmable Digital UDB... x4 UDB Port Interface & Digital System Interconnect (DSI) Bluetooth Low Energy Subsystem BLE Baseband Peripheral 1KB SRAM GFSK Modem 2.4 GHz GFSK Radio 24MHz XO 32kHz XO LDO I/O: Antenna/Power/Crystal Power Modes Active/Sleep DeepSleep Hibernate IO Subsystem 1.2 Features The PSoC 4xxx-BL family has these major components: BLE radio and subsystem 32-bit Cortex-M0 CPU with single-cycle multiply, delivering up to 43 DMIPS at 48 MHz Up to 256 KB flash and 32 KB SRAM Direct memory access (DMA) Four independent center-aligned pulse-width modulators (PWMs) with complementary, dead-band programmable outputs Twelve-bit SAR ADC (with a sampling rate of 1 Msps in PSoC 42xx-BL and 806 ksps in PSoC 41xx-BL) with hardware sequencing for multiple channels Up to four opamps that can be used for analog signal conditioning and as a comparator Two low-power comparators Two serial communication blocks (SCB) that can work as SPI, UART, I 2 C, and local interconnect network (LIN) slave serial communication channels Up to four programmable logic blocks, known as universal digital blocks (UDBs) CapSense Segment LCD direct drive Low-power operating modes: Sleep, Deep-Sleep, Hibernate, and Stop Programming and debugging system through serial wire debug (SWD) Fully supported by PSoC Creator IDE tool 1.3 CPU System 1.3.1 Processor The heart of the PSoC 4 is a 32-bit Cortex-M0 CPU core running up to 48 MHz for PSoC 42xx-BL and 24 MHz for PSoC 41xx-BL. It is optimized for low-power operation with extensive clock gating. It uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. This instruction set enables fully compatible binary upward migration of the code to higher performance processors such as Cortex M3 and M4. The CPU has a hardware multiplier that provides a 32-bit result in one cycle. PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 25

Introduction 1.3.2 Interrupt Controller The CPU subsystem includes a nested vectored interrupt controller (NVIC) with 32 interrupt inputs and a wakeup interrupt controller (WIC), which can wake the processor from Deep-Sleep mode. The Cortex-M0 CPU of PSoC 4 implements a non-maskable interrupt (NMI) input, which can be tied to digital routing for general-purpose use. 1.3.3 Direct Memory Access The DMA engine is capable of independent data transfers anywhere within the memory map (peripheral-to-peripheral and peripheral-to/from-memory) with a programmable descriptor chain. Note: DMA is available only in PSoC 41x8-BL5xx and PSoC 42x8-BL5xx families. 1.4 Memory The PSoC 4 memory subsystem consists of flash and SRAM. A supervisory ROM, containing boot and configuration routines, is also present. 1.4.1 Flash The PSoC 4 has a flash module, with a flash accelerator tightly coupled to the CPU, to improve average access times from the flash block. The flash accelerator delivers 85 percent of single-cycle SRAM access performance on an average. 1.4.2 SRAM The PSoC 4 provides SRAM, which is retained during Hibernate mode. 1.5 System-Wide Resources 1.5.1 Clocking System The clocking system for the PSoC 4 device consists of the internal main oscillator (IMO) and internal low-speed oscillator (ILO) as internal clocks and has provision for an external clock, external crystal oscillator (ECO), and watch crystal oscillator (WCO). The IMO with an accuracy of ±2 percent is the primary source of internal clocking in the device. Multiple clock derivatives are generated from the main clock frequency to meet various application needs. The ILO is a low-power, less accurate oscillator and is used as a source for LFCLK, to generate clocks for peripheral operation in Deep-Sleep mode. Its clock frequency is 32 khz with ±60 percent accuracy. An external clock source ranging from 0 MHz to 48 MHz can be used to generate the clock derivatives for the functional blocks instead of the IMO. The ECO is used to generate a highly accurate 24-MHz clock without any external components. It is primarily used to clock the BLE subsystem, which contains the Link Layer engine, the digital PHY modem, and the RF transceiver. The high-accuracy ECO clock can also be used as a clock source for the PSoC 4 device. The WCO is used as a source for LFCLK. WCO is used to accurately maintain the time interval of advertising events and connection events during Deep Sleep mode. Similar to the ILO, WCO is also available in all modes, except Hibernate and Stop modes. 1.5.2 Power System The PSoC 4 operates with a single external supply in the range 1.71 V to 5.5 V. PSoC 4 has four low-power modes Sleep, Deep-Sleep, Hibernate, and Stop in addition to the default Active mode. In Active mode, the CPU runs with all the logic powered. In Sleep mode, the CPU is powered off with all other peripherals functional. In Deep-Sleep mode, the CPU, SRAM, and high-speed logic are in retention; the main system clock is OFF while the low-frequency clock is ON and the low-frequency peripherals are in operation. In Hibernate mode, even the low-frequency clock is OFF and low-frequency peripherals stop operating. Multiple internal regulators are available in the system to support power supply schemes in different power modes. 1.5.3 GPIO Every GPIO in PSoC 4 has the following characteristics: Eight drive strength modes Individual control of input and output disables Hold mode for latching previous state Selectable slew rates Interrupt generation edge triggered CapSense and LCD drive support PSoC 4 also has two over-voltage tolerant ports, which enable I2C Fast Mode power down specification compliance and have the ability to connect to higher voltage buses while operating at lower V DD. The pins are organized in a port that is 8-bit wide. A highspeed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Pin locations for fixedfunction peripherals are also fixed. 26 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

Introduction 1.6 Bluetooth Low-Energy Subsystem PSoC 4xxx Bluetooth Low-Energy (BLE) subsystem integrates the RF transceiver, digital PHY modem, and link layer controller. 1.6.1 RF Transceiver The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50-ohm antenna via a matching/filtering network. In the receive direction, this block converts the RF signal from the antenna to a 1-MHz intermediate frequency and digitizes the analog signal to 10- bit digital signal. In the transmit direction, this block takes 1 Mbps GFSK modulated from digital PHY, up-converts it to radio frequency, and transmit it to air through antenna. 1.6.2 Digital PHY Modem In the transmit direction, this sub-block takes the 1-Mbps serial data from the link layer controller, generates GFSK direct modulated data, and sends it to the BLE analog section. On the receive side, it takes the 1-MHz IF ADC data from the BLE analog section and uses digital demodulator to generate the 1-Mbps serial data. 1.6.3 Link Layer Controller The link layer controller implements all timing critical functions specified in the Bluetooth Low-Energy Link Layer specifications (packet framing/de-framing, CRC generation/ checking, encryption/decryption, state machines, and packet transmission); it also provides interface to the digital PHY. The communication between link layer hardware and firmware is done through interrupt, FIFO, and registers. 1.7 Programmable Digital The PSoC 42xx-BL has up to four UDBs. Each UDB contains structured data-path logic and uncommitted PLD logic with flexible interconnect. The UDB array provides a switched routing fabric called the digital signal interconnect (DSI). The DSI allows routing of signals from peripherals and ports to and within the UDBs. The UDB arrays in PSoC 42xx-BL enable custom logic or additional timers/pwms and communication interfaces such as I 2 C, SPI, I2S, and UART. Note PSoC 41xx-BL does not have UDBs. 1.8 Fixed-Function Digital 1.8.1 Timer/Counter/PWM Block The Timer/Counter/PWM block consists of four 16-bit counters with user-programmable period length. The functionality of these counters can be synchronized. Each block has a capture register, period register, and compare register. The block supports complementary, dead-band programmable outputs. It also has a kill input to force outputs to a predetermined state. Other features of the block include centeraligned PWM, clock prescaling, pseudo random PWM, and quadrature decoding. 1.8.2 Serial Communication Blocks The device has two SCBs. Each SCB can implement a serial communication interface as I 2 C, UART, local interconnect network (LIN) slave, or SPI. The features of each SCB include: Standard I 2 C multi-master and slave function Standard SPI master and slave function with Motorola, Texas Instruments, and National (MicroWire) mode Standard UART transmitter and receiver function with SmartCard reader (ISO7816), IrDA protocol, and LIN Standard LIN slave with LIN v1.3 and LIN v2.1/2.2 specification compliance EZ function mode support for SPI and I 2 C with 32-byte buffer 1.9 Analog System 1.9.1 SAR ADC PSoC 42xx-BL has a configurable 12-bit 1-Msps SAR ADC and PSoC 41xx-BL has a similar 12-bit SAR ADC with 806 ksps. The ADC provides three internal voltage references (V DDA, V DDA /2, and V REF ) and an external reference through a GPIO pin. The SAR hardware sequencer is available, which scans multiple channels without CPU intervention. 1.9.2 Continuous Time Block mini The Continuous Time Block mini (CTBm) provides continuous time functionality at the entry and exit points of the analog subsystem. The CTBm has two highly configurable and high-performance opamps with a switch routing matrix. The opamps can also work in comparator mode. PSoC 42xx-BL has two such CTBm blocks, while PSoC 41xx-BL has one CTBm block. The block allows open-loop opamp, linear buffer, and comparator functions to be performed without external components. PGAs, voltage buffers, filters, and trans-impedance amplifiers can be realized with external components.ctbm block can work in Active, Sleep, and Deep-Sleep modes. 1.9.3 Low-Power Comparators The PSoC 4xxx-BL has a pair of low-power comparators, which can operate in all device power modes. This functionality allows the CPU and other system blocks to be disabled PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 27

Introduction while retaining the ability to monitor external voltage levels during low-power modes. Two input voltages can both come from pins, or one from an internal signal through the AMUX- BUS. 1.10 Special Function Peripherals 1.10.1 LCD Segment Drive The PSoC 4 has an LCD controller, which can drive up to four commons and every GPIO can be configured to drive common or segment. It uses full digital methods (digital correlation and PWM) to drive the LCD segments, and does not require generation of internal LCD voltages. 1.10.2 CapSense PSoC 4 devices have the CapSense feature, which allows you to use the capacitive properties of your fingers to toggle buttons and sliders. CapSense functionality is supported on all GPIO pins in PSoC 4 through a CapSense Sigma-Delta (CSD) block. The CSD also provides waterproofing capability. 1.10.2.1 IDACs and Comparator The CapSense block has two IDACs and a comparator with a 12-V reference, which can be used for general purposes, if CapSense is not used. 1.11 Program and Debug PSoC 4 devices support programming and debugging features of the device via the on-chip SWD interface. The PSoC Creator IDE provides fully integrated programming and debugging support. The SWD interface is also fully compatible with industry standard third-party tools. 1.12 Device Feature Summary Table 1-1 shows the PSoC 41xx-BL/42xx-BL device summary. Table 1-1. PSoC 41xx-BL/42xx-BL Device Summary Feature PSoC 41xx-BL PSoC 42xx-BL Maximum CPU Frequency 24 MHz 48 MHz Flash PSoC 41x7-BL: 128 KB PSoC 42x7-BL: 128 KB PSoC 41x8-BL: 256 KB PSoC 42x8-BL: 256 KB SRAM PSoC 41x7-BL: 16 KB PSoC 42x7-BL: 16 KB PSoC 41x8-BL: 32 KB PSoC 42x8-BL: 32 KB GPIOs (maximum) 38 38 CapSense Available Available LCD Driver Available Available Timer, Counter, PWM (TCPWM) 4 4 Serial Communication Block (SCB) 2 2 Universal Digital Block (UDB) Not Available 4 IDAC (part of CapSense) 2 2 Opamp 2 4 Comparator 2 2 ADC 12-bit SAR, 806 ksps 12-bit SAR, 1 Msps Bluetooth Available Available 28 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

2. Getting Started 2.1 Support Free support for PSoC 4 products is available online at www.cypress.com/psoc4. Resources include training seminars, discussion forums, application notes, PSoC consultants, CRM technical support email, knowledge base, and application support engineers. For application assistance, visit www.cypress.com/support/ or call 1-800-541-4736. 2.2 Product Upgrades Cypress provides scheduled upgrades and version enhancements for PSoC Creator free of charge. Upgrades are available from your distributor on DVD-ROM; you can also download them directly from www.cypress.com/psoccreator. Critical updates to system documentation are also provided in the Documentation section. 2.3 Development Kits The Cypress Online Store contains development kits, C compilers, and the accessories you need to successfully develop PSoC 4 BLE projects. Visit the Cypress Online Store website at www.cypress.com/cypress-store. Under Products, click Programmable System-on-Chip to view a list of available items. Development kits are also available from Digi-Key, Avnet, Arrow, and Future. 2.4 Application Notes Refer to application note AN91267 - Getting Started with PSoC 4 BLE for additional information on PSoC 4 BLE device capabilities and to quickly create a simple BLE application using PSoC Creator and BLE development kit. PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 29

Getting Started 30 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D

3. Document Construction This document includes the following sections: Section B: CPU System on page 35 Section C: System Resources Subsystem (SRSS) on page 67 Section D: Digital System on page 117 Section E: Analog System on page 245 Section F: Program and Debug on page 325 3.1 Major Sections For ease of use, information is organized into sections and chapters that are divided according to device functionality. Section Presents the top-level architecture, how to get started, and conventions and overview information of the product. Chapter Presents the chapters specific to an individual aspect of the section topic. These are the detailed implementation and use information for some aspect of the integrated circuit. Glossary Defines the specialized terminology used in this technical reference manual (TRM). Glossary terms are presented in bold, italic font throughout. Registers Technical Reference Manual Supplies all device register details summarized in the technical reference manual. This is an additional document. 3.2 Documentation Conventions This document uses only four distinguishing font types, besides those found in the headings. The first is the use of italics when referencing a document title or file name. The second is the use of bold italics when referencing a term described in the Glossary of this document. The third is the use of Times New Roman font, distinguishing equation examples. The fourth is the use of Courier New font, distinguishing code examples. 3.2.1 Register Conventions Register conventions are detailed in the PSoC 4100-BL/4200-BL Family: PSoC 4 BLE Registers TRM. 3.2.2 Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase h (for example, 14h or 3Ah ) and hexadecimal numbers may also be represented by a 0x prefix, the C coding convention. Binary numbers have an appended lowercase b (for example, 01010100b or 01000011b ). Numbers not indicated by an h or b are decimal. PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D 31

Document Construction 3.2.3 Units of Measure This table lists the units of measure used in this document. Table 3-1. Units of Measure Abbreviation Unit of Measure bps bits per second C degrees Celsius db decibels dbm decibels-milliwatts ff femtofarads G Giga Hz Hertz k kilo, 1000 K kilo, 2^10 KB 1024 bytes, or approximately one thousand bytes Kbit 1024 bits khz kilohertz (32.000) k kilohms MHz megahertz M megaohms µa microamperes µf microfarads µs microseconds µv microvolts µvrms microvolts root-mean-square ma milliamperes ms milliseconds mv millivolts na nanoamperes ns nanoseconds nv nanovolts ohms pf picofarads pp peak-to-peak ppm parts per million SPS samples per second sigma: one standard deviation V volts 3.2.4 Acronyms This table lists the acronyms used in this document Table 3-2. Acronyms Acronym Definition ABUS analog output bus AC alternating current ADC analog-to-digital converter ADV advertising Table 3-2. Acronyms (continued) Acronym AES AHB API APOR BC BLE BLESS BOD BOM BR BRA BRQ CAN CI CMP CO CPU CRC CSD CT CTB CTBm DAC DAP DC DI DMA DNL DO DSI DSM DW ECO EEPROM EMIF FB FIFO FSR GAP GATT GFSK GPIO HCI HFCLK HSIOM Definition Advanced Encryption Standard AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus application programming interface analog power-on reset broadcast clock Bluetooth Low Energy (Bluetooth Smart) BLE subsystem brownout detect bill of materials bit rate bus request acknowledge bus request controller area network carry in compare carry out central processing unit cyclic redundancy check CapSense sigma delta continuous time continuous time block continuous time block mini digital-to-analog converter debug access port direct current digital or data input direct memory access differential nonlinearity digital or data output digital signal interface deep-sleep mode data wire external crystal oscillator electrically erasable programmable read only memory external memory interface feedback first in first out full scale range generic access profile generic attribute profile Gaussian frequency-shift keying general purpose I/O host-controller interface (BLE stack) high-frequency clock high-speed I/O matrix 32 PSoC 41XX_BLE/42XX_BLE Family PSoC 4 BLE Architecture TRM, Document No. 001-92738 Rev. *D