Easy Multicore Programming using MAPS Jeronimo Castrillon, Maximilian Odendahl Multicore Challenge Conference 2012 September 24 th, 2012 Institute for Communication Technologies and Embedded Systems
Outline Motivation MAPS Highlights Demo Introduction Summary 2
MPSoCs and the Productivity Gap Multi-Processor Systems on Chip are a reality Increased HW and SW complexity SoC Consumer Portable Design Complexity Trends (ITRS 2007) Fujitsu, MPSOC 2009 The productivity gap: Requirements double every 10 months, HW/SW productivity every 2 years (Ecker, Mueller, Doemer, 2008) Need better support for SW development in the MPSoC era 3
Programming: Uni-processor vs. MPSoC SW Development Cycle ARM7 Uni-processor MPSoC Sequential C Program Interconnect Memory Sequential C Program Task Partitioning ARM C Compiler Mapping/Scheduling Processor Debugging - Simulator - Hardware Code Generation Debugging - Virtual Platform and/or Hardware - Low Visibility - Parallel Debugging Time 4
Compilers and Software Productivity Lack of the compiler in the programming flow for MPSoCs largely contributes to the productivity loss Applications, Programming Models Applications, Programming Models? Compilers APIs, OS, ISA, µ-architectures APIs, OS, ISA, µ-architectures Manual Process APIs, OS, ISA, µ-architectures APIs, OS, ISA, µ-architectures New tasks exposed to programmer, e.g., mapping and scheduling, with non-functional constraints, e.g., real time 5
Outline Motivation MAPS Highlights Demo Introduction Summary 6
Overview of MAPS a Multicore Compiler Features/Highlights Compilation framework for multi-core systems (heterogeneous or homogeneous) for SW developers Light-weight C extension for parallel programming C-based source-to-source translation to leverage the existing C compiler technology for multi-core processing elements Retargetability towards different multi-core platforms Sequential C partitioning facilities Advanced scheduling and mapping of single and multiple parallel applications Collaborative in working with state-of-the-art ESL (Electronic System Level) design tools and other silicon vendor SW tools 7
Programming Models Parallel Programming Models have evolved for long. Yet there is no winner. Thoughts on Programming Model Needs to be leveraged by compiler for code generation (correctness). Needs to have good properties for optimizations such as parallelism extraction and intelligent mapping/scheduling (efficiency). Programming Model Practical considerations Domain-specific: embedded systems (wireless, multimedia, etc.) C dominance is unchallenged. (not addressed in this talk) 8
Parallel Dataflow Programming Process Networks (PN) Processes Independent threads of execution Communication via channels Channels Unidirectional first-in first-out Kahn Process Networks (KPN) Blocking read semantics PN KPN SDF Example: Run Length En/Decoding (RLE/D) STOP RLE is a simple data compression technique used in e.g. fax machines. Data are encoded as {count, data_value}. RLD is the inverse. RLE example: AAAABBCCCCCDDD 4A2B5C3D RLD {4, A} {A, A, A, A} {2, B} {B, B} 9
Mapping and Scheduling Flow Arch. Model Application Constraints & Config Architecture model for retargetability Parsing, profiling, tracing, sequential performance estimation Tracing to handle KPN expressiveness M&S heuristics & Trace replay Code Generation Heuristics for mapping both computation and communication (real-time aware) RISC1 DSP1 DSP2 Code generation for productivity boost RISC2 HW DSP3 10
Mapping and Scheduling Process Application tracing: Graph representation & DAG mapping algorithms ([IEEE Trans. Industrial Informatics 2011, DAC 2012]) To PEx To MEMy 11
MAPS Backends Application spec. C/CPN Applications, Programming Models? MAPS Compiler Compiler infrastructure: Source-to-Source based Manual on Clang: Retain original code structure Process Transformations at the AST level (Abstract Syntax APIs, OS, APIs, OS, APIs, OS, Tree): Flexible, extensible, retagetable ISA, ISA, ISA, µ-architectures µ-architectures µ-architectures Configuration files (scripts, makefiles): Ready to deploy solution to the target platform SW Functional Verification: (Pthreads, Synopsys MCO) Virtual Platforms: (Synopsys PA + Debug scripts) Actual HW: (TI OMAP/Multi-core DSP families and other MPSoCs) 12
Outline Motivation MAPS Highlights Demo Introduction Summary 13
MAPS Tool Demonstration Presentation of MAPS IDE Analysis and mapping of a radar application for the TI- C6678 platform (Keystone architecture) KPN Profiling (computation and communication) KPN Mapping and Scheduling (iterative, manual/automatic, constrained) 14
Outline Motivation MAPS Highlights Demo Introduction Summary 15
Summary Today s software and hardware complexity requires powerful new tools Example: Single-processor compilers MAPS: An MPSoC compiler C + Abstract programming model Automatic mapping and scheduling flow Robust code generation for state-of-the-art MPSoCs Looking forwards to seeing you during the demo session! 16
Thank you Institute for Communication Technologies and Embedded Systems 17