Logic Circuits II ECE 2411 Thursday 4:45pm-7:20pm. Lecture 3

Logic Circuits II ECE 2411 Thursday 4:45pm-7:20pm Lecture 3

Lecture 3 Topics Covered: Chapter 4 Discuss Sequential logic Verilog Coding Introduce Sequential coding Further review of Combinational Verilog Coding

Chapter 4 Combinational Circuit Combinational circuits have no feedback paths or memory elements Asynchronous signal propagation governed only by intrinsic (gate and interconnect) delay

Sequential Circuit Chapter 5 A circuit who s state is specified by a time sequence of inputs, outputs and internal states Can be asynchronous but not widely used Synchronous signal propagation synchronized to Clock: periodic train of pulses.

Synchronous Logic Storage Elements Latch Level sensitive always @(clk) Transparent when trigger event true Output = Input Synthesis tools don t work well with latches Smaller than Flip Flops Faster than Flip Flops Used as SRAM memory cell (though not the ones covered in the book) Building blocks for Flip flops

Synchronous Logic Latch SR Latch Consists of either two cross coupled NOR or two cross coupled NAND gates Must have inversion, thus cross coupled OR/AND won t work. NOR SR Latch SET/RESET active high NAND SR Latch SET/RESET active low Sometime referred to as S R latch

SR NOR Latch `timescale 1ns/10ps NOR1 NOR2 module sr_nor(input S, R, output Q, Qb); parameter dly = 0; nor #dly NOR1(Q, R, Qb); nor #dly NOR2(Qb,S, Q); endmodule // sr_nor // Testbench for sr_nor module sr_nor_tb(); reg S = 0, R = 0; wire Q, Qb; // Instantiate sr_nor sr_nor #(.dly(1.1)) U1 (S, R, Q, Qb); // Stimulus initial begin #5 S = 1; #5 S = 0; #5 R = 1; #5 S = 1; #5 $stop; end endmodule // sr_nor_tb

SR NOR Latch

Synchronous Logic D Latch Eliminates the illegal SR state S = R = 1 with CC NORs S = R = 0 with CC NANDs

Synchronous Logic D Latch `timescale 1ns/10ps // Testbench for d_latch module d_latch_tb(); reg D = 0, En = 0; wire Q, Qb; module d_latch (input D, En, output Q, Qb); parameter dly = 0; wire S, R, Db; assign #dly S =!(D & En); assign #dly R =!(Db & En); assign #dly Db =!D; assign #dly Q =!(S & Qb); assign #dly Qb =!(R & Q); endmodule // d_latch // Instantiate sr_nor d_latch U1 (.D(D),.En(En),.Q(Q),.Qb(Qb)); // Stimulus initial begin #10 D = 1; #10 D = 0; #10 En = 1; #10 D = 1; #10 D = 0; #10 D = 1; #10 En = 0; #10 D = 0; #10 $stop; end endmodule // d_latch_tb

Synchronous Logic Storage Elements Edge sensitive always @(posedge clk) Always @(negedge clk) Input is transferred to output only on control signal transition Synthesis tools can time edge triggered logic.

D Flip Flop D (Data or Delay) Flip Flop (DFF) Most widely used

D Flip Flop module d_latch (input D, En, output Q, Qb); parameter dly = 0; wire S, R, Db; assign #dly S =!(D & En); assign #dly R =!(Db & En); assign #dly Db =!D; assign #dly Q =!(S & Qb); assign #dly Qb =!(R & Q); endmodule // d_latch module d_flipflop (input D, Clk, output Q, Qb); wire Y; wire Clkb; // Invert Clk assign Clkb =!Clk; // Instantiate master d_latch master (.D(D),.En(Clk),.Q(Y),.Qb()); // Instantiate slave d_latch slave (.D(Y),.En(Clkb),.Q(Q),.Qb(Qb)); endmodule // d_flipflop `timescale 1ns/10ps // Testbench for d_latch module d_flipflop_tb(); reg D = 0, Clk = 0; wire Q, Qb; // Instantiate sr_nor d_flipflop U1 (.D(D),.Clk(Clk),.Q(Q),.Qb(Qb)); always #10 Clk =!Clk; // Stimulus initial begin @(posedge Clk); @(posedge Clk) D = 1; @(posedge Clk); @(posedge Clk) D = 0; #5 D = 1; #10 $stop; end endmodule // d_flipflop_tb

D Flip Flop

FlipFlop Exercise Using a D-type flip flop create a toggle flip flop. Hint: A toggle or T Flip-flop inverts the output if the input T is asserted, holding the value otherwise. Chapter 3 Copyright 2012 G. Tumbush v2.3 17

Setup and Hold Time Setup time is the time before the active edge of the that the data must remain stable clk t setup D D 0 D 1 D Q clk Hold time is the time after the active edge of the that the data must remain stable t clk hold D D 0 D 1 D Q clk Chapter 3 Copyright 2012 G. Tumbush v2.3 19

Meeting Setup Time FF A D Q clk t comb Combinatorial Logic FF B D Q clk t clk-q t comb t setup clk t period Q A Q 0 Q 1 D B D 0 D 1 t period t t t clk q comb setup Chapter 3 Copyright 2012 G. Tumbush v2.3 21

Setup/hold Exercise For the following circuit determine: 1. If it meets hold time and if so by what margin 2. The fastest frequency the circuit can be operated at 3. How would one determine if setup is the cause of a problem? D Q clk D Q clk t clk-q = 1ns t comb = 0.5ns t hold = 1.2ns t setup =1.0ns t comb t clk q t hold t period t clk q t comb t setup 1) tcomb + tclk-q = 0.5 + 1.2 = 1.7 > 1.2, so exceeds by 0.5nS 2) tclk-q + tcomb + tsetup = 1 + 0.5 + 1 = 2.5, so fmax = 1/2.5ns = 400MHz 3) Slow the Chapter 3 Copyright 2012 G. Tumbush v2.3 23

Inverter Based Memory Element Two Inverters can form the basis for a simple memory element: Odd number of inverters used for ring oscillators:

Transmission Gate base D Flip Flop Previous design are too big for industry applications Figure 5.9 Flip Flop uses: 8 NANDs (8 * 4 = 32 transistors) 3 NOTs (3 * 2 = 6 transistors) Transmission gate Flip Flop uses 4 NOTs (4 * 2 = 8 transistors) 4 Transmission Gates (4 * 2 = 8 transistors) 38 transistors 16 transistors Q Data Q

Even Smaller T Gate Design

Characteristic Tables A characteristic table defines the logical properties that define its operation in tabular format. Q(t): present state prior to application of edge. Q(t+1): next state after edge JK next state depends on present state when J,K = 0,0 or 1,1 Q(t+1) = JQ + K Q D next state only depends on D input and is independent of present state. Q(t+1) = D

Direct Inputs Asynchronous set and/or reset inputs that force flip flop to a particular state independently of the. Used to bring storage elements to know state upon power up or put system in an initial state May reset part several times during testing FPGA flip flops initialize to zero upon programming. Asynchronously assert reset but de-assert synchronously Want all devices to come out of reset at the same time If reset released at or near active edge, flip flop output could go metastable

D Flop Flop with set/reset

Verilog Register Coding module dff_examples (input D, Clk, output Q, Qb); reg DFF_async, DFF_sync; // D Flip Flop Asychronous Reset Example always @(posedge clk or posedge reset) begin if(reset == 1) DFF_async <= 1 b0; else DFF_async <= D; end // Another D Flip Flop Asychronous Reset Example always @(posedge clk, negedge reset) begin if(!reset ) DFF_async <= 1 b0; else DFF_async <= D; end // D Flip Flop Sychronous Reset Example always @(posedge clk ) begin if(reset) DFF_async <= 1 b0; else DFF_async <= D; end

Blocking versus Non-Blocking Blocking = Executed sequentially in the order they are listed in the block of statements initial begin @(posedge clk); A = B + 1; // Executes first B = W; // Executes second C = Z W; // Executes third end Non-blocking <= Executes concurrently by evaluating the set of expressions on the right hand side and then make the left hand side assignments @(posedge clk) begin if(reset) begin A <= 8 h00; B <= 8 haa; end else begin A <= X && Y; B <= W; end end

Blocking versus Non-Blocking What about case statement? Use blocking assignments to model combinational logic within an always block always @(a or b or sel) begin : mux case (sel) 1'b0: y = a; 1'b1: y = b; default: y = 1'bx; endcase end Optional name

Decision Trees Post synthesis implementation will differ based on coding style Priority Decision Tree Parallel Decision Tree

Verilog Compiler Directives Compiler directive are preprocessing directives for macro definitions, conditional compilation of code, and file inclusion. In lecture 2, we introduce `timescale Other commonly used directives are (partial list): `define `include `ifdef `else

Verilog Compiler Directives A macro is defined using the `define directive: `define name value `define SIZE 32 reg [`SIZE-1:0] data; `define SZ(num,width) (num)*(width)-1:0 input [`SZ(32,3)] DeviceData, Differs from parameter which must be defines within module boundaries. The `include directive allows the inclusion of one file in another: `include " filename `include "Chip.vh" Note the.vh file extension. This is typically used to indicate files contains compiler directives (`defines, etc.) and not behavioral code.

Verilog Compiler Directives Conditional Compilation Code may be conditionally compiled using the `ifdef-`else- `endif preprocessor construct `ifdef DEBUG $display("in debug mode"); `else $display("in normal mode"); `endif To compile using debug mode with ModelSim: vlog +define+debug file_name.v

5.5 Analysis of Clocked Sequential Circuits A x x B A x B A A(t+1) = x(b + A) = xb + xa B(t+1) = xa y(t) = x (B + A) x

5.5 Analysis of Clocked Sequential Circuits A(t+1) = x(b + A) = xb + xa B(t+1) = xa y(t) = x (B + A) A x x B A x B A x

5.5 Analysis of Clocked Sequential Circuits

Lab 2 Write Verilog module for Figure 5.15 Write Verilog test bench for Figure 5.15 Simulate using ModelSim Show y1 and y2 waveforms for Figure 5.15 and correlate to equations in book (pg. 206) Due Sep. 29 y2 y1