Lecture 19: Arithmetic Modules 14-1
Syllabus Objectives Addition and subtraction Multiplication Division Arithmetic and logic unit 14-2
Objectives After completing this chapter, you will be able to: Describe both addition and subtraction modules Understand the principles of carry-look-ahead (CLA) adder Understand the essential ideas of parallel-prefix adders Describe the basic operations of multiplication Describe the basic operations of division Describe the designs of arithmetic-logic unit (ALU) 14-3
Syllabus Objectives Addition and subtraction Carry-look-ahead (CLA) adders Parallel-prefix adders Multiplication Division Arithmetic and logic unit 14-4
Bottleneck of Ripple-Carry Adder Bottleneck of n-bit ripple-carry adder The generation of carries Ways of carry generation carry-look-ahead (CLA) adder parallel-prefix adders: Kogge-Stone adder Brent-Kung adder others 14-5
A CLA adder Definition carry generate (gi): gi = xi yi carry propagate (pi): pi = xi yi s i = pi c i c i +1=g i + pi c i c 1 =g0 + p0 c 0 c 2 =g1 + p1 c 1 =g1 + p1 ( g 0 + p 0 c 0 ) g1 + p 1 g0 + p1 p0 g 0 14-6
A Carry-Lookahead Generator 14-7
A CLA Adder 14-8
A CLA Adder // a 4-bit CLA adder using assign statements module cla_adder_4bits(x, y, cin, sum, cout); // inputs and outputs input [3:0] x, y; input cin; output [3:0] sum; output cout; // internal wires wire p0,g0, p1,g1, p2,g2, p3,g3; wire c4, c3, c2, c1; // compute the p for each stage assign p0 = x[0] ^ y[0], p1 = x[1] ^ y[1], p2 = x[2] ^ y[2], p3 = x[3] ^ y[3]; 14-9
A CLA Adder // compute the g for each stage assign g0 = x[0] & y[0], g1 = x[1] & y[1], g2 = x[2] & y[2], g3 = x[3] & y[3]; // compute the carry for each stage assign c1 = g0 (p0 & cin), c2 = g1 (p1 & g0) (p1 & p0 & cin), c3 = g2 (p2 & g1) (p2 & p1 & g0) (p2 & p1 & p0 & cin), c4 = g3 (p3 & g2) (p3 & p2 & g1) (p3 & p2 & p1 & g0) (p3 & p2 & p1 & p0 & cin); // compute Sum assign sum[0] = p0 ^ cin, sum[1] = p1 ^ c1, sum[2] = p2 ^ c2, sum[3] = p3 ^ c3; // assign carry output assign cout = c4; endmodule 14-10
A CLA Adder --- Using generate statements // an n-bit CLA adder using generate loops module cla_adder_generate(x, y, cin, sum, cout); // inputs and outputs parameter N = 4; //define the default size input [N-1:0] x, y; input cin; output [N-1:0] sum; output cout; Virtex 2 XC2V250 FG456-6 // internal wires wire [N-1:0] p, g; wire [N:0] c; // assign input carry assign c[0] = cin; n f (MHz) LUTs 4 8 16 32 104.3 78.9 53.0 32.0 8 16 32 64 14-11
A CLA Adder --- Using generate statements genvar i; generate for (i = 0; i <N; i = i + 1) begin: pq_cla assign p[i] = x[i] ^ y[i]; assign g[i] = x[i] & y[i]; end endgenerate // compute generate and propagation generate for (i = 1; i < N+1; i = i + 1) begin: carry_cla assign c[i] = g[i-1] (p[i-1] & c[i-1]); end endgenerate // compute carry for each stage generate for (i = 0; i < N; i = i + 1) begin: sum_cla assign sum[i] = p[i] ^ c[i]; end endgenerate // compute sum assign cout = c[n]; // assign final carry 14-12
Syllabus Objectives Addition and subtraction Carry-look-ahead (CLA) adder Parallel-prefix adders Multiplication Division Arithmetic and logic unit 14-13
Parallel-Prefix Adders The prefix sums s[i,0] = xi xi-1 x1 x0 where 0 i < n From bits k to i g[ i,k ] g[ i, j 1] p[ i, j 1] g[ j,k ] p[ i,k ] pi, j 1] p[ j,k ] where 0 i < n, k j < i, 0 k < n g[i, i] =x i y i p[i, i]= xi y i 14-14
Parallel-Prefix Adders The carry of ith-bit adder c i =gi 1 + pi 1 c i 1 can be written as g[ i,0] g[ i, j 1] p[ i, j 1] g[ j,0] Define group g[i,j] and p[i,j] as a group and denoted as w[i,j] = (g[i,j], p[i,j]) 14-15
Parallel-Prefix Adders The operator in w[i,k] = w[i,j+1] w[j,k] is a binary associative operator. ci gi 1 pi 1 ci 1 g[ i,0] g[ i, j 1] p[ i, j 1] g[ j,0] 14-16
Kogge-Stone Adder 14-17
Brent-Kung Adder 14-18
Parallel-Prefix Adders An n-input Kogge-Stone parallel-prefix network a propagation delay of log2n levels a cost of nlog2n - n + 1 cells An n-input Brent-Kung parallel-prefix network a propagation delay of 2log2n - 2 levels and a cost of 2n - 2 - log2n cells 14-19
Syllabus Objectives Addition and subtraction Multiplication Shift-and-add multiplication Basic array multipliers A signed array multiplier Division Arithmetic and logic unit 14-20
Shift-and-Add Multiplication 14-21
Shift-and-Add Multiplication A sequential implementation 14-22
Syllabus Objectives Addition and subtraction Multiplication Shift-and-add multiplication Basic array multipliers A signed array multiplier Division Arithmetic and logic unit 14-23
A Basic Array Multiplier An iterative logic structure m 1 n 1 P= X Y = x i 2 y j 2 i i=0 j=0 m 1 n 1 j ( x i y j ) 2 i=0 j=0 m +n 1 i+ j = ( P k ) 2 k k =0 14-24
A Basic Unsigned Array Multiplier 14-25
An Unsigned CSA Array Multiplier 14-26
Syllabus Objectives Addition and subtraction Multiplication Shift-and-add multiplication Basic array multipliers A signed array multiplier Division Arithmetic and logic unit 14-27
A Signed Array Multiplier Let X and Y be two two s complement number m 2 X = x m 1 2m 1 + x i 2i i=0 n 2 Y = y n 1 2 n 1 + yj2j j=0 P= XY ( = x m 1 2 m 1 xi y j 2 i=0 j=0 )( + xi 2 y n 1 2 m 2 n 2 m 2 i=0 i+ j i +x m 1 y n 1 2 n 1 m+n 2 n 2 + y j2j j=0 ( ) m 2 x i y n 1 2 i=0 i+n 1 n 2 + x m 1 y j 2 j+m 1 j=0 ) 14-28
A Signed Array Multiplier 14-29
A Signed Array Multiplier 14-30
Syllabus Objectives Addition and subtraction Multiplication Division Nonrestoring division algorithm Implementations Arithmetic and logic unit 14-31
An Unsigned Non-restoring Division Algorithm 14-32
An Unsigned Non-restoring Division Algorithm 14-33
An Unsigned Nonrestoring Division Example 14-34
Syllabus Objectives Addition and subtraction Multiplication Division Nonrestoring division algorithm Implementations Arithmetic and logic unit 14-35
A Sequential Unsigned Non-restoring Division A sequential implementation 14-36
An Unsigned Array Non-restoring Divider 14-37
Syllabus Objectives Addition and subtraction Multiplication Division Arithmetic and logic unit Basic functions Implementations 14-38
Arithmetic-Logic Units Arithmetic unit addition subtraction multiplication division Logical unit AND OR NOT 14-39
Shift Operations Logical shift Logical left shift Logical right shift Arithmetic shift Arithmetic left shift Arithmetic right shift 14-40
Syllabus Objectives Addition and subtraction Multiplication Division Arithmetic and logic unit Basic functions Implementations 14-41
Arithmetic-Logic Units 14-42