ECE 486/586 Computer Architecture Lecture # 6 Spring 2015 Portland State University
Lecture Topics Instruction Set Principles Classifying Instruction Set Architectures Memory Addressing Alignment Byte Order Addressing Modes Operations in the Instruction Set Reference: Appendix A: Sections A.2, A.3, A.4, A.5
Register and Memory Operands
ISA Comparison
Memory Addressing Byte Addressing Each byte has a unique address Word Addressing Half-word: 16-bit (or 2 bytes) Word: 32-bit (or 4 bytes) Double word : 64-bit (or 8 bytes) Quad word: 128-bit (or 16 bytes)
Memory Addressing Two issues Alignment Byte order (Big Endian vs. Little Endian) Alignment specifies whether there are any boundaries for word addressing Byte order specifies how multiple bytes within a word are mapped to memory addresses
Memory Addressing Alignment Must half word, words, double words begin mod 2, mod 4, mod 8 boundaries? 160 161 162 163 164 165 166 167
Memory Addressing Alignment Or are there no alignment restrictions? 160 161 162 163 164 165 166 167
Alignment: Why Care? Non-aligned memory references may cause multiple memory accesses 160 161 162 163 164 165 166 167 First Access Second Access Consider a system in which memory reads return 4 bytes and a reference to a word spans a 4-byte boundary: two memory accesses are required Complicates memory and cache controller design Assemblers typically force alignment for efficiency
Memory Alignment
Byte Order Little Endian: The least significant byte within a word (or half word or double word) is stored in the smallest address 160 161 162 163 164 165 166 167 MSB LSB byte 1 byte 0 161 160
Byte Order Little Endian: The least significant byte within a word (or half word or double word) is stored in the smallest address Example: A word (5827A6FD) 16 is stored at address 180 in littleendian format. Show the contents of bytes 180 through 183.
Byte Order Little Endian: The least significant byte within a word (or half word or double word) is stored in the smallest address Example: A word (5827A6FD) 16 is stored at address 180 in littleendian format. Show the contents of bytes 180 through 183. Address Value 180 FD 181 A6 182 27 183 58
Byte Order Big Endian: The most significant byte within a word (or half word or double word) is stored in the smallest address 160 161 162 163 164 165 166 167 MSB LSB byte 1 byte 0 160 161
Byte Order Big Endian: The most significant byte within a word (or half word or double word) is stored in the smallest address Example: A word (5827A6FD) 16 is stored at address 180 in bigendian format. Show the contents of bytes 180 through 183.
Byte Order Big Endian: The most significant byte within a word (or half word or double word) is stored in the smallest address Example: A word (5827A6FD) 16 is stored at address 180 in bigendian format. Show the contents of bytes 180 through 183. Address Value 180 58 181 27 182 A6 183 FD
Byte Order in Real Systems Pros/Cons Often exaggerated Little Endian Character strings appear backwards in registers Intuitive when incrementing from LSB to MSB Big Endian: Motorola 68000, Sun Sparc, PDP-11 Little Endian: VAX, Intel IA32 Configurable: MIPS, ARM
Addressing Modes
Addressing Modes Addressing modes can reduce instruction counts but at a cost of added CPU design complexity and/or increase average CPI Example (usage of auto-increment mode): With auto-increment mode: Add R1, (R2)+ Without auto-increment mode Add R1, (R2) Add R2, #1
Addressing Modes Addressing modes can reduce instruction counts but at a cost of added CPU design complexity and/or increase average CPI Example (usage of displacement mode): With displacement mode: Add R4, 100(R1) Without displacement mode Add R1, #100 Add R4, (R1) Sub R1, #100
Addressing Modes Addressing modes can reduce instruction counts but at a cost of added CPU design complexity and/or increase average CPI Example (usage of displacement mode): With displacement mode: Add R4, 100(R1) Without displacement mode Add R1, #100 Add R4, (R1) Sub R1, #100 Support most frequently used addressing modes (make the common case fast)
Frequency of Addressing Modes
Displacement Values are Widely Distributed
Immediate Operand Frequency
Distribution of Immediate Values
Type and Size of Operands
Operations in the Instruction Set
Most Frequent 80x86 Instructions Most widely executed instructions are the simple operations of an instruction set Optimize the common case => make the common instructions run as fast as possible