General Purpose Processors

Transcription

1 Calcolatori Elettronici e Sistemi Operativi Specifications Device that executes a program General Purpose Processors Program list of instructions Instructions are stored in an external memory Stored program Data can be read and written from/to an external memory Universal computation approximate finite storage Execution steps Execution steps Load an instruction from memory (fetch) Understand the required operation Instruction fetch Instruction address calculation Compute Store results Instruction decoding Detect the next instruction position Not only linear instruction flow Operand address calculation Result store jumps Operand fetch Data operation Result address calculation

2 Execution steps Execution steps Instruction Fetch Load instruction (portion) from memory Instructions can have several formats and lenghts Prefetch can hide memory latency and multiple lengths issue Decode Detect if other I-fetches are needed Decode instruction fields (operands, operation) Operand address calculation Find operands position Register file Memory Address can depend on register or memory content More memory reads can be required Operand fetch Load operands from register file Load operands from memory Execution steps Instructions Data operation Perform computation through function unit Result address computation Find where result(s) must be stored Registers Memory Result store Save data Instruction address calculation Find position of the next instruction Data manipulation Operation Data transfer, Arithmetic, Logic, Shift Data type Integer Binary, Decimal (BCD) Floating point Parallelism Scalar Vectorial

3 Instructions Instructions Control flow Conditional jumps Unconditional jumps Return from function call Return from exception Exception generation Other Instruction repetition prefix Conditional execution Memory and IO access Transfer data to and from registers Other instructions can have memory references Data instruction operands Jump target Other Synchronization accesses Atomic read-modify-write Conditional storing Bus locking prefix Memory consistency model manipulation Memory and execution barriers Instructions Execution steps System management Processor mode changes Protection level Interrupt enabling/disabling Processor power state changes Memory model management Cache management System identification Special registers manipulation Instruction fetch Instruction decoding Operand and result address calculation Operand fetch Instruction address calculation Result store Data operation

4 ASM chart ASM chart RESET PC <= START_ADDR General scheme RESET PC <= START_ADDR [PC] = INSTR INSTR execution [PC] = INSTR [PC] = INSTR INSTR i i execution Unconditional jump [PC] = INSTR i Combinational: + DECODER [PC] = INSTR INSTR j j execution CONDITION Conditional jump [PC] = INSTR j CONDITION PC <=PC + disp Structure Structure PC Timing: ) dpreg dpreg 2) PC dpreg 3) PC PC PC Control Signals Control Signals Status Flags Status Flags CONTROL UNIT DATAPATH CONTROL UNIT DATAPATH

5 ASM chart Structure RESET PC <= START_ADDR IR <= [PC] IR = INSTR PC Control Signals IR = INSTR i Combinational: DECODER IR Status Flags IR = INSTR j CONDITION PC <=PC + disp CONTROL UNIT DATAPATH Structure ASM chart Timing: ) PC IR 2) dpreg dpreg 3) IR dpreg 4) IR PC PC RESET PC <= START_ADDR + incr IR <= [START_ADDR] IR <= [PC] IR = INSTR Single cycle scheme Control Signals IR IR = INSTR i Combinational: DECODER Status Flags IR = INSTR j CONDITION CONTROL UNIT DATAPATH PC <=PC + disp

6 ASM chart ASM chart RESET PC <= START_ADDR + incr IR <= [START_ADDR] Single cycle scheme with branch stall RESET PC <= START_ADDR + incr IR <= [START_ADDR] Multi-cycle scheme IR <= [PC] IR <= [PC] IR = INSTR IR = INSTR Wait state (for branches) Wait state (for branches) IR = INSTR i IR = INSTR i IR = INSTR j CONDITION PC <=PC + disp IR = INSTR j CONDITION IR = INSTR i Multi-cycle instruction PC <=PC + disp Structure Multi-cycle control Pipeline Hard-wired control Control unit FSM PC IR Control signals for Datapath, PC, IR, other special registers Memories DEC Control Signals Status signals (flags) from Pipeline registers Functional units Flag registers Memories CONTROL UNIT Status Flags DATAPATH

7 Multi-cycle control Microprogrammed Processor Microprogrammed control Branch IR Control unit microprogrammed FSM µ-instruction Control signals Datapath, PC, IR, other special registers Memories Next state info Conditions to check Addresses for next µ-instructions Status signals (flags) from PC + COMB CAR Control Store COMB2 µ-instruction Control Signals COMB3 Functional units Flag registers Memories Address generator CONTROL UNIT Status Flags DATAPATH Microprogrammed Processor Microprogramming Next state state + branch from opcode Control signals encoded vertical µp not encoded horizontal µp PC increment Simplify development Decouples HW and ISA design Control design becomes SW development Flexibility Adaptable to changes in µ-architecture, timing, technology Can make changes late in design cycle, or even in the field Can implement very powerful instruction sets just more control memory branch

8 Microprogramming Microprogramming Generality Can implement multiple instruction sets on same machine Can tailor instruction set to application Compatibility Many micro-architectures, same instruction set Costly to implement Requires a fast control memory Can tailor instruction set to application Slow Microprogramming Microprogramming Horizontal microprogram no decoding larger words ( larger control store) Vertical microprogram smaller memory need decoding Hybrid Diagonal Enhancements µ-instructions are buffered and executed out-of-order Instructions are fetched and translated in µ-instructions Translation and execution no more in lock-step µ-instructions are cached in a special cache Special instructions sequences are recognized Translated in special (optimized) µ-instructions sequences Some instructions are translated through random logic HW decoders vs Memory

9 Microprogramming CPU - interface Von Neumann Microprogrammed architectures examples IBM System/36 series (some: M3, M4, M5, M65) DEC PDP- DEC VAX- Zilog Z8 Motorola 68 Intel x86 DP INSTR/DATA CPU - interface Harvard Datapath DP Register file symmetric Rz <= Rx op Ry x, y, z, op asymmetric INSTR DATA Function Units Adder, Multiplier, Divider, Logic functions, Shifter,... cost, computational power, software complexity

10 Datapath Instruction Set Architecture Acc Reg File ALU Accumulator architecture op Rx Reg File ALU Symmetric architecture op Rd, Rs, Rs 2 Memory and registers model Size and meaning of registers General purpose registers Special purpose registers Floating Point registers How registers can be used by operations Available instructions (Instruction Set) formats, operations, data types, addressing modes Operating modes standard, protection levels, special modes ISA: operands ISA: memory access Classification by operands number 3 operands: <instr> Rd, Rs, Rs 2 Rd <= Rs op Rs 2 e.g., add R, R3, R4 Memory-to-memory Operands are fetched/stored from/in memory e.g., add M[Rd], M[Rs ], M[Rs 2 ] ; M[Rd] <= M[Rs ] + M[Rs 2 ] 2 operands: <instr> Rd, Rs e.g., add R, R3 operand: <instr> Rs e.g., add R3 operands: <instr> e.g., add Rd <= Rd op Rs acc <= acc op Rs M[TOP] <= M[TOP] op M[TOP+] use memory as a stack Load / Store Memory is only accessed by specific instructions e.g. ld R, M[R4] ; R <= M[R4] ld R2, M[R5] ; R2 <= M[R5] add R3, R, R2 ; R3 <= R + R2 st M[R6], R3 ; M[R5] <= R3

11 ISA: addressing modes ISA: addressing modes Implicit Indirect No need to indicate the operand location (is implicit) The instruction contains a memory address that is a pointer e.g., stack architectures Operand is fetched from memory (2 memory accesses) Immediate operand: [[addr]] Operand is a constant in the instruction No need for operand fetch Direct The instruction contains a memory address Operand is fetched from memory Register indirect The instruction contains register index, the register contains a pointer Operand is fetched from memory (access to register file and to memory) operand: [Rs] operand: [addr] Register Operand is in a register, the instruction indicates the register number Operand fetch is performed in register file ISA: addressing modes Endianness Indexed How is stored, in memory, the 32-bit number: x234? The instruction contains an address and a displacement Address and/or displacement can be in a register operand: [addr + REG[x]] operand: [addr + REG[x]*n] operand: [REG[a] + REG[b]*n] Easy access to vector elements or structure fields Register x234 Memory x addr x2 addr+ x3 addr+2 x4 addr+3 Big-endian: big end first (68x, SPARC, System/36, Java Virtual Machine, Internet protocols) Others post/pre increment/decrement The register containing the address is incremented/decremented before/after the access For vectors/strings scan Register x234 Memory x4 addr x3 addr+ x2 addr+2 x addr+3 Little-endian: little end first (652, x86, VAX, Alpha, ARM) Bi-endian: switchable endianness (ARM (from v3), MIPS, SPARC (from v9), Alpha (optional), PA-RISC, Power PC, SuperH)

12 Instruction Set Name Mnemonic code Format Opcode RTL description of operation Affected flags Orthogonal Instruction Set All (GP) registers can be used as operands and destinations for all of the operations Simpler SW Less stringent constraints on resources usage Not orthogonal Simpler HW Reduced wiring among registers and functional units Reduced instruction size Instruction format Memory model Opcode: operating code Data fields Fixed or Variable length Memory protection Memory areas vs Operating mode Address translation opcode inc CPU address (virtual address) opcode opcode opcode operand operand operand operand operand operand inc EAX add EAX, EBX add R, R4, R5 Memory address (physical address) Memory consistency Strong consistency, Weak consistency,... Cache management Flushing, cacheable/non-cacheable memory areas

13 Exception handling Exception External signals Reset Interrupts Not maskable interrupts Software events Memory access protection violation Not existing translation Operation Division by zero, overflow,... Trap instructions