Recap from last class Taxonomy of microprocessor architecture Von Neumann Memory for both data and instructions, single bus Easier to write Harvard Separate memories for data and instructions, two buses Higher throughput RISC vs. CISC Multiple implementations of microprocessor ARM: von Neumann + RISC SHARC: Harvard + CISC, optimized for DSP ECE 1160/2160 Embedded Systems Design 1
ECE 1160/2160 Embedded System Design CPU I/O, Interrupt, and Bus Wei Gao ECE 1160/2160 Embedded Systems Design 2
Embedding A Computer: I/O devices output analog analog actuators CPU input analog analog sensors embedded computer mem ECE 1160/2160 Embedded Systems Design 3
I/O Devices Digital interface to I/O devices Some devices have non-digital components, e.g., electronics for rotating disk and analog read/write in hard drive Devices usually use registers to talk to CPU Status: info, e.g. if the data is ready to read, 1: ready, 0: finished Data: holds data outputted to or inputted from the device CPU status register data register Device mechanism Typical I/O device ECE 1160/2160 Embedded Systems Design 4
Programming I/O Devices Two types of instructions can support I/O: 1. special-purpose I/O instructions; 2. memory-mapped load/store instructions. Intel x86 provides special in, out instructions. Separate address space for I/O devices Most CPUs use memory-mapped I/O. Registers in I/O devices have normal memory address Use CPU s normal read/write instructions to access I/O I/O instructions do not preclude memory-mapped I/O ECE 1160/2160 Embedded Systems Design 5
Peek and Poke Traditional high-level functions to implement memorymapped I/O Read: dereference a given location pointer int peek(char *location) { } return *location; Write to a certain location void poke(char *location, char newval) { (*location) = newval; } ECE 1160/2160 Embedded Systems Design 6
Busy-Wait I/O Programming Simplest way to program I/O devices. Devices are much slower than CPU and require more cycles CPU has to wait for device to finish before starting next Use peek instruction to test when device is finished CPU status register data register Device mechanism CD burner ECE 1160/2160 Embedded Systems Design 7
Busy-Wait I/O Programming //send a string to device using Busy-Wait handshaking current_char = mystring; while (*current_char!= \0 ) { //send character to device (data register) poke(out_char,*current_char); //wait for device to finish by checking its status while (peek(out_status)!= 0); //advance character pointer to next one current_char++; } test as an atomic operation CPU status register data register Device mechanism CD burner ECE 1160/2160 Embedded Systems Design 8
Simultaneous I/O using Busy-Wait Repeatedly read a character from the input device and then write it to the output device while (TRUE) { /* read a character into variable achar */ while (peek(in_status) == 0);/* wait until ready */ achar = (char)peek(in_data);/* read the character */ /* write achar to output device*/ poke(out_data,achar); poke(out_status,1); /* turn on the device */ while (peek(out_status)!= 0); /* wait until done*/ } ECE 1160/2160 Embedded Systems Design 9
Mutual Exclusion using Busy-Wait Exclusive access on the I/O device Multi-threaded systems TestAndSet() { oldvalue=peek(lock); //read poke(lock, true); //write return oldvalue; }.. //wait until LOCK is acquired while (TestAndSet()); TestAndSet for mutual exclusion //send character to device (data register) poke(out_char,*current_char); //wait for device to finish by checking its status while (peek(out_status)!= 0); //advance character pointer to next one current_char++; poke(lock, false); //release lock ECE 1160/2160 Embedded Systems Design 10
Interrupt-based I/O Busy-wait is very inefficient. CPU can t do other work while testing device. Hard to do simultaneous I/O. Interrupts allow to change the flow of control in the CPU. Call interrupt handler (i.e. device driver) to handle device. IR CPU PC interrupt request interrupt ack status register Device mechanism data/address data register ECE 1160/2160 Embedded Systems Design 11
Interrupt Behavior Based on subroutine call mechanism. Interrupt forces next instruction of CPU to be a subroutine call to the interrupt handler. Context switch: return address is saved to resume executing foreground program. CPU may not service a request immediately e.g. CPU needs to finish a disk transaction before handling a keyboard interrupt ECE 1160/2160 Embedded Systems Design 12
Interrupt Physical Interface CPU and device are connected by CPU bus. CPU and device handshake: Device asserts interrupt request; CPU asserts interrupt acknowledge when it can handle the interrupt. ECE 1160/2160 Embedded Systems Design 13
Simultaneous I/O using Interrupt void input_handler() { /*get a char and put in global*/ achar = peek(in_data); /*get a character*/ gotchar = TRUE; /*Signal to main program*/ poke(in_status,0); /*reset status for next transfer */ } Request interrupt when input comes main() { while (TRUE) { /*read then wait forever*/ if (gotchar) { /*write a character*/ poke(out_data,achar); /*put character in device*/ poke(out_status,1); /*set status to write*/ gotchar = FALSE; /*reset flag*/ } Write data as interrupt // do some other jobs here. handler } } ECE 1160/2160 Embedded Systems Design 14
Interrupt I/O with Buffers No waiting; CPU can read and write simultaneously Use a queue to store characters, producer/consumer Allow input/output devices to run at different rates a head tail tail Output device (consumer) a b c d e f g Input device (producer) head head tail ECE 1160/2160 Embedded Systems Design 15
Priorities and Vectors Need to handle interrupts from multiple devices Two mechanisms allow us to make interrupts more general: Priorities determine what interrupt gets CPU first. Vectors determine what code is called for each type of interrupt. Mechanisms are orthogonal: most CPUs provide both. ECE 1160/2160 Embedded Systems Design 16
Prioritized Interrupts Some interrupts are more important Lower-numbered interrupt lines have higher priority Re-connect lines to change priorities interrupt acknowledge device 1 device 2 device n L1 L2.. Ln CPU interrupt requests ECE 1160/2160 Embedded Systems Design 17
Interrupt Prioritization Masking: interrupt with priority lower than current priority is not recognized until current interrupt is complete. In TinyOS, event handlers should not do long processing because the priority is highest by default Use tasks because they can be preempted Highest-priority is non-maskable interrupt (NMI) which is never masked. Often used to save critical states of memory and turn off devices for power-down. ECE 1160/2160 Embedded Systems Design 18
Interrupt Vectors Flexibility: allow different devices to be handled by different handlers; mapping is changeable Devices store the vector # Interrupt vector table: :CPU :device Interrupt vector table head handler 0 handler 1 handler 2 handler 3 Vector 0 Vector 1 Vector 2 Vector 3 receive request receive vector receive ack ECE 1160/2160 Embedded Systems Design 19
Generic Interrupt Mechanism continue executing next instruction N interrupt? Y ignore N interrupt priority > current priority? ack Y bus error Y timeout? N Y vector? Y call table[vector] ECE 1160/2160 Embedded Systems Design 20
Interrupt Sequence 1. Device requests interrupt 2. CPU checks for pending interrupts and acknowledges the highest priority request. 3. Device receives acknowledge and sends CPU the interrupt vector. 4. CPU saves current states, looks up and calls the corresponding handler. 5. Handler processes request. 6. CPU restores states to foreground program. ECE 1160/2160 Embedded Systems Design 21
Interrupt Overhead Context switch: registers (e.g., PC) save/restore when handler is called. Handler execution time. Extra cycles for requests, acknowledges, vectors, etc. Other overhead Pipeline-related penalties. Cache-related penalties. ECE 1160/2160 Embedded Systems Design 22
Embedding A Computer: The CPU Bus output analog analog actuators CPU input analog analog sensors embedded computer mem ECE 1160/2160 Embedded Systems Design 23
Typical Microprocessor Bus Bus is a set of wires and a protocol for the CPU to communicate with memory and devices Five major components to support reads and writes CPU Device 1 Device 2 a n Clock Address provides is an a-bit synchronization R/W bundle is 1 of when signals to the that Data the bus transmits bus ready is reading the components and Data address signals 0 is when an for when n-bit an the the bus bundle access values is writing of on signals the that Clock data can bundle carry are data to valid R/W or from the CPU Address Data ready Data Memory ECE 1160/2160 Embedded Systems Design 24
Timing Diagrams The behavior of a bus is specified as a timing diagram A timing diagram shows how signals on a bus vary over time. Generally used for asynchronous machines with timing constraints. enq Enquiry signal time Acknowledge signal ack time ECE 1160/2160 Embedded Systems Design 25
Timing Diagram Notation Timing diagram syntax: Constant value (0/1), stable, changing, unknown. Timing constraints: minimum time between two events High (1) Rising Falling Signal A Low (0) 10 ns Signal B Changing Stable unknown Signal C Timing Constraint ECE 1160/2160 Embedded Systems Design 26
Basic Block of Most Bus Protocols: Four-Cycle Handshake 1. Device 1 raises its output to signal an enquiry 2. Device 2 raises output to signal an acknowledge 3. Device 1 and 2 can start to transmit data 4. Once transfer is complete, device 2 lowers output, signaling it finishes the data transmission 5. Device 1 lowers output Device 1 Device 2 Device 1 Device 2 ack 1 enq enq data ack 2 3 time time ECE 1160/2160 Embedded Systems Design 27 4
When Should You Handshake? When response time cannot be guaranteed in advance: Data-dependent delay. Component variations. ECE 1160/2160 Embedded Systems Design 28
Typical Bus Access Clock R/W Address enable Address Data Ready data read write time ECE 1160/2160 Embedded Systems Design 29
Bus Design Bus signals are usually tri-stated. Low, high, stable Address and data lines may be shared. Bus mastership Bus master controls operations on the bus. CPU is default bus master. Other devices may request bus mastership. Separate set of handshaking lines. CPU can t use bus when it is not master ECE 1160/2160 Embedded Systems Design 30
Summary I/O programming Memory-mapped I/O vs. special-purpose I/O instructions Busy-wait is simplest but very inefficient Devices are usually slower than CPU Interrupts Using buffer to allow input/output at different rates Priorities and vectors allow to handle multiple interrupts The CPU Bus A set of wires and protocols for CPU to communicate with memory and I/O devices. Four-cycle handshake protocol Timing diagram for typical bus access ECE 1160/2160 Embedded Systems Design 31