Using the Nios II Controller Reerence Designs AN-346-1.2 March 2009 Introduction This application note describes coniguration controller reerence designs or Nios II systems using Altera Stratix II, Cyclone II, and Cyclone III FPGAs. The note describes how to use the reerence designs with our dierent Altera development boards, provides steps to port the reerence designs to other boards, and oers suggestions or modiying the reerence designs to support more complex systems. A coniguration controller helps accomplish the ollowing tasks: Intelligently conigure FPGAs rom a lash memory device on system power-up Utilize a single lash memory device to store hardware coniguration data as well as embedded sotware instructions and data Provide lash partitions or multiple hardware images Provide a mechanism or users to reset the board to a known working hardware image Facilitate in-the-ield upgrades by responding to reconiguration requests rom a Nios II processor residing on the FPGA Many modern embedded systems use lash memory to store processor coniguration inormation and program data or the system processor. Systems also use lash memory to store FPGA hardware coniguration data. The use o lash memory or both processor memory and FPGA coniguration data typically requires an intelligent coniguration controller, particularly or systems with sot embedded processors such as the Altera Nios II processor. The Altera development boards running reerence designs discussed in this application note contain a programmable coniguration controller that provides a stable platorm or managing system coniguration and reset in embedded systems. The controller provides instant-on coniguration control enabling system coniguration or reconiguration in a minimal amount o time. Table 1 identiies the device where the coniguration controller is implemented or each solution discussed in this application note. Table 1. Controller Location Board/Kit Controller Device Nios Development Board, Stratix II Edition Altera EPM7256AE non-volatile MAX 7000 Nios Development Board, Cyclone II Edition Altera EPM7256AE non-volatile MAX 7000 Cyclone III FPGA Starter Board Altera EP3C25 Cyclone III Nios II Embedded Evaluation Kit, Cyclone III Edition Cyclone III 3C120 Development Board Altera EPM2210 non-volatile MAX II Altera Embedded System Development Kit, Cyclone III Edition For more inormation about the development boards reerenced in this application note, reer to the ollowing documents: March 2009 Altera Corporation Using the Nios II Controller Reerence Designs
Page 2 Controller or Stratix II Devices Nios Development Board Cyclone II Edition Reerence Manual Nios Development Board Stratix II Edition Reerence Manual Cyclone III FPGA Starter Board Reerence Manual Cyclone III 3C120 Development Board Reerence Manual For more inormation about the Nios II embedded processor, reer to the ollowing documents: Nios II Processor Reerence Handbook Nios II Sotware Developer's Handbook Controller or Stratix II Devices This section discusses the ollowing coniguration controller topics: Flash Images on the Nios Development Board, Stratix II Edition on page 2 Controller Boot Sequence or Stratix II Devices on page 3 Controller Hardware or Stratix II Devices on page 4 Controller Reerence Designs or Stratix II Devices on page 6 Flash Images on the Nios Development Board, Stratix II Edition The Nios Development Board, Stratix II Edition includes an Altera EPCS64 serial coniguration device as well as 8-bit wide Common Flash Interace (CFI) lash memory. The CFI lash memory on the board is partitioned into three sections (reer to Figure 1). Figure 1. Nios Development Board Flash Partition Address (hex) 0x00000000 0x10000000 0x20000000 0x30000000 0x40000000 0x50000000 0x60000000 0x70000000 CFI Flash Memory User Sotware or Data (6 MB) User Hardware Image (1MB) Sae Hardware Image (1MB) Flash Memory Allocation EPCS Flash Memory User Hardware Image User Sotware or Data Factory programmed (do not erase) Available or user data The irst section is used or general programming or data storage. The other two sections user and sae image store FPGA hardware conigurations. The user image typically contains a hardware design that is under development or testing. The sae (actory programmed) image typically contains a working, deault hardware image. Using the Nios II Controller Reerence Designs March 2009 Altera Corporation
Controller or Stratix II Devices Page 3 The EPCS64 lash memory is divided into two sections with a loating section boundary. The section boundary between the user hardware and user sotware/data sections is determined by the size o the user hardware section. The coniguration controller loads the EPCS user, CFI user, or the CFI sae image into the Stratix II device. By observing the behavior illustrated in the Figure 2 lowchart, the coniguration controller determines which image to load. Controller Boot Sequence or Stratix II Devices When the Nios Development Board, Stratix II Edition initially powers-on, the coniguration controller is idle until it detects the power-on reset. Upon detecting power-on reset, the controller attempts to load the EPCS user image into the FPGA. I coniguration o the serial user lash image is successul, the controller continually blinks the User LED, tri-states all o its lash interace pins, and remains idle until a reset, reconiguration, or sae image request is detected. I coniguration o the serial user lash image ails, the controller attempts to program the user image rom the 8-bit parallel lash into the Stratix II device. I the controller successully programs the user image into the Stratix II device, the User LED illuminates and the controller remains idle until a reset, reconiguration request, or sae image reset is detected. I coniguration o the parallel user lash image ails, the controller attempts to program the sae image rom the 8-bit lash into the Stratix II device. I the controller successully programs the sae image into the Stratix II device, the Sae LED illuminates and the controller remains idle until a reset, reconiguration, or sae image request is detected. I an error occurs while programming the sae image to the device, the controller illuminates the Error LED and remains in an error state. The controller only exits the error state when a reset or power-on reset request is detected. Figure 2 shows the coniguration controller boot sequence or Stratix II and Cyclone II devices. March 2009 Altera Corporation Using the Nios II Controller Reerence Designs
Page 4 Controller or Stratix II Devices Figure 2. Stratix II and Cyclone II Controller Boot Sequence Flowchart Power on state Power on reset detected Load user image rom serial coniguration device to FPGA successul? No Yes Reset or reconig request Blink User LED Sae conig request Reset or reconig request Light User LED Sae conig request Yes Load user image rom parallel lash to FPGA successul? No Load sae image rom parallel lash to FPGA successul? Yes Sae conig request Light Sae LED Reset or reconig request No Reset Light Error LED For more inormation about the coniguration process and the lash structure o the Nios Development Board, Stratix II Edition, reer to the Nios Development Board Stratix II Edition Reerence Manual. Controller Hardware or Stratix II Devices You can program Stratix II FPGAs in a number o dierent modes; however, when programming a Stratix II device via an external coniguration controller, Altera recommends programming the device in ast passive parallel (FPP) mode. When in FPP mode, the external coniguration controller generates a coniguration clock or the Stratix II device and presents an 8-bit coniguration data word to the Stratix II device on each coniguration clock cycle. For more inormation about the FPP coniguration capabilities o Stratix II devices, reer to the Coniguring Stratix II and Stratix II GX Devices chapter o the Stratix II Device Handbook. Using the Nios II Controller Reerence Designs March 2009 Altera Corporation
Controller or Stratix II Devices Page 5 The coniguration controller reerence design included with the Nios II Embedded Design Suite (EDS) uses an EPM7256AE device to generate the coniguration clock or the Stratix II device, as well as generate the address and control signals necessary to pull coniguration data out o lash memory. Figure 3 shows a block diagram o the coniguration controller reerence design or Stratix II devices. Figure 3. Development Board Controller or Stratix II Devices A[23..0] D[7..0] CONTROL External Flash Drive A[23..0] D[7..0] CONTROL reset_n MAX EPM7256AE Controller Flash Address and Control-Logic Generator Clock Generator Reset Distribution Logic Clock Logic Status Monitor DATA[0] EPCS64 Device DCLK CONF_DONE STATUS_n CONFIG_n CS_n ASDO Stratix II EP2S60 Reconig_request ENET RST PROTO1 RST PROTO2 RST Status LEDs Figure 3 depicts the coniguration controller as the ive conceptual sub-blocks described in the ollowing sections. Flash Address and Control Logic Generator The lash address and control logic block generates the address signals to send to the CFI lash device. The logic initiates coniguration rom either the user or actory image based on inputs rom the control logic, and then increments the CFI lash address bus until the appropriate number o coniguration bytes transer, or an error is detected. Ater a successul coniguration, the CFI lash address and control pins o the EPM7256AE device are tri-stated so that the lash can be accessed by the Nios II embedded processor running in the Stratix II device. Clock Generator The coniguration clock generator drives the DCLK input signal o the Stratix II device. The clock is derived rom the 50 MHz oscillator on the development board. The reerence design divides the oscillator by 16 to create a 3.125MHz coniguration clock. The clock is also used to time the address and control signals o the CFI lash device. March 2009 Altera Corporation Using the Nios II Controller Reerence Designs
Page 6 Controller or Cyclone II Devices Reset Distribution Logic The coniguration controller also delivers reset signals to other devices on the development board. A board level reset is issued to the Ethernet device, the lash device, and the two board-prototype headers under the ollowing conditions: A power-on reset occurs. A reconiguration request rom the processor arrives. The Force Sae button is pressed. Control Logic To control the coniguration low, the coniguration control logic monitors the various board reset sources as well as the Stratix II device coniguration status signals. This logic block drives the MSEL pins on the Stratix II device to set the coniguration mode based on the low chart shown in Figure 2 on page 4. The logic manages the loading o the user or actory images based on the status o the Stratix II devices STATUS_n and CONF_DONE signals. The coniguration control logic initiates a new coniguration i a reset_n is detected, the Force Sae button is pressed, or the Nios II processor residing in the Stratix II device issues a Reconiguration_request. Status Monitor The Nios Development Board, Stratix II Edition contains our LEDs that indicate the coniguration status o the processor. Dierent LEDs illuminate depending on which image is loaded into the Stratix II device or i an error occurs during coniguration. Controller Reerence Designs or Stratix II Devices The Nios II EDS provides a coniguration controller reerence design or the EP2S60 device. I you have installed the Nios II EDS, you can ind the source code and Quartus II project iles or the reerence design in the <Nios II EDS install path>/examples/conig_controller/niosii_stratixii_2s60_rohs directory. Table 2 provides a description o each o the source iles used in the coniguration controller design. Table 2. Stratix II Controller Files File Name conig_controller.td address_counter.td dclk_divider.td reset_counter.td Description Top-level design. Contains control logic and instantiations o the lower-level iles, namely, address_counter.td, dclk_divider.td, and reset_counter.td. Counter used to generate address bus or lash device access. Clock divider used to generate DCLK rom the board oscillator. Used to debounce reset switch inputs. Controller or Cyclone II Devices This section discusses the ollowing coniguration controller topics: Flash Image on the Nios Development Board, Cyclone II Edition on page 7 Controller Boot Sequence or Cyclone II Devices on page 7 Using the Nios II Controller Reerence Designs March 2009 Altera Corporation
Controller or Cyclone II Devices Page 7 Controller Hardware or Cyclone II Devices on page 7 Controller Reerence Designs or Cyclone II Devices on page 8 Flash Image on the Nios Development Board, Cyclone II Edition The lash image on the Nios Development Board, Cyclone II Edition also contains a user and sae (actory programmed) image in CFI lash, as well as a user hardware image in an EPCS64 serial coniguration device. Controller Boot Sequence or Cyclone II Devices When the Nios Development Board, Cyclone II Edition initially powers-on, the coniguration controller is idle until it detects the power-on reset. Upon detecting power-on reset, the controller attempts to load the EPCS user image into the FPGA. I coniguration o the serial user lash image is successul, the controller continuously blinks the User LED, tri-states all o its lash interace pins, and remains idle until a reset, reconiguration, or sae image request is detected. I coniguration o the serial user lash image ails, the controller attempts to program the user image rom the 8-bit parallel lash into the Cyclone II device. I the controller successully programs the user image into the Cyclone II device, the User LED illuminates and the controller remains idle until a reset, reconiguration request, or sae image reset is detected. I coniguration o the parallel user image ails, the controller attempts to program the sae image rom the 8-bit lash into the Cyclone II device. I the controller successully programs the sae image into the Stratix II device, the Sae LED illuminates and the controller remains idle until a reset, reconiguration, or sae image request is detected. I an error occurs while programming the sae image to the device, the controller illuminates the Error LED and remains in an error state. The controller only exits the error state when a reset or power-on reset is detected. Figure 2 on page 4 shows the coniguration controller boot sequence or Stratix II and Cyclone II devices. For more inormation about the coniguration process and the lash structure o the Nios Development Board, Cyclone II Edition, reer to the Nios Development Board Cyclone II Edition Reerence Manual. Controller Hardware or Cyclone II Devices You program Cyclone II FPGAs serially via either a download cable, a serial coniguration device, or in passive serial (PS) mode using an external coniguration controller. The coniguration controller reerence design demonstrates the lexibility o using a single CPLD as a coniguration controller or two dierent Altera device amilies. In the case o the Nios Development Board, Cyclone II Edition, the coniguration controller has been modiied to enable programming the Cyclone II device in PS mode using an 8-bit lash as the coniguration source as well as rom an Altera serial coniguration device. For more inormation about the coniguration capabilities o Cyclone II devices, reer to the Coniguring Cyclone II Devices chapter o the Cyclone II Device Handbook. March 2009 Altera Corporation Using the Nios II Controller Reerence Designs
Page 8 Controller or Cyclone II Devices The coniguration controller reerence design included with the Nios Development Board, Cyclone II Edition uses a MAX 7256AE device to generate the coniguration clock or the Cyclone II device as well as generate the address and control signals necessary to pull coniguration data out o lash memory and convert it to serial data or the Cyclone II device. Figure 4 shows a block diagram o the coniguration controller reerence design or Cyclone II devices. Figure 4. Development Board Controller or Cyclone II Devices A[23..0] D[7..0] CONTROL External Flash Drive A[23..0] D[7..0] CONTROL MAX EPM7256AE Controller Flash Address and Control-Logic Generator Flash Parallel to Serial Data Converter EPCS64 Device CSn ASD0 reset_n Clock Generator Reset Distribution Logic Clock Logic Status Monitor DATA[0] DCLK MSEL[1..0] CONF_DONE STATUS_n CONFIG_n Reconig_Request Cyclone II EP2C35 ENET RST PROTO1 RST PROTO2 RST Status LEDs The main dierences between the Cyclone II edition and Stratix II edition development board s coniguration controllers are that the Cyclone II edition includes a parallel to serial converter block and control logic block modiications. The parallel to serial block reads an 8-bit word rom the lash image every 8 DCLK cycles and shits the word out to the DATA0 input o the Cyclone II device on every DCLK cycle. Controller Reerence Designs or Cyclone II Devices The Nios II EDS provides a coniguration controller reerence design or the Cyclone II EP2C35 device. I you have installed the Nios II EDS, you can ind the source code and Quartus II project iles or the reerence designs in the <Nios II EDS install path>/examples/conig_controller/niosii_cycloneii_2c35 directory. Table 3 provides a description o each o the source iles used in the coniguration controller design. Using the Nios II Controller Reerence Designs March 2009 Altera Corporation
Controller or Cyclone III Devices Page 9 Table 3. Cyclone II Controller Files File Name conig_controller.td address_counter.td dclk_divider.td reset_counter.td data_bit_counter.td shit_register.td Description Top-level design. Contains control logic and instantiations o the lower-level iles, namely, address_counter.td, dclk_divider.td, reset_counter.td, data_bit_counter.td, shit_register.td. Counter used to generate address bus or lash access. Clock divider used to generate DCLK rom the board oscillator. Used to debounce reset switch inputs. Used to determine when a word should be loaded into the shit register. Shits a coniguration bit out to the DATA0 line each DCLK cycle. Controller or Cyclone III Devices This section discusses the ollowing coniguration controller topics: Flash Image on the Nios II Embedded Evaluation Kit, Cyclone III Edition on page 9 Controller Hardware or the Nios II Embedded Evaluation Kit, Cyclone III Edition on page 10 Controller Boot Sequence or the Nios II Embedded Evaluation Kit, Cyclone III Edition on page 10 Flash Image on the Altera Embedded Systems Development Kit, Cyclone III Edition on page 11 Controller Hardware or the Altera Embedded Systems Development Kit, Cyclone III Edition on page 12 MAX II Register Interace on the Altera Embedded Systems Development Kit, Cyclone III Edition on page 13 Controller Boot Sequence or the Altera Embedded Systems Development Kit, Cyclone III Edition on page 16 Flash Image on the Nios II Embedded Evaluation Kit, Cyclone III Edition The lash image on the Nios II Embedded Evaluation Kit, Cyclone III Edition contains one actory-programmed image in CFI lash memory. The actory image is the application selector utility. Use the application selector utility to load user designs into CFI lash memory. March 2009 Altera Corporation Using the Nios II Controller Reerence Designs
Page 10 Controller or Cyclone III Devices Controller Hardware or the Nios II Embedded Evaluation Kit, Cyclone III Edition The coniguration controller on the Nios II Embedded Evaluation Kit, Cyclone III Edition board is not a separate chip; it resides in the Cyclone III device. You can conigure the Cyclone III FPGA using either a serial or parallel interace. Conigure the Cyclone_III FPGA serially via a download cable, a serial coniguration device, or an external coniguration controller. Conigure the Cyclone_III FPGA over a parallel interace either passively via an external controller, or actively by reading rom a parallel lash memory device. The Nios II Embedded Evaluation Kit, Cyclone III Edition uses the active parallel (AP) coniguration method. The Cyclone III device contains a hard-coded remote update block that allows logic in the FPGA to control reconiguration. The application selector utility uses this block to reconigure the FPGA with user designs. For more inormation about the remote update block, reer to the Remote Update Circuitry Megaunction User Guide and the Cyclone III Remote Update Controller Core chapter in volume 5 o the Quartus II Handbook. For more inormation about the coniguration capabilities o Cyclone III devices, reer to the Coniguring Cyclone III Devices chapter in volume 1 o the Cyclone III Device Handbook. Controller Boot Sequence or the Nios II Embedded Evaluation Kit, Cyclone III Edition When the Nios II Embedded Evaluation Kit, Cyclone III Edition initially powers on, the coniguration controller attempts to conigure the Cyclone III FPGA rom the CFI lash memory starting at oset 0x20000. Oset 0x20000 is the location o the application selector utility actory image. I coniguration is successul, the controller illuminates the CONF_DONE LED. Ater the application selector utility starts up, LED1 blinks continuously. Once the application selector utility boots, you can load a user image using either the GUI displayed on the touch screen LCD, or over Ethernet by connecting to the board's web server with a web browser. Figure 5 shows the coniguration controller boot sequence lowchart or the Nios II Embedded Evaluation Kit, Cyclone III Edition. Using the Nios II Controller Reerence Designs March 2009 Altera Corporation
Controller or Cyclone III Devices Page 11 Figure 5. Nios II Embedded Evaluation Kit, Cyclone III Edition Controller Boot Sequence Flowchart Power on state Power on reset detected Conigure FPGA rom 0x20000 successul? No Yes Light CONF_DONE LED Start application selector utility Blink LED1 Copy image to lash memory rom SD card or download image over Ethernet Conigure FPGA rom new image successul? No Yes Reset Enter user mode For more inormation about the coniguration process, the application selector utility, and the lash structure o Nios II Embedded Evaluation Kit, Cyclone III Edition, reer to the Nios II Embedded Evaluation Kit, Cyclone III Edition User Guide. Flash Image on the Altera Embedded Systems Development Kit, Cyclone III Edition The lash image on the Altera Embedded Systems Development Kit, Cyclone III Edition contains one actory-programmed image in CFI lash memory. The actory image is the application selector utility. Use the application selector utility to load user designs into CFI lash memory. March 2009 Altera Corporation Using the Nios II Controller Reerence Designs
Page 12 Controller or Cyclone III Devices Controller Hardware or the Altera Embedded Systems Development Kit, Cyclone III Edition You can conigure the Cyclone III FPGA using either a serial or parallel interace. Conigure the Cyclone_III FPGA serially via a download cable, a serial coniguration device, or an external coniguration controller. Conigure the Cyclone_III FPGA over a parallel interace either passively via an external controller, or actively by reading rom a parallel lash memory device. The Altera Embedded Systems Development Kit, Cyclone III Edition uses the passive serial (PS) coniguration method in combination with a coniguration controller that reads coniguration data rom a parallel lash device, then serializes the data in the PS ormat. For more inormation about the coniguration capabilities o Cyclone III devices, reer to the Coniguring Cyclone III Devices chapter in volume 1 o the Cyclone III Device Handbook. The coniguration controller reerence design included with the Altera Embedded Systems Development Kit, Cyclone III Edition, uses a MAXII EPM2210F256 device to generate the coniguration clock or the Cyclone III device as well as generate the address and control signals necessary to pull coniguration data out o lash memory and convert it to serial data or the Cyclone III device. 1 Switch bank SW1 switch 5 (SW1.5), labeled MAX0, must be in the open (1) position to enable FPGA coniguration rom lash memory using the coniguration controller. Putting SW1.5 in the closed (0) position disables the coniguration controller in the MAXII CPLD. Figure 6 shows a block diagram o the coniguration controller reerence design or the Altera Embedded Systems Development Kit, Cyclone III Edition. Using the Nios II Controller Reerence Designs March 2009 Altera Corporation
Controller or Cyclone III Devices Page 13 Figure 6. Development Board Controller or the Altera Embedded Systems Development Kit, Cyclone III Edition A[24..0] D[15..0] CONTROL A[24..0] MAXII EPM2210F256 Controller External Flash Drive D[15..0] CONTROL FPGA Register Interace Clock Generator reset_n PFL Megaunction DATA[0] DCLK Power Monitoring Logic CONF_DONE NSTATUS NCONFIG Reconig_request Cyclone III EP3C120 Status LEDs The coniguration controller or the Cyclone III edition diers considerably rom the Cyclone II and Stratix II coniguration controllers. The Cyclone III coniguration controller uses the Parallel Flash Loader (PFL) megaunction to manage the coniguration process. For more inormation about the PFL megaunction, reer to AN 386: Using the MAX II Parallel Flash Loader with the Quartus II Sotware. In addition to the PFL megaunction, the Cyclone III coniguration controller contains a register interace that allows external logic to control the coniguration process. In the Altera Embedded Systems Development Kit, Cyclone III Edition, the Nios II processor in the actory image is connected to the coniguration controller's register interace, which allows the Nios II to control FPGA reconiguration. MAX II Register Interace on the Altera Embedded Systems Development Kit, Cyclone III Edition The register map or the MAX II interace contains our 32-bit registers. There are no byte enables or writing, so treat all accesses as 32-bit DWORD transactions. Table 4 shows the register names and deault reset values or the register map. March 2009 Altera Corporation Using the Nios II Controller Reerence Designs
Page 14 Controller or Cyclone III Devices Table 4. MAX II Register Map Table 5. Regile 2 Register Description DWORD Register Name Deault Reset Value 0x0 IDR1 0x1338BEEF 0x4 Regile 1 0x00000000 0x8 Regile 2 0x0E787FC0 0xC IDR2 0xDEADBEEF Press the CPU_RESET button or either coniguration button to restore the deault reset values. For coniguration, the only register o interest is the Regile 2 register. Regile 2 is a 32-bit register serving many purposes in a single 32-bit DWORD. Regile 2 is typically accessed as a read/modiy/write unction when writing a bit or number o bits. Table 5 and the ollowing paragraphs show the ield names and descriptions or the Regile 2 register. Name 31... 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OMR RSO RSR RSS DSO DAW OCRE E125 E50 PSO PSR PSS SRST URST MRST Read / Write R RW RW RW R RW RW RW RW RW RW RW R W W W Reset Value 0000111 0 0 1111 SW4 1 1 1 1 1 1 111 SW5 - - - MRST MAX Reset (bit 0) The MRST ield is only local to the MAX II CPLD internals. This ield is write-only. Writing a zero causes a short reset pulse to occur. You cannot hold the device in reset via sotware control. Writing a one to the MRST ield has no eect. URST User Reset (bit 1) The URST ield resets the MAX II CPLD and the Cyclone III FPGA with board net CPU_RESET. This ield is write-only. Writing a zero causes a short reset pulse to occur. This pulse drives the MAX reset and the board reset low. You cannot hold the device in reset via sotware control. I the FPGA uses CPU_RESET as a reset input, the device's logic resets as well. Writing a one to the URST ield has no eect. SRST System Reset (bit 2) The SRST ield resets the MAX II CPLD and reloads the Cyclone III FPGA with coniguration data. This ield is write-only. PSS Page Select Switch (bits 5:3) The PSS ield shows the current position o the PGM CONFIG SELECT rotary switch (SW5). This ield is read-only. When PSO = 1, the PSS ield value determines the image to load rom lash memory into the FPGA. Using the Nios II Controller Reerence Designs March 2009 Altera Corporation
Controller or Cyclone III Devices Page 15 PSR Page Select Register (bits 8:6) When PSO = 0, the PSR ield value determines the image to load rom lash memory into the FPGA. This ield is readable and writable. PSO Page Select Sotware Override (bit 9) The PSO ield indicates the ield to use to determine the image to load into the FPGA. When PSO = 0, the PSR ield determines the image to load. When PSO = 1, the PSS ield determines the image to load. E50 50 MHz Oscillator Enable (bit 10) The E50 ield controls the 50-MHz oscillator that drives to the FPGA. This ield is readable and writable. A zero disables the oscillator. A one enables the oscillator. You must write the OCRE bit low beore the E50 ield actively drives the oscillator's enable pin. Do not disable the oscillator used in the Nios II design responsible or interacing to the MAX II CPLD. E125 125 MHz Oscillator Enable (bit 11) The E125 ield controls the 125-MHz oscillator that drives to the FPGA. This ield is readable and writable. A zero disables the oscillator. A one enables the oscillator. You must write the OCRE bit low beore the E125 ield actively drives the oscillator's enable pin. Do not disable the oscillator used in the Nios II design responsible or interacing to the MAX II CPLD. OCRE Oscillator Control Register Enable (bit 12) The OCRE ield gates usage o the E50 and E125 ields. A zero enables the E50 and E125 ield values to drive the oscillator's enable pin. A one drives both oscillator enable pins regardless o the E50 and E125 ield values. DAW Display Amps/Watts (bit 13) When DSO = 0, the DAW ield controls the power display ormat. A zero displays power in mw. A one displays current in ma. When DSO = 1, the DAW ield has no eect. DSO Display Select Sotware Override (bit 14) The DSO ield gates usage o the DAW ield. When DSO = 1, the display mode is chosen through DIP switch SW1.1, which is the deault behavior. When DSO = 0, the switch has no eect; the DAW ield controls the display. RSS Rotary Select Switch (bits 18:15) The RSS ield shows the current position o the POWER SELECT rotary switch (SW4). This ield is read-only. When RSO = 1, the RSS ield value determines which power rail the MAX II CPLD's power monitoring unction monitors. RSR Rotary Switch Register (bits 22:19) When RSO = 0, the RSR ield value determines which power rail the MAX II CPLD's power monitoring unction monitors. This ield is readable and writable. March 2009 Altera Corporation Using the Nios II Controller Reerence Designs
Page 16 Controller or Cyclone III Devices RSO Rotary Switch Sotware Override (bit 23) The RSO ield indicates the ield to use to determine the power rail to monitor. When RSO = 0, the RSR ield determines the power rail to monitor. When RSO = 1, the RSS ield determines the power rail to monitor. OMR Graphics Display Mode (bit 24) The OMR ield determines whether the graphics LCD is in 8080 mode or 68000 mode. A zero selects 8080 mode. A one selects 68000 mode. Controller Boot Sequence or the Altera Embedded Systems Development Kit, Cyclone III Edition When the Altera Embedded Systems Development Kit, Cyclone III Edition board initially powers-on, the coniguration controller is idle until it detects the power-on reset. Upon detecting power-on reset, the controller attempts to conigure the FPGA rom the image located at page 0. Page 0 contains the application selector utility actory image. The illumination o the FACTORY LED indicates that the actory image is coniguring the FPGA. I coniguration is successul, the controller illuminates the CONF_DONE LED. Ater the application selector utility starts up, LED1 blinks continuously. Once the application selector utility boots, load a user image using either the GUI displayed on the touch screen LCD, or over Ethernet by connecting to the board's web server with a web browser. Ater the user image is loaded into lash memory, the application selector utility uses the register interace attached to the PFL megaunction in the coniguration controller to orce the controller to reconigure the Cyclone III FPGA with the new image. Figure 7 shows the coniguration controller boot sequence lowchart or the Altera Embedded Systems Development Kit, Cyclone III Edition. Using the Nios II Controller Reerence Designs March 2009 Altera Corporation
Controller or Cyclone III Devices Page 17 Figure 7. Altera Embedded Systems Development Kit, Cyclone III Edition Controller Boot Sequence Flowchart Power on state Light FACTORY LED Conigure FPGA rom PFL page 0 Power on reset detected successul? No Yes Light CONF_DONE LED Start application selector utility Blink LED1 Copy image to PFL page 1 rom SD card or download image over Ethernet Conigure FPGA rom PFL page 1 Yes successul? No Reset Enter user mode For more inormation about the coniguration process, the application selector utility and the lash structure o Altera Embedded Systems Development Kit, Cyclone III Edition, reer to the Altera Embedded Systems Development Kit, Cyclone III Edition User Guide that comes on the Altera Embedded Systems Development Kit, Cyclone III Edition CD available on the Altera Embedded Systems Development Kit, Cyclone III Edition page o the Altera website. For inormation about the coniguration and JTAG-related board switch settings, reer to the Cyclone III 3C120 Development Board Reerence Manual. March 2009 Altera Corporation Using the Nios II Controller Reerence Designs
Page 18 Porting the Controller Reerence Designs to Other Boards Porting the Controller Reerence Designs to Other Boards You can easily adapt the coniguration controller reerence design included with Nios II development kits to work on other boards that contain a CPLD and an Altera FPGA. In general, the only required modiication is to match the Nios development board coniguration controller to the type o lash image present on your board. The lash image contained on the Nios development board is an 8-bit-wide, 16-MByte lash image, which requires 24 address lines. Other size lashes may require a dierent number o address bits. In this case, you need to modiy the coniguration controller source code such that the address bus width matches the address width o your lash. I you are using a dierent size lash, you also need to modiy the location o the user and sae images within the coniguration controller. The coniguration controller or the Stratix II development board wires the upper two address bits (namely, bits 23 and 22) to the 16-MByte lash and to 1 (or V CC ), and uses address bit 21 to select between the user and sae images. Figure 8 shows the 16-MByte lash connection. Figure 8. 8-Bit Wide, 16-MByte Uniorm Sector Flash Connection MAX Controller 16-MByte Uniorm Sector Flash Memory A23 A22 A21 A[20..0] V CC Control Logic Address Counter Note to Figure 8: (1) This igure assumes that the coniguration target is an EP2C35 device. Other size devices may have dierent coniguration ile sizes requiring dierent address mapping. I you are using a 4-MByte lash, change the address bus width rom [23..0] to [21..0] and wire address bit 21 o the coniguration controller address bus to 1 (or V CC ); then continue to use bit 20 to select between the user and sae image. Figure 9 shows the 4-MByte lash connection. Using the Nios II Controller Reerence Designs March 2009 Altera Corporation
Modiying the Reerence Design to Support a Variety o System and Requirements Page 19 Figure 9. 8-Bit Wide, 4-MByte Uniorm Sector Flash Connection MAX Controller V CC 4-MByte Uniorm Sector Flash Memory A21 A20 A[19..0] Control Logic Address Counter Note to Figure 9: (1) This igure assumes that the coniguration target is an EP2C35 device. Other size devices may have dierent coniguration ile sizes requiring dierent address mapping. I you are using a top boot sector lash, you also need to make modiications to the source code. The lash used in the Nios II development kits is a uniorm sector lash; thereore, it is generally advisable to leave the lower sections o a uniorm sector lash or the host processor and the upper sections or data storage. However, a top boot sector lash generally reserves the upper sections as processor boot code. In this case, it is better to store the hardware coniguration data in a lower section o the lash. This type o lash requires that the upper address bit (bit 21) o the lash is tied to 0 (or GND), and bit 20 is used to select the user or sae image. Figure 10 shows the top boot sector lash connection. Figure 10. 8-Bit-Wide, 4-MByte Top Boot Sector Flash Connection MAX Controller 4-MByte Top Boot Flash Memory A21 A20 A[19..0] Control Logic Address Counter GND Note to Figure 10: (1) This igure assumes that the coniguration target is an EP2C35 device. Other size devices may have dierent coniguration ile sizes requiring dierent address mapping. Modiying the Reerence Design to Support a Variety o System and Requirements In addition to accommodating dierent lash types, you can modiy the coniguration controller reerence design to support many dierent types o systems and coniguration requirements. For example, you can use a MAX device to create coniguration controllers that can perorm the ollowing tasks: Selecting rom Multiple Flash Images on page 20 Upgrading Hardware Images via an Ethernet Link on page 21 March 2009 Altera Corporation Using the Nios II Controller Reerence Designs
Page 20 Modiying the Reerence Design to Support a Variety o System and Coniguring Multiple Devices on page 21 Selecting rom Multiple Flash Images Figure 11. Image Select Capability The coniguration controller reerence designs that ship with Altera development kits are designed to irst attempt to program the user image into the targeted FPGA. I the user image coniguration attempt ails, the reerence design attempts to program the sae image. The concept o a priority image-selection design can easily be extended to include a number o user images to chose rom to program the FPGA. Figure 11 shows an example coniguration controller that oers priority image selection. The Figure 11 controller design is virtually identical to the Figure 3 controller design. However, the Figure 11 controller has a 2-bit image_select[1..0] bus used to select one o our user images stored in lash memory. The 2-bit image_select[1..0] bus is driven by an external source such as a Nios II embedded processor running in the target device. To load a new image into the target device, the Nios II processor (or external source) writes out the desired coniguration image number to the image_select[1..0] bus and issues a reconiguration request. An alternative solution is to reserve a lash memory location that contains a hardware image number. In this scenario, the processor writes to the desired lash coniguration number. When a reset or reconiguration request occurs, the coniguration controller reads the image number location rom lash and proceeds to load the indicated image into the target device. Controller Sae Image Image 1 Image 2 DATA[7..0] A[22..0] CS_n OE_n RW_n Flash Address and Control-Logic Generator Image 3 Program Memory reset_n Clock Generator Reset Distribution Logic Clock Logic Status Monitor DCLK CONF_DONE STATUS_n CONFIG_n image_select[1..0] Reconig_request FPGA Device Nios II CPU ENET RST PROTO1 RST PROTO2 RST Status LEDs Using the Nios II Controller Reerence Designs March 2009 Altera Corporation
Modiying the Reerence Design to Support a Variety o System and Requirements Page 21 Upgrading Hardware Images via an Ethernet Link Figure 12. Ethernet Reconigurable System The coniguration controller that ships with Altera development kits supports upgrading the hardware image over an Ethernet link. Upgrading can occur when a Nios II embedded processor equipped with a transmission control protocol (TCP) stack is running in the target FPGA. In this scenario, the Nios II processor receives a programming ile via an Ethernet link, and then stores the programming ile into lash memory. When the lash ile upgrade completes, the Nios II processor issues a reconiguration request, which downloads the new hardware image into the target device. Figure 12 shows an example system that can automatically be reconigured via an Ethernet link. Controller Sae Image Image 1 Image 2 DATA[7..0] A[22..0] CS_n OE_n RW_n Flash Address and Control-Logic Generator Image 3 Program Memory reset_n Clock Generator Reset Distribution Logic Clock Logic Status Monitor DCLK CONF_DONE STATUS_n CONFIG_n image_select[1..0] Reconig_request FPGA Device Nios II CPU TCP Stack ENET RST PROTO1 RST PROTO2 RST Status LEDs The Nios Embedded Evaluation Kit, Cyclone III Edition and the Altera Embedded Systems Development Kit, Cyclone III Edition include an application selector utility as their actory design. The application selector utility is capable o remote update using Ethernet. Coniguring Multiple Devices Coniguring multiple FPGAs is another application that demonstrates the lexibility o a CPLD-based coniguration controller. There are a number o dierent coniguration scenarios that exist when multiple FPGAs reside on the same board, including: Multiple identical FPGAs Multiple FPGAs rom the same vendor with dierent hardware images Multiple FPGAs rom dierent vendors March 2009 Altera Corporation Using the Nios II Controller Reerence Designs
Page 22 Conclusion Figure 13. Multiple Device Figure 13 illustrates a coniguration controller that can conigure multiple FPGAs where each FPGA requires a dierent coniguration ile. The Figure 13 controller can program dierent device amily devices rom either the same vendor or dierent vendors. In this scenario, the lash memory contains two coniguration images or two target FPGAs. The Figure 13 controller logic programs one device at a time. Controller FPGA 1 Image FPGA 2 Image DATA[7..0] A[22..0] CS_n OE_n RW_n reset_n Flash Address and Control-Logic Generator Clock Generator Reset Distribution Logic Clock Logic Status Monitor DATA[7..0] Conig signals Reconig_request DATA[7..0] Conig signals Reconig_request Device 1 Device 2 ENET RST PROTO1 RST PROTO2 RST Status LEDs Conclusion The use o lash memory to store hardware coniguration data or FPGAs located in an embedded system typically requires an intelligent coniguration controller. Many o Altera s development boards contain a programmable coniguration controller that provides a stable platorm or managing system coniguration and reset in embedded systems. You can port the Nios II coniguration controller reerence designs to other boards, as well as modiy the designs to support more complex systems and coniguration requirements. Because the Altera MAX amily CPLDs are ideally-suited or use as board-level coniguration controllers, coniguration controllers on Altera development boards utilize Altera MAX CPLDs. The programmable nature o MAX CPLDs allows you to use the same device in a variety o dierent systems. Because the MAX device supports both local and remote coniguration updates, a MAX-based coniguration controller is particularly useul in systems with embedded processors such as the Nios II embedded processor. Document Revision History Table 6 shows the revision history or this document. Using the Nios II Controller Reerence Designs March 2009 Altera Corporation
Document Revision History Table 6. Document Revision History Date and Revision Changes Made Summary o Changes March 2009 Added coverage or the Nios II Embedded Evaluation Kit, Cyclone III v1.2 Cyclone III Edition using the Cyclone III FPGA Starter Board and the Altera Embedded System Development Kit, Cyclone III Edition using the Cyclone III 3C120 Development Board. July 2006 v1.1 March 2004 v1.0 Updated application note to cover Stratix II and Cyclone II, rather than Stratix and Cyclone. Stratix II, Cyclone II Initial Release. 101 Innovation Drive San Jose, CA 95134 www.altera.com Technical Support www.altera.com/support Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, speciic device designations, and all other words and logos that are identiied as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks o Altera Corporation in the U.S. and other countries. All other product or service names are the property o their respective holders. Altera products are protected under numerous U.S. and oreign patents and pending applications, maskwork rights, and copyrights. Altera warrants perormance o its semiconductor products to current speciications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out o the application or use o any inormation, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version o device speciications beore relying on any published inormation and beore placing orders or products or services.