Validation Strategies with pre-silicon platforms

Mobile & Internet-of-Things Driving Growth Convergence SoC complexity New verification challenges Multicore CPUs + Multicore Graphics + Multimedia + Connectivity + Sensors Verification Complexity Power Efficiency More Software Time-to-Market 2014 Synopsys. All rights reserved. 3 Synopsys Confidential

SoC Multi Core Architecture Trends Massive feature integration Driven largely by Moore s Law (supply) and convergence (demand) Distributed architectures Higher scalability (and independence) Sharing memory Multiple processors (Multicore) CPU DSP Special purpose (MPEG, GFX, ) Always on controller Distributed DMA Removes centralized DMA bottleneck Increasing software complexity Re-use with multiple platform SoCs Broader end use market coverage per SoC with software programmability From NIT Alumni Meet Keynote Speech: Jim Hogan 2014 Synopsys. All rights reserved. 4 4

SoC Design Complexity & Cost Out of Control Increasing complexity means increased risk At 32nm, a typical design has ~50% chance to meet all objectives At 22nm, that number drops to ~30% Source: I.B.S. Inc. Designer productivity must improve to match chip complexity The later a problem is detected, the more impact it will have on design schedules SoC Development Cost 2014 Synopsys. All rights reserved. 5 Source: Gartner

Need Shift-Left for Faster Time-to-Market Earlier HW verification, earlier SW bring-up SoC Bugs Found per Week Static & Formal Automate Setup VIP Debug Faster Simulation Earlier Virtual Platforms Fast Emulation HW-SW Bring-up Virtual & FPGA Prototyping Project Time Smart Verification Strategy - Static and Formal Earlier HW-SW Bring-up - Faster emulation Intelligent Verification Methodology - Integrated, automated flows Verification Continuum - Seamless flow 2014 Synopsys. All rights reserved. 6 Synopsys Confidential

Three Ways to Emulate 256 Million Gates Emulation chip capacity accounts for the wide range of sizes. Custom Processors Commercial FPGAs 1 meter Custom FPGAs 2014 Synopsys. All rights reserved. 8 CONFIDENTIAL 4/10/2014

Custom Emulation Chip Advantages Compile Time Custom FPGA Custom Processor Commercial FPGA Faster due to emulation-specific interconnect architecture. Faster due to processor-type architecture. Slower due to chip place & route. Easily run on parallel on a small server farm. Debug Built-in: Change probes without recompile. Built-in: Change probes without recompile. Mix of built-in (readback) and FPGA resource. Some probe changes require recompile. Emulation Compiler Single-vendor: Fully integrated, all vendor-developed at vendor cost. Small user base. Single-vendor: Fully integrated, all vendor-developed at vendor cost. Small user base. Chip-level half by FPGA vendor s large team at no cost. Large user base good for quality. 2014 Synopsys. All rights reserved. 9 CONFIDENTIAL

Commercial FPGA based solution superior for Emulation Highest capacity per chip ZeBu Server 3 module emulates 60M gates in 9 emulation chips. Palladium XP needs 54 chips, Veloce 2 needs 75 chips. Components fit better, fewer design nets get cut. Means less interconnect HW Highest performance: 2 to 5 MHz Low power, small size, reliable Latest process every two years From Xilinx, no development cost == Lowest TCO Fastest, coolest, smallest, cheapest, most reliable logic emulation. 2014 Synopsys. All rights reserved. 10 CONFIDENTIAL

ZeBu Server-3 Hardware Performance Advantage 6-8X larger capacity emulation chips fewer nets must cross chip-to-chip, more nets stay on-chip where they are fast High bandwidth communication between emulation chips, modules, units, host Each chip has 600 Gbps bandwidth to other chips 33 Gbps bandwidth between modules 640 Gbps bandwidth between units 4 Gbps host communication bandwidth FPGA architecture advantages Specialized HW for arithmetic operations in FPGA. Wire-to-wire and gate-to-gate mapping, no modeling abstraction Application Design Size Performance GPU Quad Cluster 60 MG 5.0 MHz GPU Dual Cluster 40 MG 4.95 MHz GPU Single Cluster 33 MG 4.75 MHz Customized GPU 50 MG 3.75 MHz Communication Processor 60 MG 2.9 MHz Consumer SoC 100 MG 2.8 MHz Broadband SOC 80 MG 2.5 MHz 2014 Synopsys. All rights reserved. 11

ZeBu Server-3 Throughput Advantage Highest raw performance hardware Multi-threaded runtime Truly concurrent communication message port No blocking message transfer Dedicated high speed HW resources for implementation of transactors and communication ports. Each transactor can be modeled as separate process for maximum parallelism. 2014 Synopsys. All rights reserved. 12

Verification: Architecture to Silicon Accuracy Architecture Exploration HW / SW Integration Functional Verification System Validation Does the architecture meet performance and power requirements? Processor & GPU selection Memory System Dimensioning Interconnect Configuration Cache Coherency Global Interrupts Power Management Prototype SW before first silicon OS Integration Driver Development Virtualisation Performance Optimisation Does the design function correctly &meet performance and power requirements? Protocol Compliance Interconnect BW & Latency Cache Coherency Data integrity Power & Clock Domains Validate that the design functions as specified. Graphics Video Audio Browser Application Gesture recognition Phone functions Camera functions Design Technology: Tools: Design Technology: Design Technology: Traffic Models Transaction Level Models Performance Visualisation Hybrid-Simulation Debugger Transaction Level Models systemc Virtual Prototypes FPGA Prototypes Performance Visualisation Traffic Models Verification IP System Monitor Performance Visualisation FPGA Prototypes HW Accelerated Simulation Hybrid-Simulation Verification IP Transaction Level Models IO Traffic Turn Around Time 2014 Synopsys. All rights reserved. 14

Common HW-Assisted Verification Modes Host Workstation External Hardware Target System Simulation Test bench Simulator DUT In-Circuit Emulation (ICE) DUT Emulator Buffer Rate Adaptor Embedded Testbench Object Code Emulator DUT Co-Simulation (Signal-Level) Test bench Simulator DUT Emulator Transaction-Based Verification (TBV) Virtual Peripheral Transactor SCEMI/ZEMI Transactor DUT Emulator 2014 Synopsys. All rights reserved. 15 Confidential

Summary of Verification Modes External Hardware Challenges Simulation Everyone has one Perfect for 90% of designs Never fast enough In-Circuit Emulation (ICE) Highest performance Physical connections Rate adapter availability Embedded Testbench Co-Simulation (Signal-Level) Transaction-Based Verification (TBV) Very fast No physical connections Simple to use Leverages existing TB Good for DUT bring-up Highest performance Works with virtual devices No rate adapters needed Needs synthesizable TB Limited to Software only Little performance gain Availability of transactors 2014 Synopsys. All rights reserved. 16 Confidential

One Emulator, Many Applications Advanced verification use modes with ZeBu Server-3 Hybrid Emulation architecture optimization & early software development Transaction-based Verification system-level SoC verification In-circuit Emulation real-world connections Simulation Acceleration up to 100x simulation performance Synthesizable Testbench higher performance Power-aware Emulation UPF support and SAIF output 2014 Synopsys. All rights reserved. 17 Synopsys Confidential

Environment for In-Circuit Emulation Emulator DUT Wires Adapter DDR Memory Wires Adapter Flash Memory Physical Test Environment Ethernet Wires Wires Wires Wires Wires Wires Wires Frame Grabber Frame Grabber Frame Capture Slow-Down Bridge Slow-Down Bridge Adapter Adapter Adapter Adapter Adapter Adapter Adapter NTSC TV LCD Display Terminal Digital Still Camera Keypad USB 2.0 Ethernet 10/100 ARM11 Core DSP Core Logic Memory Wires HW CODEC Adapter I2S Audio Wires Lauterbach Pod Adapter JTAG SoC Prototype 2014 Synopsys. All rights reserved. 18 Confidential

Transaction-based Verification Environment PC Emulator RTB DUT LCD Display Window TV Display Window Synthesizable DDR2 Memory Synthesizable Flash Memory DDR Memory Flash Memory C C NTSC Transactor LCD Transactor HW HW NTSC TV LCD Display ARM11 Core C UART Transactor HW Terminal DSP Core Image Files C C DSC Transactor Keypad Transactor HW HW Digital Still Camera Keypad Logic Ethernet HDD C Model NIC Card C C USB Function Transactor Ethernet Transactor HW HW USB 2.0 Ethernet 10/100 Memory SW CODEC C I2S Transactor HW I2S Audio SW Debugger C JTAG Transactor HW JTAG SoC Prototype Virtual Test Environment Transactors 2014 Synopsys. All rights reserved. 19 Confidential

ZeBu Power Analysis Generates Power Profiles Ideal for block and system-level analysis with hardware and software Captures every transition within each clock period User-programmable: blocks, registers, buses, entire SoC Includes cumulative total spanning user-defined clock numbers Large span for highest performance Short span for highest accuracy Works seamlessly with PrimeTime 10 15 3 31 21 53 12 18 6 12 21 9 Unexpected power spike 59 104 48 Focus to identify source SAIF or FSDB files 2014 Synopsys. All rights reserved. 20 Confidential

ZeBu Hybrid Emulation Architecture optimization and early software development TLM2 Adapter ZeBu TLM 2.0 Transactor Platform Creator Adapter User Traffic, Scenarios for Exploration Architecture Model Library Third Party SystemC Virtual Prototype Platform Architect MCO / Virtualizer RTL runs at high speed in ZeBu while processor model or other components run in virtual prototype Reduces need to have high level models for all components 2014 Synopsys. All rights reserved. 21 Synopsys Confidential

Verdi 3 s Unique Technology Clock Tree Extraction/Debug Power-Aware Debug Siloti Design & Synthesis Synthesis Synthesis Formal Formal State State Verification Inference Evaluation Trace This Inference Value Phase Trace Evaluation Active Phase X Models Phase Phase Phase Phase Assertion Analysis Verdi Behavior Verdi Behavior Analysis Analysis Engine Engine Verdi 33 Visualization Bundled with simulator Verdi Behavior with basic Analysis debug: Engine Waveform, Source Verdicode, Schematic Only come in to play after simulation, Debug Automation Visualization tied with specific version and platform Database in not optimized for debug esign & Design & rification Verification odelsmodels Combining Uncluttered Design Optimized for debug state/event behavior database Combining Uncluttered Design needs Optimized for debug information Combining state/event behavior visualization Design database Optimized for Simulator Verification Uncluttered and Debug Oriented DB needs De facto Standard FSDB information visualization Database Debug Needs FSDB State/Event Platform Independent Behavior FSDB Information Visualization Native Debug A Native Debug B 2014 Synopsys. All rights reserved. 24 Confidential

ZeBu Simulator-Like Debug with Verdi 3 RTL & Gate-Level Hierarchical Debug Full visibility (RTL & gate level) All registers, nodes, memories Run-time and post-run debug No recompiles required Open standard support FSDB, VCD, etc. Transaction level debug icsa integration for fast time to waveform New! Runtime Control Verdi 3 Waveform 2014 Synopsys. All rights reserved. 25 Synopsys Confidential

Complex Debug Scenarios Cache Coherency Error First Symptom (OS Hangs) Problem: Symptom happens far later than bug Root cause cannot be traced 2+ billion clocks Typical Logic Analyzer Trace Depth (1 million samples) Reset (1000 clocks) Boot OS (Bootloader, Kernel, Init, VM, etc.) (1 billion clocks) System Services (Pwr, Batt, NetStat, Blutooth, etc.) (1 billion clocks) User Applications (Internet Browser) 1 1k 2k 3k 1B 2B 2.1B CPU Clocks 2014 Synopsys. All rights reserved. 26 Confidential

ZeBu Post Run Debug Billion-Cycle Full Visibility, Optimized for HW/SW Co-Verification Testbench captures DUT state periodically DUT inputs captured on every clock Data stored on Host PC disk drive To debug, user selects a restore point and loads it into ZeBu to generate waveforms Host Machine 2+ billion clocks Reset (1000 clocks) Boot OS (Bootloader, Kernel, Init, VM, etc.) (1 billion clocks) System Services (Pwr, Batt, NetStat, Blutooth, etc.) (1 billion clocks) User Applications (Internet Browser) 1 1k 2k 3k 1B 2B 2.1B CPU Clocks 2014 Synopsys. All rights reserved. 27 Confidential

HW/SW Debug Overview Embedded Processor Debug with Synchronized RTL, C, Assembly Enables co-debug between RTL and SW HW and SW debug synchronized in time View C/Assembly source, C variables, stack, memory Debugs multiple core simultaneously Supports all popular cores Easy to support additional cores or custom cores Custom Core support without exposing CPU internals CPU (RTL) USB Host IIP Mem Model X-Bar (RTL) Application Logic (RTL) SoC Simulation/Emulation Mem Image Programmer s View Full Verdi Features 2014 Synopsys. All rights reserved. 28 Confidential

HW/SW Debug Use Models Verification Environment with C-Tests Part of SoC verification schedule Hardware debug with C-tests /stimulus C-tests may have minimal OS or boot code Requires concurrent software and hardware debug Use HW/SW Debug for this task Driver Development Software (driver) development Fast speed is required ( 1MHz) Approximate hardware is acceptable Example text Fill in your own text Example text Fill in own text Example text Use Virtualizer for this task Prepare for First Silicon Bring-Up Debug synthetic tests mimic specific use scenarios Tests run on a bare-metal OS Develop and bug tests on a pre-silicon model Get ready for silicon bring up Use HW/SW Debug for this task First Silicon Debug Observed failure running Example test text on first silicon Fill in your own text Debug the failure and isolate a design bug Example text Create/Validate software/firmware Fill in own text workaround Example text Use HW/SW Debug for this task 2014 Synopsys. All rights reserved. 29 Confidential