Outline An Introduction to Programmable Logic 3 November 24 Transistors Logic Gates CPLD Architectures FPGA Architectures Device Considerations Soft Core Processors Design Example Quiz Semiconductors Semiconductor Physics Semiconductors: Can be conductor OR insulator, located at boundary of the two Insulators: Do not conduct electricity Metals: Conduct electricity
Transistor Analog Characteristics Transistor Switch Apply current here And the switch is on! Fundamental Logic Gates Transistor Logic Implementation NOT NAND 2
Logic Combinations Basic Logic Example Output Input AND Gate AND Gate OFF All inputs must be a or On in order to have an output of or On The Flip-Flop Flop Logic Integrated Circuits transition A transition B Introduced in the late 6 s Multiple gates in a single package! Aliases: DTL, RTL, TTL, SSI, MSI, LSI Major players today: Philips, TI, National Gives design flexibility to connect individual chips off the shelf saving lots of time DATA CLOCK OUTPUT go! go! The black outline is the IC package, this one 6 pin Dual Inline Package (DIP) time 4-5 gates 3
Programmable Array Logic (PAL) Programmable Logic Device Developed in the late 7 s Major player today: Lattice First device that needs software interconnect gates flip flops D Q D Q D Q D Q 5-2 gates Definition: PAL*-derived programmable logic devices that implement logic as sum-of of- products driving macrocells. *Programmable Array Logic. Oldest practical form of programmable logic, implemented a sum-of-products plus optional output flip-flops. interconnect macrocells 32-24 macrocells Altera MAX Macrocell Altera MAX CPLD Architecture 4
Altera CPLD Look-Up Table Logic Macrocells Internal Routing I/O Elements (IOEs) Field Programmable Logic Array Altera FPGA Logic Element (LE) 2 types of FPGAs Reprogrammable (SRAM- based) Xilinx, Altera, Lattice, Atmel One-time Programmable (OTP) Actel, Quicklogic LUT flip flop SRAM logic cell gates flip flop OTP logic cell 5
Altera FPGA Interconnect Altera FPGA Memory Block Altera FPGA Multiplier Block Altera FPGA DSP Blocks Logic Array Blocks (LABs) M-RAM Blocks Phase-Locked Loops (PLLs) I/O Elements (IOEs) M52 RAM Blocks M4K RAM Blocks Internal Routing 6
Issues - Interconnect Issues Input / Output Method to hook-up gates inside a single device Need to have enough to connect most gates Larger gate counts result in bigger die size & higher cost horizontal interconnect A vertical interconnect B used interconnect path All signals on & off chip must go through I/O buffer User can choose many I/O buffer options I O I/O buffer package pin silicon die gates Issues Propagation Delay Propagation Delay: The time required for a signal to travel from A to B, measured in nanoseconds (ns). A Gate Delay B Interconnect Delay A B Issues Path Delay Path Delay: The sum of all the gate and net delays from starting to ending point. A fanout=2 C B t PD = 3ns t PD = ns t PD = 3ns t PD =.2ns t PD = 3ns t PD =.8nst PD = 3ns Path Delay A to B = sum of all gate + net delays 3ns +.2ns + 3ns +.8ns + 3ns = 2ns 7
Issues Maximum Frequency Maximum Frequency: The fastest speed a circuit containing flip-flops flops can operate. Issues Power Consumption Power = V CCINT x I CCINT + P EXT D Q D Q t CQ = 2.5ns t PD = ns t PD =.5ns t PD =.5ns t PD = 2ns t PD =.5ns f MAX = /(flip-flop delay + gate delays + net delays) = /(2.5 + +.5 +.5 + 2 +.5)ns = 25 MHz CPLD versus FPGA System Partitioning Yesterday CPLD Lower Power Lower Density Lower Speed FPGA Higher Power Higher Density Higher Speed Backplane ASSP ASSP DSP PLD PLD SRAM Flash Processor ASSP DRAM O/E O/E DRAM Logic Processors Memory Analog Optical /Analog Serial Backplane Communication Serial Chip-to-Chip Line-Side Communication Communication 8
FPGA Vendor Desired System Today NIOS II Processor Core Flash DRAM DRAM Backplane Stratix O/E O/E Optical /Analog Altera Logic Devices Now Perform Majority of System s Digital Functions NIOS II Processor Example FPGA Design Design Entry Design Implementation Functional & Timing Verification Synthesis & Functional Simulation Define Design Functionality Schematic HDL Optimize Design Functionality Functional Simulation Compilation Convert to FPGA resources Place & Route Design Verification Verify Design Functionality Verify Performance Timing Simulation 9
3 Second Timer Expired Traffic Light Design Traffic Light State Diagram EW Car Present / Set Second Timer 3 Second Timer Expired / Set Second Timer Design Examples Design Comparisons Hardware Based Design Implemented Completely in Discrete Logic Soft Core Processor Based Design Implemented in Software With MicroC/OS /OS-II RTOS Logic Elements PLLs DSP Blocks Memory Design Effort Modification Effort Hardware Design 48 Moderate Moderate Processor Design 356 8 57,36 Easy Easy
Resource Usage Quiz Questions Resource Usage Does a transistor functions as an insulator, a conductor or a switch? A switch Are logic gates built with paper, plastic or transistors? Transistors Name three fundamental logic gates? And, Or and Not What does FPGA stand for? Field Programmable Gate Array What is a look-up table? A memory block that is used to implement logic functions Define the maximum frequency of an FPGA. The highest clock frequency at which the FPGA can operate correctly What is a Soft Core processor? A processor built using FPGA resources (e.g. gates, memory) How are VHDL and / or Verilog used in FPGA design? Simulation and Synthesis - A subset of each language is synthesizable into logic Quiz Questions Presentation Questions? How long does it take a lobster to grow to be lb? 7 Years How much does a pelican consume in one meal? About /3 of its body weight How fast can a grizzly bear run? About as fast as the average horse When was the first million share trading day on the NYSE? 886 What does a selenologist study? The Moon What is the largest island in the world? Greenland, at 84, square miles