ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec : April 4, 7 Memory Overview, Memory Core Cells Today! Memory " Classification " ROM Memories " RAM Memory " Architecture " Memory core " SRAM " DRAM " Periphery (time permitting) CPU Memory Hierarchy Memory Overview CPU Chip L on-cpu cache off-chip cache memory L L3 L4 k to 64 k SRAM (register file) 64k to 4M 4M to 3M SRAM or DRAM 8M 4 Locality and Cacheing Semiconductor Memory Classification! Memory hierarchies exploit locality by cacheing (keeping close to the processor) data likely to be used again! This is done because we can build " large, slow memories OR " small, fast memories BUT " we can t build large, fast memories! If hierarchy works, we get the illusion of SRAM access time with disk based memory capacity. " SRAM (static RAM) -- 5- ns access time, very expensive (on-cpu faster) " DRAM (dynamic RAM) -- 6- ns, cheaper " Disk -- access time measured in milliseconds, very cheap Random Access SRAM DRAM RWM NVRWM ROM Non-Random Access FIFO LIFO Shift Register CAM EPROM E PROM FLASH Mask-Programmed Programmable (PROM) 5
Memory Architecture: Core Memory Architecture: Decoders M bits M bits M bits M bits N Words S S S S N- S N_ Word Word Word Word N- Word N- Storage Cell A A A K- Decoder S Word Word Word Word N- Word N- Storage Cell N Words S S S S N- S N_ Word Word Word Word N- Word N- Storage Cell A A A K- Decoder S Word Word Word Word N- Word N- Storage Cell Input-Output (M bits) Input-Output (M bits) Input-Output (M bits) Input-Output (M bits) N words > N select signals Too many select signals Decoder reduces # of select signals K logn N words > N select signals Too many select signals Decoder reduces # of select signals K logn Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH L-K Bit Line Storage Cell Latches/Register Can Store a State! Build master-slave register from pair of latches! Control with non-overlapping clocks A K A K+ A L- Row Decoder Word Line Sense Amplifiers / Drivers M. K Amplify swing to rail-to-rail amplitude A A K- Column Decoder Selects appropriate word Input-Output (M bits) MOS NOR ROM ROM Memories [] [] [] [3] [] [] [] [3]
MOS NOR ROM MOS NOR ROM [] [] [] [] [] [3] [] [3] [] [] [] [3] [] [] [] [3] MOS NAND ROM MOS NAND ROM [] [] [] [3] [] [] [] [3] [] [] [] [] [] [] [3] [3] All word lines high by default with exception of selected row All word lines high by default with exception of selected row MOS NAND ROM Non-Volatile Memory ROM PseudonMOS NOR gate [] [] [] [3] [] [] [] [3] All word lines high by default with exception of selected row 8 Kenneth R. Laker, University of Pennsylvania, updated Apr5 3
Contact-Mask Programmable ROM Contact-Mask Programmable ROM 9 Read-Write Memories (RAM) Latches/Register Can Store a State! Static (SRAM) " Data stored as long as supply is applied " Large (6 transistors/cell " Fast " Differential! Dynamic (DRAM) " Periodic refresh required " Small (-3 transistors/cell) " Slower " Single ended! Build master-slave register from pair of latches! Control with non-overlapping clocks Gate Based Latch 6T SRAM Cell! How many transistors in this latch?! Cell size accounts for most of memory array size! 6T SRAM Cell " Used in most commercial chips " Data stored in cross-coupled inverters! Read: " Precharge, bit " Raise word! Write: " Drive data onto, " Raise bit_b 3 4 4
6-transistor CMOS SRAM Cell 6-transistor CMOS SRAM Cell M M M M 6-transistor CMOS SRAM Cell CMOS SRAM Analysis (stored ) Assume is stored () M M M 6-transistor CMOS SRAM Cell CMOS SRAM Analysis (Read) Assume is stored () Read Operation: - First bitlines get precharged high (Vdd) - Then wordline goes high (Vdd) M M V M k n, --------------- ----------- V Tn ----------- k nm, ( V ) V Tn ----------- DD ----------- 8 (W/L)n, (W/L)n,M (supercedes read constraint) 5
CMOS SRAM Analysis (Read) CMOS SRAM Analysis (Read) V M V M k n, ΔV V Tn ( ) k n,m ( V Tn )ΔV ΔV W k n, L 5 k n,m W L ( V Tn )ΔV ΔV ( ΔV V Tn ) CMOS SRAM Analysis (Read) CMOS SRAM Analysis (Read) V M Voltage Rise (V)..8.6.4. W k n, L 5 k n,m W L ( V Tn )ΔV ΔV ( ΔV V Tn ) ΔV V Tn W L 5 W L (.5V Tn )V Tn V Tn ( ).5..5 Cell Ratio (CR).5 3 6-transistor CMOS SRAM Cell CMOS SRAM Analysis (Write) Assume is stored () Write Operation: - Want to write a - First drive bitlines with input data - Then wordline goes high (Vdd) M M k n, ( V ) Tn ---------- ---------- 8 M k p, ( V ) Tp ---------- ---------- 8 (W/L) n,.33 (W/L) p, k n, ------------- ---------- V Tn ---------- kn, ( M ) V DD V VTn ---------- DD ----------- 8 (W/L) n, (W/L) n,m 6
CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) M M ( ) k n,m 4 ( V Tp )V V k n,m 6 V Tn k n,m 4 k n,m 6 ( V Tn ) ( V Tp )V V CMOS SRAM Analysis (Write) CMOS SRAM Analysis (Write) PR W 4 L 4 W 6 L 6 PR W 4 L 4 W 6 L 6 M k n,m 4 k n,m 6 ( V Tn ) ( V Tp )V V V V Tn k n,m 4 k n,m 6 ( V Tn ) ( V Tp )V Tn V Tn DRAM 3-Transistor DRAM Cell! Smaller than SRAM! Require data refresh to compensate for leakage W W R R M X M X -VT C S -VT ΔV No constraints on device ratios Reads are non-destructive Value stored at node X when writing a V W-V Tn 4 7
-Transistor DRAM Cell DRAM Cell Observations C M C S X / C ΔV V V ( PRE V BIT V ) S ----------------------- PRE C S + C Write "" Read "" V T sensing / Write: CS is charged or discharged by asserting and. Read: Charge redistribution takes places between bit line and storage capacitance T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than. Voltage swing is small; typically around 5 mv. Periphery Memory Periphery! Decoders! Sense Amplifiers! Input/Output Buffers! Control/Timing Circuitry Array Architecture Array Architecture! n words of m bits each! Good regularity easy to design! Very high density if good cells are used! n words of m bits each! Good regularity easy to design! Very high density if good cells are used 47 48 8
Array Architecture Array Architecture! n words of m bits each! Good regularity easy to design! Very high density if good cells are used! n words of m bits each! Good regularity easy to design! Very high density if good cells are used 49 5 Decoders Decoders! n: n decoder consists of n n-input AND gates " One output needed for each row of memory " Build AND from NAND or NOR gates Static CMOS A A word word A A 8 4 word word word3 5 Large Decoders! For n > 4, NAND gates become slow " Break large gates into multiple smaller gates A3 A A A word Predecoding! Many of these gates are redundant " Factor out common A3 gates into predecoder A " Saves area " Same path effort A A predecoders word word of 4 hot predecoded lines word word word3 word word3 word5 word5 53 54 9
Row Select: Precharge NAND Row Select: Precharge NOR 55 56 Array Architecture Column Circuitry & Bit-line Conditioning! n words of m bits each! Good regularity easy to design! Very high density if good cells are used 58 Column Circuitry Bitline Conditioning! Some circuitry is required for each column! Precharge bitlines high before reads " Bitline conditioning " Precharging " Driving input data to bitline bit φ bit_b " Sense amplifiers " Column multiplexing (AKA Column Decoders) 59 6
Bitline Conditioning! Precharge bitlines high before reads Bitline Conditioning! Precharge bitlines high before reads bit φ bit_b bit φ bit_b! What if pre-charged to Vdd/? " Pros: reduces read-upset " Challenge: generate Vdd/ voltage on chip 6 6 Sense Amplifiers Idea! Bitlines have many cells attached " Ex: 3-kbit SRAM has 8 rows x 56 cols " 8 cells on each bitline! t pd (C/I) ΔV " Even with shared diffusion contacts, 64C of diffusion capacitance (big C) " Discharged slowly through small transistors in each memory cell (small I)! Sense amplifiers are triggered on small voltage swing V (ΔV) V()! Memory for compact state storage! Share circuitry across many bits " Minimize area per bit # maximize density! Aggressively use: " Pass transistors, Ratioing " Precharge, Amplifiers to keep area down V PRE ΔV V() Sense amp activated Word line activated t 63 64 Admin! Homework 7 due Thursday " Extra Credit due Sunday! Project partners due Thursday " Email your team names to me " taniak@seas.upenn.edu! Final Project " Design and layout memory " Handout posted before Thursday class " Due 4/5 (last day of class) " Everyone gets an extension until 5/3 (day of final exam) 65