IA-32 CSE 5302 Spring 2011 Ngoc Tam Tran 3/3/2011 1
Overview IA-32(Intel Architecture 32-bit) CISC Architecture Many instructions sets 3/3/2011 2
Registers 16 basic program execution registers for use in general system and application programming 8 General-purpose registers Holding: Operands for logical and arithmetic operations Operands for address calculations Memory pointers 6 segment registers Hold up to 6 segment selectors Segment selector is a special pointer that identifies a segment in memory EFLAGS (program status and control) register Report on the status of the program being executed and allows control of the processor EIP (instruction pointer) register Contains a 32-bit pointer to the next instruction to be executed 3/3/2011 3
Registers (Cont.) 8 General Purpose Registers 6 Segment Registers EIP (instruction pointer) Register EFLAGS (program status and control Register) 3/3/2011 4
Immediate Operands Maximum size 2^32 Register Operands Operand Addressing Source and destination operands can be General-purpose registers Segment registers EFLAGS register Memory Operands Source and destination operands in memory are referenced by means of a segment selector and an offset Segment selectors specify the segment containing the operand Offsets specify the effective address of the operand 3/3/2011 5
Specifying a Segment Selector Common method is to load it in a segment register and then allow the processor to select the register implicitly depending on the type of operation The processor automatically chooses a segment according to the rules below 3/3/2011 6
Specifying an Offset Can be specified directly as a static value (displacement)or through an address computation by using Displacement An 8-, 16-, or 32-bit value Base The value in a general-purpose register Index The value in a general-purpose register Scale factor A value of 2, 4, or 8 that is multiplied by the index value Example [EAX][EDI*2 + 80] The effective address is calculated by taking the contents of register EDI multiply by 2 and add it to a constant 80, then add to the contents of register EAX 3/3/2011 7
Instruction Types for Arithmetic, Logical, & Data Transfer Instructions Source/Destination Operand Type Register Register Register Memory Memory Second Source Operand Register Immediate Memory Register Immediate Immediate: 8, 16, or 32 bits Register: 1 of 14 General Purpose or Segment Registers Arithmetic and Logical instructions must have 1 operand acts as both source and destination 1 of the operands can be in the memory 3/3/2011 8
Integer Operations Support 8-bit, 16-bit, and 32-bit Can be divided into 4 major classes Data movement instructions: move, push, pop Arithmetic & logic instructions: test, integer & decimal arithmetic operations Control flow: conditional branches, unconditional jumps, calls, returns String instructions: string move & string compare 3/3/2011 9
Integer Operations (Cont.) 3/3/2011 10
General Instruction Format Instructions consist : Instruction prefixes (optional) Opcode (1 or 2 bytes) ModR/M SIB (Scale-Index-Base) byte Displacement (if required) Immediate data field (if required) 3/3/2011 11
General Instruction Format (Cont.) Instruction prefixes Modify the instruction Repeat string instructions Provide section overrides Change operand and address sizes Opcode Decide the operation to take ModR/M Addressing modes Register/Memory Mod = 00 1st operand is a register 2nd operand is in memory, address stored in a register numbered by R/M (Memory[Reg[R/M]]) 3/3/2011 12
General Instruction Format (Cont.) ModR/M (Cont.) Mod=01 Same like Mod 00 with 8-bit displacement Mod=10 1st operand is a register 2nd operand is in memory, address stored in a register numbered by R/M plus displacement (Memory[disp8+Reg[R/M]]) Same like Mod 01 with 32-bit displacement Mod=11 SIB Bytes 2nd operand is a register, numbered by R/M Scale Index Base 3/3/2011 13
Instruction Encoding Instruction encodings are subsets of the general instruction format Encoding the instruction is complex Many different instruction formats Instruction may vary from 1 byte up to 17 bytes 3/3/2011 14
Instruction Encoding (Cont.) 3/3/2011 15
References 1. IA-32 Intel Architecture Software Developer s Manual. Volume 1: Basic Architecture. Available from http://flint.cs.yale.edu/cs422/doc/24547012.pdf. 2. IA-32. Available from http://en.wikipedia.org/wiki/ia-32. 3. D. Patterson and J. Hennessy. Computer Organization Design the Hardware/Software Interface. 3 rd Edition. 2005. 4. IA-32 Intel Architecture Software Developer s Manual. Volume 2: Instruction Set Reference. Available from http://www.cs.grinnell.edu/~walker/courses/211.fa01/pentium-3- manual-instructions.pdf 5. IA-32 (x86) Architecture. Available from http://pages.cs.wisc.edu/~cs354-1/cs354/karen.notes/pentium.html 6. IA-32 Instruction Set Architecture. Available from http://cs.gmu.edu/~huangyih/365/lec04-ia32.pdf 3/3/2011 16