Chapter 10. Counters (a short discussion)

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EE2L_ClassNotes_Ch_Counters_transparencies.fm Chapter Counters (a short discussion) ecimal count sequence: Ex: 788, 789, 79,... Ex: 798, 799, 8,... Generalization: 2 Binary count sequence: In a multi-bit up counter, a bit (such as 2) will flip (increment) when all its right neighbors ( and ) are (all s / all s). In a multi-bit down counter, a bit (such as 2) will flip (decrement) when all its right neighbors ( and ) are (all s / all s). 3 Basic element in building a counter: A toggle flip-flop 2 2 A JK FF with its J and K tied to (, /,) acts as a toggle FF. If the J and K are tied to (, /,), the FF remains stay put. 4 Ripple counter K Which of the following is an up-counter and which is a down-counter? What are the rest? o you call the counter a positive-edge triggered counter or a negative-edge triggered counter or a mixed-edge triggered counter? Whey are these called ripple counters? J K J 4/24/6 EE2L Class Notes - Chapter # Counters Page / 8 C Copyright 26 Gandhi Puvvada

EE2L_ClassNotes_Ch_Counters_transparencies.fm J K J K J K J K J K J K J K J K J K J K J K J K The above 4 hook-ups are reproduced below with an inverter in clock input of the left-most FF. Answer the same question for these 4 hook-ups. J K J K J K J K J K J K J K J K J K J K J K J K 4/24/6 EE2L Class Notes - Chapter # Counters Page 2 / 8 C Copyright 26 Gandhi Puvvada

EE2L_ClassNotes_Ch_Counters_transparencies.fm J K J K J K J K J K J K J K J K J K J K J K J K The above 4 hook-ups are reproduced below with an inverter in clock input of the left-most FF. Answer the same question for these 4 hook-ups. J K J K J K J K J K J K J K J K J K J K J K J K 4/24/6 EE2L Class Notes - Chapter # Counters Page 2 / 8 C Copyright 26 Gandhi Puvvada

EE2L_ClassNotes_Ch_Counters_transparencies.fm 5 Building a toggle flip-flop using a -FF Which of the following -FF hook-ups act as a toggle FF? How do you describe the others? Which of the following -latch hook-ups act as a toggle latches!? How do you describe the others? 6 Ripple counter using -FFs In lab #4, you built a ripple counter, using negative-edge triggered JK Flip-Flops. Build a 4-bit ripple UP counter using the four -FF hookups given below. This counter shall count-up whenever the produces a positive edge. Label the four outputs R 3 R 2 R R (R is the LB. "R" stands for "ripple). To change the above design so as to make the counter to count on the negative edges of the, would you change just one of the four FFs to a negative-edge triggered FF or all the four? If one, which one? 4/24/6 EE2L Class Notes - Chapter # Counters Page 3 / 8 C Copyright 26 Gandhi Puvvada

EE2L_ClassNotes_Ch_Counters_transparencies.fm 5 Building a toggle flip-flop using a -FF Which of the following -FF hook-ups act as a toggle FF? How do you describe the others? Which of the following -latch hook-ups act as a toggle latches!? How do you describe the others? 6 Ripple counter using -FFs In lab #4, you built a ripple counter, using negative-edge triggered JK Flip-Flops. Build a 4-bit ripple UP counter using the four -FF hookups given below. This counter shall count-up whenever the produces a positive edge. Label the four outputs R 3 R 2 R R (R is the LB. "R" stands for "ripple). To change the above design so as to make the counter to count on the negative edges of the, would you change just one of the four FFs to a negative-edge triggered FF or all the four? If one, which one? 4/24/6 EE2L Class Notes - Chapter # Counters Page 3 / 8 C Copyright 26 Gandhi Puvvada

EE2L_ClassNotes_Ch_Counters_transparencies.fm 7 Ripple counter vs. ynchronous counter: You may have seen in one of the episodes of "I love Lucy". Lucy tries to dance by looking at other dancers rather than by following the beat of the drum. If the FF propagation delay is ns, then, in the case of a 32-bit ripple counter In the case of a synchronous counter design, each FF shall be prepared individually to toggle if appropriate on the tick of the next clock. 8 A synchronous counter with, LOA, and controls A A B B 3 I I I2 I I I2 Y Y BA BA B 2 * I I I2 I I I2 Y Y LOA I I I2 I I I2 Y Y * 2* 2 To build the three bit incrementer, do you need 3 full-adders or 3 half-adders? A A A B B A implify this further! NC (no connection) 4/24/6 EE2L Class Notes - Chapter # Counters Page 4 / 8 C Copyright 26 Gandhi Puvvada

EE2L_ClassNotes_Ch_Counters_transparencies.fm 7 Ripple counter vs. ynchronous counter: You may have seen in one of the episodes of "I love Lucy". Lucy tries to dance by looking at other dancers rather than by following the beat of the drum. If the FF propagation delay is ns, then, in the case of a 32-bit ripple counter In the case of a synchronous counter design, each FF shall be prepared individually to toggle if appropriate on the tick of the next clock. 8 A synchronous counter with, LOA, and controls A A B B 3 I I I2 I I I2 Y Y BA BA B 2 * I I I2 I I I2 Y Y LOA I I I2 I I I2 Y Y * 2* 2 To build the three bit incrementer, do you need 3 full-adders or 3 half-adders? A A A B B A implify this further! NC (no connection) 4/24/6 EE2L Class Notes - Chapter # Counters Page 4 / 8 C Copyright 26 Gandhi Puvvada

EE2L_ClassNotes_Ch_Counters_transparencies.fm 9 A 4-bit free-running synchronous counter Label the outputs A A A3 B B B3 3 * * 2* 2 3* 3 Instead of looking at half-adders building an incrementer, you can explain the design slightly differently. The XOR gate in front of the -FF acts like an inverter if the control input is a. Else (if the control input is a zero), it (the XOR gate) acts like a non-inverter. o basically, the control input (CTRL) is telling the - FF (through the XOR gate) whether it should be toggling on the next clock. CTRL i i Can you replace this with a 3-input and gate to improve performance? CTRL i = i-. i-2..... Make a 5-bit counter using this building block. Transitional values at the output of counters during transition all s ( ) rolling over to all s ( ), is it possible that any 6-bit number may appear at the output of the counter for a very short time during the transition? (Yes / No). oes your answer assume that the counter is a ripple counter or a synchronous counter or any of the two types? Is there any harm due to these transitional values? 4/24/6 EE2L Class Notes - Chapter # Counters Page 5 / 8 C Copyright 26 Gandhi Puvvada

EE2L_ClassNotes_Ch_Counters_transparencies.fm 9 A 4-bit free-running synchronous counter Label the outputs A A A3 B B B3 3 * * 2* 2 3* 3 Instead of looking at half-adders building an incrementer, you can explain the design slightly differently. The XOR gate in front of the -FF acts like an inverter if the control input is a. Else (if the control input is a zero), it (the XOR gate) acts like a non-inverter. o basically, the control input (CTRL) is telling the - FF (through the XOR gate) whether it should be toggling on the next clock. CTRL i i Can you replace this with a 3-input and gate to improve performance? CTRL i = i-. i-2..... Make a 5-bit counter using this building block. Transitional values at the output of counters during transition all s ( ) rolling over to all s ( ), is it possible that any 6-bit number may appear at the output of the counter for a very short time during the transition? (Yes / No). oes your answer assume that the counter is a ripple counter or a synchronous counter or any of the two types? Is there any harm due to these transitional values? 4/24/6 EE2L Class Notes - Chapter # Counters Page 5 / 8 C Copyright 26 Gandhi Puvvada

EE2L_ClassNotes_Ch_Counters_transparencies.fm Enable control Consider the following two designs. Are they both right designs? Is one of them better if you want to build a "fast" counter? A A B B * I I I2 Y * Y I I I2 2* 2 A A B B * * 2* 2 2 Truncated Counters Complete the following two incomplete designs of a truncated counter with 5 states,, 2, 3, 4, (from 4 back to ). Which is better if we want to build a "fast" counter. A A B B * I I I2 Y * Y I I I2 2* 2 A A B B * I I I2 Y * Y I I I2 2* 2 3 pecial 3-bit counter skipping,, and 2 ( 3, 4, 5, 6, 7, 3, 4, 5, 6, 7,...) Complete the following two designs. Why one of them is a "bad" design? A A B B * I I I2 Y * Y I I I2 2* 2 LOA A A B B * PRE * PRE 2* 2 4/24/6 EE2L Class Notes - Chapter # Counters Page 6 / 8 C Copyright 26 Gandhi Puvvada

EE2L_ClassNotes_Ch_Counters_transparencies.fm Enable control Consider the following two designs. Are they both right designs? Is one of them better if you want to build a "fast" counter? A A B B * I I I2 Y * Y I I I2 2* 2 A A B B * * 2* 2 2 Truncated Counters Complete the following two incomplete designs of a truncated counter with 5 states,, 2, 3, 4, (from 4 back to ). Which is better if we want to build a "fast" counter. A A B B * I I I2 Y * Y I I I2 2* 2 A A B B * I I I2 Y * Y I I I2 2* 2 3 pecial 3-bit counter skipping,, and 2 ( 3, 4, 5, 6, 7, 3, 4, 5, 6, 7,...) Complete the following two designs. Why one of them is a "bad" design? A A B B * I I I2 Y * Y I I I2 2* 2 LOA A A B B * PRE * PRE 2* 2 4/24/6 EE2L Class Notes - Chapter # Counters Page 6 / 8 C Copyright 26 Gandhi Puvvada

EE2L_ClassNotes_Ch_Counters_transparencies.fm 4 Cascading Counters: Build a 6-bit counter by cascading two 3-bit counters A A B B * I I I2 Y * Y I I I2 2* 2 A A B B 3* 3 I I I2 Y 4* 4 Y I I I2 5* 5 Try completing this alternative design and also criticize the same. A A B B * I I I2 Y * Y I I I2 2* 2 A A B B 3* 3 4* 4 5* 5 _ 4/24/6 EE2L Class Notes - Chapter # Counters Page 7 / 8 C Copyright 26 Gandhi Puvvada

EE2L_ClassNotes_Ch_Counters_transparencies.fm 4 Cascading Counters: Build a 6-bit counter by cascading two 3-bit counters A A B B * I I I2 Y * Y I I I2 2* 2 A A B B 3* 3 I I I2 Y 4* 4 Y I I I2 5* 5 Try completing this alternative design and also criticize the same. A A B B * I I I2 Y * Y I I I2 2* 2 A A B B 3* 3 4* 4 5* 5 _ 4/24/6 EE2L Class Notes - Chapter # Counters Page 7 / 8 C Copyright 26 Gandhi Puvvada

EE2L_ClassNotes_Ch_Counters_transparencies.fm 5 Fix Mr. Bruin, I mean, Mr. Bruin s design of a stop watch. This stop watch goes from : to :59 ( Min. 59 ec.) and rolls back to :. It has a CLEAR and TART/TOP controls. A A A3 B B B3 3 I I I2 I3 I I I2 I3 Y Y Y3 I I I2 I3 I I I2 I3 TART/TOP Y Y Y3 * * * 3* CLEAR 3 A A A3 B B B3 3 I I I2 I3 I I I2 I3 Y Y Y3 T* I I I2 Y T* I3 Y I I Y3 T* I2 I3 T3* T T T T3 CLEAR M 6 Timing analysis of a counter 4/24/6 EE2L Class Notes - Chapter # Counters Page 8 / 8 C Copyright 26 Gandhi Puvvada

EE2L_ClassNotes_Ch_Counters_transparencies.fm 5 Fix Mr. Bruin, I mean, Mr. Bruin s design of a stop watch. This stop watch goes from : to :59 ( Min. 59 ec.) and rolls back to :. It has a CLEAR and TART/TOP controls. A A A3 B B B3 3 I I I2 I3 I I I2 I3 Y Y Y3 I I I2 I3 I I I2 I3 TART/TOP Y Y Y3 * * * 3* CLEAR 3 A A A3 B B B3 3 I I I2 I3 I I I2 I3 Y Y Y3 T* I I I2 Y T* I3 Y I I Y3 T* I2 I3 T3* T T T T3 CLEAR M 6 Timing analysis of a counter 4/24/6 EE2L Class Notes - Chapter # Counters Page 8 / 8 C Copyright 26 Gandhi Puvvada

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